JPS634956B2 - - Google Patents
Info
- Publication number
- JPS634956B2 JPS634956B2 JP12442582A JP12442582A JPS634956B2 JP S634956 B2 JPS634956 B2 JP S634956B2 JP 12442582 A JP12442582 A JP 12442582A JP 12442582 A JP12442582 A JP 12442582A JP S634956 B2 JPS634956 B2 JP S634956B2
- Authority
- JP
- Japan
- Prior art keywords
- receiver
- wiring board
- wiring
- conductive wire
- receiving element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003287 optical effect Effects 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 10
- 239000000919 ceramic Substances 0.000 claims description 6
- 230000007257 malfunction Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は光信号を電気信号に変換する光受信器
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an optical receiver that converts an optical signal into an electrical signal.
〔発明の技術的背景〕
光受信器は、光送信器から光フアイバを介して
伝送されてくる光信号を電気信号に変換するもの
であり、PIN構造のフオトダイオードなどの受光
素子により光信号を受け、電流信号に変換し、更
にレシーバICなどにより波形調整、増幅などを
行ない所定の電圧信号を得るようになつている。[Technical Background of the Invention] An optical receiver converts an optical signal transmitted from an optical transmitter through an optical fiber into an electrical signal, and converts the optical signal into an electrical signal using a light receiving element such as a photodiode with a PIN structure. The voltage signal is received, converted into a current signal, and then subjected to waveform adjustment and amplification using a receiver IC or the like to obtain a predetermined voltage signal.
次に従来の光受信器の一例を第１図により説明
する。 Next, an example of a conventional optical receiver will be explained with reference to FIG.
即ち、出力端子６を含む外部接続端子が貫通植
設された金属ステム２上には所定の配線をなされ
たセラミツクからなる配線基板１が固定され、こ
の配線基板１上にSiのPIN構造のフオトダイオー
ドなどからなる受光素子４とレシーバIC５が載
置固定され、これら受光素子４とレシーバIC５
間はボンデイングワイヤ９1，９2と配線８からな
る導電線で接続され、またレシーバIC５と出力
端子６を含む外部接続端子間はボンデイングワイ
ヤ１０1，１０2と配線７からなる導電線で接続さ
れ、受光素子４の受光面に対設する位置に透明部
材からなる窓部３を有するシエル１１とステム２
を固定することにより内部を気密封止するように
なつている。 That is, a wiring board 1 made of ceramic with predetermined wiring is fixed on a metal stem 2 through which external connection terminals including output terminals 6 are implanted, and a photo of a Si PIN structure is mounted on this wiring board 1. A light receiving element 4 consisting of a diode etc. and a receiver IC 5 are mounted and fixed, and these light receiving element 4 and receiver IC 5 are mounted and fixed.
A conductive wire consisting of bonding wires 9 1 , 9 2 and wiring 8 connects between them, and a conductive wire consisting of bonding wires 10 1 , 10 2 and wiring 7 connects between external connection terminals including the receiver IC 5 and output terminal 6. A shell 11 and a stem 2 each have a window 3 made of a transparent material at a position opposite to the light-receiving surface of the light-receiving element 4.
By fixing it, the inside is hermetically sealed.
このような構造の光受信器の動作は、窓部３か
ら約10-7〜10-6Wの光信号が入射すると受光素子
４によつて約10-7〜10-6Aの電流信号に変換さ
れ、この電流信号はボンデイングワイヤ９1，９
２、配線８によつてレシーバIC５に入力される。
このレシーバIC５では電流信号を電圧信号に変
換、増幅しボンデイングワイヤ１０1，１０2、配
線７を通つて出力端子６から数Ｖの大きさの電圧
信号が出力される。 The operation of the optical receiver having such a structure is such that when an optical signal of about 10 -7 to 10 -6 W enters from the window 3, the light receiving element 4 converts it into a current signal of about 10 -7 to 10 -6 A. This current signal is converted to the bonding wire 9 1 , 9
2 , is input to the receiver IC 5 through the wiring 8.
The receiver IC 5 converts the current signal into a voltage signal, amplifies it, and outputs a voltage signal of several volts from the output terminal 6 through the bonding wires 10 1 and 10 2 and the wiring 7.
然るに第１図の構造ではボンデイングワイヤ９
１，９2、配線８と、ボンデイングワイヤ１０1，
１０2、配線７及び出力端子６との間の静電容量
Ｃにより誤動作や発振を起すことがある。例えば
出力端子６に出力される信号がΔt時間の間にΔν
の電圧が変化すると、ボンデイングワイヤ９1，
９2、配線８の部分にはｉ＝ＣΔν／Δtの電流が誘導
される。
However, in the structure shown in Fig. 1, the bonding wire 9
1 , 9 2 , wiring 8 and bonding wire 10 1 ,
10 2 , the capacitance C between the wiring 7 and the output terminal 6 may cause malfunction or oscillation. For example, the signal output to the output terminal 6 is Δν during the Δt time.
When the voltage of bonding wire 9 1 ,
9 2 , a current of i=CΔν/Δt is induced in the wiring 8 portion.
特に、配線７，８及び出力端子６はボンデイン
グワイヤ９1，９2，１０1，１０2よりも表面積が
大きく、配線８と配線７及び出力端子６間の静電
容量が問題となる。 In particular, the wirings 7 and 8 and the output terminal 6 have a larger surface area than the bonding wires 9 1 , 9 2 , 10 1 , and 10 2 , and the capacitance between the wiring 8 and the wiring 7 and the output terminal 6 becomes a problem.
例えばＣ＝0.01pF、Δν＝3V、Δt＝30nsとする
と、ｉ＝10-6Aとなり、受光素子４から出力され
る信号電流である10-7〜10-6Aと同程度となり、
誤動作する問題点があつた。 For example, if C = 0.01 pF, Δν = 3 V, and Δt = 30 ns, i = 10 -6 A, which is about the same as the signal current of 10 -7 to 10 -6 A output from the light receiving element 4.
There was a problem with malfunction.
本発明は前記従来の問題点に鑑みなされたもの
であり、受光素子とレシーバICとの接続部と、
レシーバICと出力端子間の接続部間の静電容量
を減少させ、誤動作を起すことのない受光信器を
提供することを目的としている。
The present invention has been made in view of the above-mentioned conventional problems, and includes a connection portion between a light receiving element and a receiver IC,
The purpose of this invention is to reduce the capacitance between the connection between the receiver IC and the output terminal, and to provide a photoreceiver that does not malfunction.
即ち、本発明は金属板またはステム上載置固定
されたそれぞれセラミツクからなる第１の配線基
板及び第２の配線基板の重層基板と、第２の配線
基板上に載置固定された受光素子及びレシーバ
ICと、一部が第１の配線基板の配線を使用する
ようになされた少くとも受光素子とレシーバIC
とを接続する第１の導電線とレシーバICの出力
を外部に取り出すために第１の配線基板に設けら
れた第２の導電線と、この第１の導電線と第２の
導電線を静電的に遮蔽するために第１の配線基板
上または第２の配線基板上の少くとも一方に設け
られた交流的に接地電位の導電体とを少なくとも
具備することを特徴とする光受信器であり、接地
電位の導電体により受光素子とレシーバICとの
導電線と、レシーバICと出力端子間の静電容量
を減少させ誤動作を起すことがないようになされ
ている。
That is, the present invention provides a multilayer substrate including a first wiring board and a second wiring board, each made of ceramic, mounted and fixed on a metal plate or a stem, and a light receiving element and a receiver mounted and fixed on the second wiring board.
an IC, at least a light receiving element and a receiver IC, some of which use the wiring of the first wiring board;
A first conductive wire connecting the first conductive wire and a second conductive wire provided on the first wiring board to take out the output of the receiver IC to the outside, and a static conductive wire connecting the first conductive wire and the second conductive wire. An optical receiver comprising at least a conductor at an alternating current ground potential provided on at least one of the first wiring board and the second wiring board for electrical shielding. A conductor at ground potential reduces the capacitance between the conductive wire between the light receiving element and the receiver IC, and between the receiver IC and the output terminal to prevent malfunctions.
次に本発明の光受信器の第１の実施例を第２図
により説明する。
Next, a first embodiment of the optical receiver of the present invention will be described with reference to FIG.
即ち、出力端子２６を含む外部接続端子が貫通
植設された金属ステム２２上にはそれぞれ所定の
プリント配線をほどこしたセラミツクからなる第
１の配線基板２１1及び第２の配線基板２１2の重
層基板が載置固定されており、この第２の配線基
板２１2上にはSiのPIN構造のフオトダイオード
からなる受光素子２４とレシーバIC２５が載置
固定され、これら受光素子２４とレシーバIC２
５はボンデイングワイヤ２９1，２９2と第２の配
線基板２１2上の配線２８とからなる第１の導電
線により接続され、またレシーバIC２５の出力
部と、出力端子２６はボンデイングワイヤ３０1，
３０2と第２の配線基板２１2上の配線２７とから
なる第２の導電線により接続され、更に配線２８
及び２７に対応する第２の配線基板２１2上、及
びレシーバIC２５に対応する第１の配線基板２
１1上にはそれぞれ交流的に接地電位の導電体３
２，３３，３４が設けられ、受光素子２４の受光
面に対設する位置に透明部材からなる窓部２３を
有するシエル３１とステム２２を固定することに
より内部を気密封止するようになつている。 That is, on the metal stem 22 through which the external connection terminals including the output terminals 26 are implanted, a first wiring board 21 1 and a second wiring board 21 2 made of ceramic each having predetermined printed wiring are layered. A substrate is placed and fixed on this second wiring board 212 , and a light receiving element 24 consisting of a Si PIN photodiode and a receiver IC 25 are placed and fixed on this second wiring board 212.
5 is connected by a first conductive wire consisting of bonding wires 29 1 , 29 2 and the wiring 28 on the second wiring board 21 2 , and the output part of the receiver IC 25 and the output terminal 26 are connected to the bonding wires 30 1 , 29 2 .
30 2 and the wiring 27 on the second wiring board 21 2 , and the wiring 28
and 27, and the first wiring board 2 corresponding to the receiver IC 25.
1 On top of each is a conductor 3 at AC ground potential.
2, 33, and 34 are provided, and the interior is hermetically sealed by fixing the stem 22 to the shell 31, which has a window portion 23 made of a transparent material at a position opposite to the light-receiving surface of the light-receiving element 24. There is.
このように接地電位の導電体３２，３３，３４
を設けることによりボンデイングワイヤ２９1，
２９2配線２８からな導電線と、ボンデイングワ
イヤ３０1，３０2配線２７からなる導電線間には
静電容量がほとんど存在しなくなり、後者に発生
する出力電圧の変化によつて前者に誘導される電
流はほぼ皆無となり極めて特性の良好な光受信器
を得ることができる。 In this way, the conductors 32, 33, 34 at ground potential
By providing the bonding wire 29 1 ,
Almost no capacitance exists between the conductive wire consisting of the 29 2 wiring 28 and the conductive wire consisting of the bonding wires 30 1 and 30 2 wiring 27, and the capacitance is induced in the former by the change in the output voltage generated in the latter. The amount of current generated is almost nil, and an optical receiver with extremely good characteristics can be obtained.
次に本発明の光受信器の第２の実施例を第３図
により説明する。図中第１の実施例と同一符号は
同一部を示し特に説明しない。 Next, a second embodiment of the optical receiver of the present invention will be described with reference to FIG. In the drawings, the same reference numerals as in the first embodiment indicate the same parts and will not be particularly described.
即ち本実施例はセラミツクパツケージ形の光受
信器であり、ステムの代りに接地電位の金属板４
２を使用し、シエル４１を板状とし、第２の配線
基板２１2の周縁に設けたセラミツクからなるス
ペーサ４３を使用している。本例の場合ボンデイ
ングワイヤ３０2がないので更に静電容量が減少
する。 That is, this embodiment is a ceramic package type optical receiver, and a metal plate 4 at ground potential is used instead of the stem.
2, the shell 41 is plate-shaped, and a spacer 43 made of ceramic is provided around the periphery of the second wiring board 212 . In this example, since there is no bonding wire 302 , the capacitance is further reduced.
前記実施例では受光素子２４とレシーバIC２
５間の導電線の配線２８と、レシーバIC２５と
出力端子２６間の導電線の配線２７に対設する第
２の配線基板２１2上に接地電位の導電体３２，
３３を設けたがこれは導電体３２のみでも良いこ
とは勿論である。 In the above embodiment, the light receiving element 24 and the receiver IC 2
A conductor 32 at ground potential is disposed on the second wiring board 212 opposite to the conductive wire wiring 28 between the receiver IC 25 and the output terminal 26, and the conductive wire wiring 27 between the receiver IC 25 and the output terminal 26.
Although the conductor 33 is provided, it goes without saying that only the conductor 32 may be used.
上述のように本発明によれば、受光素子とレシ
ーバIC、レシーバICと出力端子間に静電容量の
発生が極めて少なく、特性の良好な光受信器を得
ることが可能であり、その工業的価値は極めて大
である。
As described above, according to the present invention, it is possible to obtain an optical receiver with excellent characteristics in which the generation of electrostatic capacitance between the light receiving element and the receiver IC, and between the receiver IC and the output terminal is extremely small. The value is extremely great.
第１図は従来の光受信器の説明用断面図、第２
図は本発明の光受信器の第１の実施例の説明用断
面図、第３図は本発明の光受信器の第２の実施例
の説明用断面図である。
１，２１1，２１2…配線基板、２，２２…ステ
ム、３，２３…窓部、４，２４…受光素子、５，
２５…レシーバIC、６，２６…出力端子、７，
８，２７，２８…配線、９1，９2，１０1，１０
２，２９1，２９2，３０1，３０2…ボンデイングワ
イヤ、１１，３１，４１…シエル、３２，３３，
３４…接地電位の導電体。
Figure 1 is an explanatory cross-sectional view of a conventional optical receiver;
The figure is an explanatory cross-sectional view of a first embodiment of the optical receiver of the present invention, and FIG. 3 is an explanatory cross-sectional view of a second embodiment of the optical receiver of the present invention. 1, 21 1 , 21 2 ... wiring board, 2, 22 ... stem, 3, 23 ... window section, 4, 24 ... light receiving element, 5,
25... Receiver IC, 6, 26... Output terminal, 7,
8, 27, 28...Wiring, 9 1 , 9 2 , 10 1 , 10
2 , 29 1 , 29 2 , 30 1 , 30 2 ... bonding wire, 11, 31, 41 ... shell, 32, 33,
34...A conductor at ground potential.
Claims (1)
と、この第１の配線基板の他方の面に積層された
第２の配線基板とからなるセラミツク重層基板
と、 前記第２の配線基板上に載置固定された受光素
子とレシーバICと、 前記第１の配線基板の前記他方の面に設けられ
た、前記受光素子と前記レシーバICとを接続す
るための第１の導電線及び前記レシーバICの出
力を外部に取り出すための第２の導電線と、 前記第１の導電線及び前記第２の導電線の少な
くとも一方に対応して前記第２の配線基板上、及
び前記第１の導電線と前記第２の導電線との間で
前記第１の配線基板上の、少なくとも一方に配置
された交流的に接地電位の導電体とを、 具備することを特徴とする光受信器。[Claims] 1. A ceramic multilayer board consisting of a first wiring board on which a conductor is arranged on one surface, and a second wiring board laminated on the other surface of the first wiring board; A light receiving element and a receiver IC mounted and fixed on the second wiring board, and a first wiring board provided on the other surface of the first wiring board for connecting the light receiving element and the receiver IC. a second conductive wire for taking out the output of the receiver IC to the outside; and a second conductive wire on the second wiring board corresponding to at least one of the first conductive wire and the second conductive wire. , and a conductor having an AC ground potential placed on at least one side of the first wiring board between the first conductive wire and the second conductive wire. optical receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57124425A JPS5916385A (en) | 1982-07-19 | 1982-07-19 | Photo receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57124425A JPS5916385A (en) | 1982-07-19 | 1982-07-19 | Photo receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5916385A JPS5916385A (en) | 1984-01-27 |
| JPS634956B2 true JPS634956B2 (en) | 1988-02-01 |
Family
ID=14885163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57124425A Granted JPS5916385A (en) | 1982-07-19 | 1982-07-19 | Photo receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5916385A (en) |
-
1982
- 1982-07-19 JP JP57124425A patent/JPS5916385A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5916385A (en) | 1984-01-27 |
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