JPS6348993Y2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field The present invention relates to a counter and a shift register using a D flip-flop, and particularly to a counter suitable for a DA converter.

(b) Prior art In general, AD converters, as shown in Figure 1,
It is composed of a comparator 1, an RS flip-flop 2, a clock oscillator 3, a counter 4, a DA converter 5, a gate circuit 6, a shift register 7, and a control circuit 8, and includes an analog voltage Vi to be converted and an output voltage V of the DA converter 5. ₀ is input to the inverting input terminal and non-inverting input terminal of comparator 1, respectively. First, when the conversion start signal ST is generated from the control circuit 8, the counter 4 and the RS flip-flop 2 are reset, the clock oscillator 3 starts oscillating, and the counter 4 counts the counter clock CL and its contents are Rise. The contents of the counter 4 are converted into an analog voltage _V0 by the DA converter 5, and when this voltage _V0 slightly exceeds the input analog voltage Vi, the output C of the comparator 1 becomes "H" and the RS flip-flop 2 is set. . Therefore, the Q output becomes "H" and the oscillation of the clock oscillator 3 stops, and the contents of the counter 4 stop when the output voltage _V0 of the DA converter 5 and the input analog voltage Vi become almost equal. . That is, the counter 4 obtains a digital signal corresponding to the input analog voltage Vi. Then, the "H" Q output of the RS flip-flop 2 is given to the control circuit 8 as a conversion end signal END. Therefore, the control circuit 8
By applying the signal G to the gate circuit 6,
Transfer the contents of counter 4 to shift register 7. Furthermore, the control circuit 8 applies a shift clock CK to the shift register 7, and the shift register 7
The contents transferred from counter 4 are serial data.
Output as SD.

(c) Disadvantages of conventional technology In conventional AD converters, although the configurations are very similar, the counter and shift register are provided separately, which increases the number of elements and is uneconomical. However, there is a drawback that a transfer time is required to transfer the counter data to the shift register, and therefore, the time required to read the converted digital data becomes longer.

(d) Purpose of the invention In order to eliminate the above-mentioned drawbacks, the present invention provides a novel counter that also operates as a shift register in response to a switching signal by combining a D flip-flop and a logic gate.

(E) Embodiment FIG. 2 is a circuit diagram showing an embodiment of the counter according to the present invention, and shows a case where the counter is applied to an AD converter. Note that the same components as in FIG. 1 are given the same numbers.

In Fig. 2, 9 is a 4-bit shift register counter according to the present invention, and 4 D
Flip-flop 10a, 10b, 10c, 10
It has d. The D flip-flops 10b, 10c, and 10d of each stage except the first stage are first AND gates 11b, 1, which receive the Q output of the previous stage and the inverted signal of the switching signal C/S from the control circuit 8.
1c, 11d, output of the relevant stage and switching signal C/S
The second AND gates 12b, 12c, 1 input
2d, the third AND gate 13b, 13c, 13d, which inputs the output of the previous stage and the switching signal C/S;
Input the output of 1AND gate and 2nd AND gate,
The first OR gates 14b, 14c, 14d whose output terminals are connected to the data input terminal D of the stage concerned,
A second OR gate 15b, 1 inputs the output of the 3AND gate and the shift clock CK from the control circuit 8.
5c and 15d are provided. Also, first stage D
First AND gate 11a of flip-flop 10a
The third AND gate 13a receives the ground input instead of the output of the previous stage, and the counter clock from the clock oscillator 3 instead of the output of the previous stage.
CL is input, and other logic gates 12a,
14a and 15a are the same as the logic gates of each stage.

Therefore, when the conversion start signal ST is generated, all the D flip-flops 10a and 10 of the counter 9 are activated.
b, 10c, 10d and RS flip-flop 2
is reset, the RS flipflop 2
The Q output of becomes "L", the conversion end signal END of "L" is input to the control circuit 8, and the switching signal C/S
is set to "H". Therefore, inverter 1
6 becomes "L", and the data input terminals D of the D flip-flops 10a, 10b, 10c, 10d of each stage are connected to the second AND gates 12a, 1, respectively.
2b, 12c, 12d and the first OR gate 14a,
The output of the relevant stage is input via 14b, 14c, and 14d. That is, the D flip-flops in each stage operate as T flip-flops. Further, the clock input terminals φ of each stage except the first stage are connected to third AND gates 13b, 13c, and 13, respectively.
The output of the previous stage is inputted via d and second OR gates 15b, 15c, and 15d. moreover,
When the RS flip-flop 2 is reset, the clock oscillator 3 starts oscillating, and the counter clock CL is input to the clock input terminal φ of the first-stage D flip-flop 10a via the third AND gate 13a and the second OR gate 15a. Ru. That is, T flip-flops made up of D flip-flops are connected in cascade, and the counter clock CL is input to the T flip-flop at the first stage, so that it operates as a counter.

The Q output of each D flip-flop 10a, 10b, 10c, 10d operating as a counter is
It is converted into an analog voltage V ₀ by the DA converter 5 and compared with the input analog voltage Vi. And when the output voltage V ₀ slightly exceeds the input analog voltage Vi,
Output C of comparator 1 becomes "H" and RS flip-flop 2 is set. Therefore, the counter clock CL stops and the conversion end signal END of "H" is input to the control circuit 8.
The control circuit 8 changes the switching signal C/S from "H" to "L"
At the same time, the shift clock CK is generated.

When the switching signal C/S becomes "L", the output of the inverter 16 becomes "H", and the clock input terminals φ of the D flip-flops 10a, 10b, 10c, and 10d of each stage are connected to the second OR gates 15a, 15a, and 15b, respectively.
Shift clock via 15b, 15c, 15d
CK is input, and the first stage data input terminal D is
The ground input is connected via the 1AND gate 11a and the first OR gate 14a, and the data input terminal D of each stage except the first stage is connected to the first AND gate 11.
b, 11c, 11d and the first OR gate 14b,
The Q output of the previous stage is inputted via 14c and 14d. That is, the D flip-flops in each stage are connected in cascade, and the shift clock CK is commonly input to the clock input terminal φ of each stage, so that the D flip-flops operate as a shift register. Then, digital data corresponding to the input analog voltage Vi is outputted as serial data SD from the Q output terminal of the final stage D flip-flop 10d in accordance with the shift clock CK.

(f) Effects As mentioned above, the counter according to the present invention can be operated as a shift register in response to a switching signal by simply combining a D flip-flop with a logic gate. In comparison, the number of elements can be reduced, and since the same D flip-flop is used as both a counter and a shift register, there is no need for transfer time from the counter to the shift register, and therefore reading of converted data is It saves time and is ideal for AD converters.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a general AD converter, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. Explanation of main drawing numbers, 1... Comparator, 2...
RS flip-flop, 3...clock oscillator,
4... Counter, 5... DA converter, 6... Gate circuit, 7... Shift register, 8... Control circuit, 9 ... Counter, 10a, 10b, 10c,
10d...D flip-flop, 11a, 11
b, 11c, 11d... 1st AND gate, 12
a, 12b, 12c, 12d...second AND gate, 13a, 13b, 13c, 13d...second
3AND gate, 14a, 14b, 14c, 14d
... 1st OR gate, 15a, 15b, 15c,
15d...second OR gate, 16...inverter.

Claims (1)

[Scope of utility model registration request] A plurality of stages of D flip-flops, a first AND gate that receives the Q output or input signal of the previous stage of each stage of the D flip-flop and an inverted signal of the switching signal, and inputs the output of the relevant stage and the switching signal. a second AND gate that inputs the output of the previous stage or the counter clock and the switching signal, and a third AND gate that inputs the outputs of the first and second AND gates and has an output terminal. a first OR gate connected to the data input terminal of the relevant stage; and a second logic circuit which inputs the output of the third AND gate and the shift clock, and whose output terminal is connected to the clock input terminal of the relevant stage. a sum gate, and is operable as a shift register in response to the switching signal.