JPS62164315A - Da converter - Google Patents

Abstract

PURPOSE:To make the error in the vicinity of a central value into zero by providing a gate circuit in which the upper-most digit (MSB) of digital data is '1', the high level division of the output of a pulse width modulating (PWM) circuit or MSB is '0', the MSB of the digital data is outputted to the low level division of the output of the PWM circuit and at the division except for it, the output comes to be a high impedance. CONSTITUTION:When a reference voltage source 20 is selected to about 1/2 of an electric power source voltage 23 of a gate circuit and input digital data 1 is larger than a central value, MBS=1 is obtained, and for the average direct current voltage of a PWM signal determined by the value except for the MSB of the input digital data, the value can be obtained from the voltage of a reference voltage source up to the electric power source voltage by the digital data. Reversely, when the input digital data are smaller than the central value, in the same manner, the average direct current voltage of the PWM signal can be obtained from 0V up to the voltage of the reference voltage source. When the input digital data are the central value, MSB=1 is obtained, the lower order value is wholly '0', and therefore, the value is equal to the voltage of the reference voltage source.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a DA that converts digital data into analog voltage.
It concerns converters.

Conventional technology One of the conversion technologies used in conventional DA converters is
Pulse width modulation (hereinafter referred to as PWM) compatible with digital data
There is a method of outputting a signal (called .) and smoothing it. For example, an example thereof is shown in Japanese Patent Application Laid-Open No. 57-204631 entitled "Pulse Width Modulation Circuit", and its schematic diagram and operation will be explained with reference to the drawings.

FIG. 5 is a diagram showing a conventional example of a DA converter using PWM, and FIGS. 6 and 7 are diagrams for explaining its operation.

In FIG. 5, an n-bit binary counter 39 counts the input clock 38 and outputs a count output 37 and an overflow signal '5' a at the time of overflow.

Outputs . - The number circuit 36 compares the output 37 of the n-bit binary counter 39 with the n-bit manual data 35, and outputs a pulse to the output terminal 41 when the re-inputs match. The flip-flop 43 is clocked by the overflow output 40 of the n-bit binary counter 39 to set the output terminal 44 to a high level, and is reset by the defeat output 41 of the - number circuit 36 to set the output terminal 44 to a low level. At this time, the output high level of the output terminal 44 is from the flip-flop 4.
3, the voltage V of the power supply 42. It becomes 0. Therefore, the period in which the output terminal 44 of the flip-flop 43 is at a high level is equal to the time during which the n-bit binary counter 39 counts by the number of clocks 38 that is equal to the n-bit input data 35, and the period in which the output terminal 44 of the flip-flop 43 is at a high level is The level corresponds to an interval excluding the interval in which the output terminal 44 becomes high level from the clock number 2° of the clock 38 at which the n-bit binary counter 39 overflows. Therefore, flip-flop 43
As shown in FIG. 6, the output signal 47 of the output terminal 44 of the output terminal 44 has a high level equal to the voltage V of the power supply 42. . , (48), the low level is 0V (49), and the high level section e is n
This is the time during which the bit binary counter 39 counts the number of clocks of the clock 38 until it becomes equal to the n-bit input data 35.

Output signal 4 of output terminal 44 of this flip-flop 43
7, the DC average voltage is expressed as DC average voltage = vcc ·- using e in FIG. 6 and the overflow period of the n-bit binary counter 39, and the high level section e is the n-bit input. It is proportional to the data, and P is proportional to the n-bit input data.
It becomes a WM signal. The filter 45 is a flip-flop 43
The output signal 47 of the output terminal 44 of the filter 45 is smoothed and the average voltage is outputted to the output terminal 46 of the filter 45.
An output voltage whose maximum value is the voltage vCc of the voltage s42 is generated. That is, the DA output 50 shown in FIG. 7 is outputted to the output 46 of the filter 45, and operates so that an analog voltage corresponding to n-bit input data is outputted to the output terminal 46.

Problems to be Solved by the Invention A conventional DA converter is configured as shown in Fig. 5, but the output of this DA converter and the data deviation from the median value (2 torr for n-bit input data) are When detecting with an analog voltage, for example, as shown in FIG.
2 (55) and stabilized with capacitor C1 (56), this ■. . This was done by taking the differential voltage between the terminal 57 that generates /2 and the DA output 46. In this case, resistors R154 and R255 actually have an error of 2-3%, and at Voo=SV, the V given in FIG. 8 is compared to the exact value of vcc/2. o/2 is 100
Errors of mV to 150 mV were common.

Therefore, it is very difficult to accurately obtain an analog voltage corresponding to the deviation of the actual n-bit input data value from the median value of the n-bit input data, which is a problem.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides the most significant digit (hereinafter referred to as MSB) of input digital data.
A PWM circuit that generates a pulse width modulated output according to the lower digit data except for the input digital data M
The configuration is such that the MSB of digital data is output in the high level section of the output of the PWM circuit when SB is 1 or the low level section of the output of the PWM circuit when MSB is 0, and the output becomes high impedance during other times. a gate circuit, a reference voltage source, a resistor connected between the gate circuit output terminal and the reference voltage source, and a filter for smoothing a PWM signal generated at the resistor. did.

Effect With the above configuration, if the reference voltage source is selected to be approximately 1/2 of the power supply voltage of the gate circuit, when the input digital data is greater than the median value, MBS = 1, and the input digital data. The average DC voltage of the PWM signal, which is determined by values other than the MSB, can take values from the reference voltage to the power supply voltage using digital data. Conversely, when the input digital data is smaller than the median value, the average DC voltage of the PWM signal can take values other than the MSB of the input digital data from 0 to the voltage of the base voltage source.

When the input digital data is the median value, MSB = 1 and all lower values are 0, so the PWM output has no high level section and is the gate circuit output of the resistor connected between the gate circuit and the reference voltage source. The voltage at the end will be equal to the voltage of the reference voltage source.

Therefore, if this reference voltage source is used as an analog voltage corresponding to the median value of the input digital data,
The DA converter output obtained by smoothing the signal at the connection terminal of the resistor with the gate circuit output end with a filter becomes completely equal when the input digital data is a median value.

Therefore, an analog voltage corresponding to the deviation of the actual input data value from the median value of the possible values of the input digital data can be obtained accurately, and the conventional problems are solved.

Embodiment FIG. 1 is a book diagram showing an embodiment of the DA converter of the present invention. In FIG. 1, ■ is n-bit input digital data, and data other than the MSB are input to one input terminal group of the one-loss circuit 2.

5 is an n-1 bit binary counter which receives clock 3, counts the clock, outputs overflow output 6 and counting output 4, and sends counting output 4 to the other input terminal of matching circuit 2. The overflow output 6 is also input to the flip-flop 8. 2 is a coincidence circuit, which has an n-1 bit binary counter 5 and an n-bit input data 1.
A pulse is generated at the output terminal 7 when the lower digits except the MSB of 8 is a flip-flop, n-1
An overflow output from the bit binary counter 5 is used to set the output terminal 11 at a high level, and a match output 7 from the minus number circuit 2 resets the output terminal 11 at a low level. )n 1-bit binary counter 5, -number circuit 2. The flip-flop 8 constitutes a PWM circuit 10,
- The period is the overflow period of the n-1 bit binary counter 5, that is, the time when the clock 3 generates 2 rl-1 clocks, and the high level is the n-bit input data 1.
A PWM signal is generated at the output terminal 11, which is equal to the time it takes for the n-1 bit binary counter to count the number of clocks 3 given by the lower digit data excluding the MSB. Further, in FIG. 1, 18 is a gate circuit, and AND circuits 14.
15, inverter 12, 13, OR circuit 16, high level, low level.

It is composed of a three-state buffer (hereinafter referred to as a tri-state buffer) that can take a high impedance state, and receives the output II of the PWM circuit 10 and the MSB of n-bit input data.

No. 23 is the power supply supplied to the gate circuit 18, and its voltage is ■. . In the gate circuit 18, the MSB of n-bit input data is sent to the inverter 12 and the AND circuit 1.
5 is connected to each input terminal of the tri-state buffer 17, and the output of the PWM circuit 10 is connected to the AND circuit 1.
The other input of the inverter 5 is connected to each input terminal of the inverter 13. The outputs of the inverters 12 and 13 are both input to the AND circuit 14, the outputs of the AND circuits 14 and 15 are input to the OR circuit 16, and the output of the OR circuit 16 is connected to the gate terminal 17G of the tri-state buffer. When this gate terminal 17G is at a high level, the tri-state buffer 17 receives the MS of n-bit input data.
B is output to its output terminal 17F, and when the gate terminal 17G is at a low level, the tri-state buffer 17 operates so that its output becomes high impedance. The output terminal 17F of the output terminal 17 of this tri-state buffer 17 is also the output terminal of the gate circuit 18, and the gate terminal 17G
is at a high level and the MSB of n-bit input data is at a high level, the voltage of the power supply 23 is applied to the output terminal 17F. 0 is output, and if the terminal 17C; is high level and the MSB of n-bit input data is low level, the output terminal 17F is 0.
is output. If the gate terminal 17G is at a low level, the output terminal 17F is at high impedance. Further, a reference voltage source 20 of power supply voltage V is connected to the output terminal 17F of the gate circuit 18 via a resistor 19, and when the output terminal of the tri-state buffer 17 is in high impedance, the voltage of the terminal 17F is set to V. , set to . Terminal 17F is also input to filter 21, causing the output terminal 22 of filter 21 to output a smoothed DA ratio output.

The embodiment shown in FIG. 1 has the above configuration. For example, when the MSB of n-bit human data is 1, the PWM circuit I
O is output to the PWM output terminal 11 corresponding to the lower data excluding the MSB of the n-bit input data, but the high level of this PWM output means that the inputs of the AND circuit both become high level, and the output is sent to the gate terminal via the OR circuit 16. 17G is set to high level, and the MSB of tristate buffer 17 is set to 1.
Therefore, the power supply voltage is V. 0 is output to the output terminal 17F.

Conversely, if the output of the PWM circuit 10 is low level, the gate terminal 17G is low level and the output of the tristate buffer 17 is high impedance, so the terminal 17F is the voltage V of the reference voltage source 20.

become. FIG. 2 shows the above change state of the terminal 17F when the MSB is 1, and the voltage change of the terminal 17F is based on the voltage VcC25 of the power supply 23 of the gate circuit as shown in FIG. 24. Voltage #I20 voltage v326 2
Takes the street value. Of course, as mentioned above, the interval a in FIG. 2 corresponds to the output high level interval of the PWM circuit IO, and the interval in FIG. 2 corresponds to the overflow period ( In other words, it corresponds to the time required for the counter to count 20-1 clocks of clock 3). Therefore, when all the lower data except the MSB of n-bit input data is zero, the section a in FIG. 2 is zero and the voltage at the terminal 17F is always equal to the voltage V of the reference voltage source 20, When all lower-order data excluding is 1, the second
Section a in the figure is the longest, and the voltage 24 at terminal 17F is v3.
This is only for one clock of clock 3, and the remaining section is all V. becomes equal to C. Since the voltage at terminal 17F is smoothed by filter 21 and made into an average DC voltage, D
At the A output terminal 22, an A output as shown in FIG. 4 is obtained. In FIG. 4, the horizontal axis 34 is the value of n-bit input data, and when it is MSB-1, the input data is larger than 1/2 (2 bits) of the maximum value (2"-1) that the input data can change. ! or more), and the average voltage is from vs to v
cc, and the DA ratio output shown in FIG. 4, 32, is obtained.

Also, when the MSB of the n-bit input data in FIG. 1 is 0,
The output of AND circuit 15 is always low level, AND circuit 1
4 is an inverter only when the output terminal 11 of the PWM circuit 10 is at a low level, and the input terminals through 13 are both at a high level, and the gate terminal 17F is at a high level through an OR circuit 16, MSB (=O). Therefore, output terminal 1?
Set F to OV. When the output of the PWM circuit IO is at a high level, the output of the tri-state buffer 17 becomes high impedance, so that the reference voltage V of the reference power supply 20.

is equal to i.e. terminal 17 for MSB or zero.
The voltage waveform of F takes two values, Ov and ■3, as shown in FIG.
The period d corresponds to the overflow period of the n-1 bit binary counter 5. If this MSB=O, n-bit manual data 1
The time interval C in which all bits of It becomes shorter. The interval C at this time corresponds to one cycle of the clock 3.

Therefore, when the MSB of n-bit input data 1 is zero, the average value of the voltage generated at terminal 17F is Ov when n-bit input data 1 is zero, and as the data increases, the average voltage also increases. The data grows in proportion to the data up to 21+1. Since this average voltage is generated at the output of the filter 21, that is, the DA output terminal 22, as shown in 31 shown in FIG. A voltage of up to 100% will be generated.

Effects of the Invention As can be seen from FIG. 4, the DA output terminal of the embodiment of FIG. 1 becomes completely equal to the reference voltage source voltage V5 at the variable median value of the input digital data, The deviation between the value and the median value of the digital data is exactly the base i! This is represented by an analog voltage between the L voltage source voltage vs and the DA output, and the problems described in the conventional example are completely solved. Therefore, according to the present invention, the analog voltage corresponding to the difference between the changeable median value of the input digital data and the actual input digital data has a DA with zero error around the median value. This makes it possible to realize a converter, and its utility value is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG.
The figure is an operating waveform diagram of Figure 1, Figure 4 is a characteristic diagram explaining the output characteristics of Figure 1, and Figure 5 is a conventional 1... digital data, 10... PWM Circuit, 18...
...Gate circuit, 19...Resistor, 20...
...Reference voltage source, 21...Filter. Name of agent Patent attorney Toshio Nakao (1 person) Figure 2 Figure 3 Figure 6 Figure 7 Input data

Claims (1)

[Claims] Digital data consisting of multiple binary data is input,
a pulse width modulation circuit that generates a pulse width modulated output according to lower digit data excluding the most significant digit of the digital data, and an output of the pulse width modulation circuit when the most significant digit of the digital data is 1; or the most significant digit is 0 and the most significant digit of the digital data is output in the low level section of the output of the pulse width modulation circuit, and the output is high in the output section of the pulse width modulation circuit other than the above. a gate circuit configured to have an impedance, a reference voltage source, a resistor connected between the gate circuit output terminal and the reference voltage source, and a pulse width modulated signal generated in the resistor. Equipped with a filter that smoothes the
A DA converter characterized in that the filter output is output as an analog signal output.