JPS6348929A - Synchronizing pattern detecting device - Google Patents

Abstract

PURPOSE:To attain the sure detection of a synchronizing pattern by providing a window circuit, a missing detection circuit, an error detection circuit and an adder circuit or the like so as to control a threshold value in response to the quality of an input data signal. CONSTITUTION:+, - Patterns of a data signal via a shift register 10 are detected by +, - pattern detection circuits 11, 12, +, - synchronizing patterns are processed by a differential circuit 13, from which a differential output is compared with the threshold value by a comparator 14 to detect a synchronizing pattern inserted in the data signal. On the other hand, the output of the circuit 14 and the output of the window circuit 15 giving the output of a signal with a prescribed interval are compared respectively by missing/error detection circuits 16, 17 thereby decreasing/increasing the threshold value of the circuit 14 via the adder circuit 18 in response to the result and frequency of comparison. Thus, even if the pattern missing or mis-detection of a data as a synchronizing pattern takes palce, the synchronizing pattern is detected surely.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization pattern detection device used for data communications and the like.

(Prior Art) FIG. 3 shows the configuration of a conventional synchronization pattern detection device. In FIG. 3, 1 is a signal input terminal, which is connected to the shift register 2. In FIG. This shift register 2 is
(+) pattern detection circuit 3 and (-) pattern detection circuit 4
Be connected to. Further, the (+) pattern detection circuit 3 and the (-) pattern detection circuit 4 are connected to a differential circuit 5,
This difference 1+ circuit 5 is connected to a comparison circuit 6. Further, this comparison circuit 6 is connected to a synchronization pattern output terminal 8 and a threshold level setting terminal 7.

Next, the operation of the above conventional example will be explained. A data signal including the synchronization pattern shown in FIG. 4 (1) is applied to the signal input terminal 1 shown in FIG. 3 and guided to the shift register 2. Of these, only the (+) synchronization pattern is guided to the (+) pattern detection circuit 3, and a signal proportional to the matched value of the (+) pattern is sent to the differential circuit 5. This signal is shown in Part 4 (2). Further, the synchronization pattern (-) is also sent to the differential circuit 5 through the same processing as above. This waveform is shown in FIG. 4 (3). The differential circuit 5 takes the difference between the above signals and sends it to the comparison circuit 6. This waveform is shown in Figure 4 (4).
Shown below. The comparison circuit 6 compares the differential circuit output with the threshold level setting signal, and outputs the result to the synchronization pattern output terminal 8. This signal is shown in FIG. 4 (5).

In this way, even with the conventional synchronization pattern detection device described in Section 2,
Synchronization patterns embedded within the data signal can be detected.

(Problems to be Solved by the Invention) However, in the above-mentioned conventional synchronization pattern detection device,
If an error occurs in the line and a bit error occurs in the synchronization pattern, or conversely, if a pattern with a very similar synchronization pattern occurs in the data, an incorrect
There was a problem with outputting No. 3. That is, there is a problem when a synchronization signal is not present at a time when a synchronization signal should be present, or when a synchronization signal is present at a time when a synchronization signal should not be present.

The present invention is intended to solve such conventional problems, and aims to provide an excellent synchronization pattern detection device that can detect synchronization patterns more reliably in any of the above cases.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a window circuit, an omission detection circuit, an error detection circuit, and an addition circuit, and performs one-to-one processing according to the A and No. 1 quality of the human-powered data signal. The threshold level is controlled. To this end, the synchronous pattern detection device of the present invention includes a shift register that sequentially shifts the input signal, and a (+) shift register of the input signal by this shift register.
and a pattern detection circuit that detects the (-) pattern;
A differential circuit that takes the difference between the (+) and (-) patterns of this pattern detection circuit, a comparison circuit that compares the signal of this differential circuit with a threshold, and an output signal from this comparison circuit that generates a signal at regular intervals. a window circuit that outputs a signal, and a direct current signal that is proportional to the frequency of a signal that detects the absence of a signal where a signal should exist by comparing the output signal of the comparison circuit and the output of the window circuit. a loss detection circuit that compares the output signal of the comparison circuit with the output signal of the window circuit, and detects that a signal is present in a place where the signal should not be present.The DC signal is proportional to the frequency of the signal. A transmitting error detection circuit and an addition circuit that adds and subtracts the signals output from the omission detection circuit and the error detection circuit are provided, and the threshold level of the comparison circuit is controlled to more reliably detect the synchronization pattern. It is something.

(Function) Therefore, according to the present invention, the threshold level of the comparison circuit is changed depending on the case where the detection of a synchronization pattern is missing and the case where the same pattern is mistakenly detected as a synchronization pattern when it should not be present. In either case, the synchronization pattern can be detected more reliably.

Further, according to the present invention, the threshold level can be optimized by controlling it with a DC signal proportional to the frequency of omissions or errors.

(Example) FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 9 is a signal input terminal, which is connected to a shift register 10. In FIG. The shift l-register 10 is (+
) pattern detection circuit 11 and (-) pattern detection circuit 12
These outputs are also connected to the inputs of the differential circuit 13. The output of this differential circuit 13 is connected to one input of a comparison circuit 14.

The output of the adder circuit 18 is connected to the other input of the comparator circuit 14 . Further, the output of the comparison circuit is connected to the synchronous pattern output terminal 20 and the wind circuit 15,
The output of the window circuit 15 is connected to the input of the omission detection circuit 16 and the input of the error detection circuit 17.

The output of the comparison circuit 14 is also connected to the input of the omission detection circuit 160 and the error detection circuit 17. Further, the output of the omission detection circuit 16, the output of the error detection circuit 17, and the threshold level setting terminal 19 are connected to the input of the addition circuit 18.

Next, the operation of the above embodiment will be explained. In the above embodiment, the steps up to the output of the differential circuit 13 are the same as those in the conventional example, so explanation thereof will be omitted. Now, the comparison circuit 14 compares a certain threshold temporarily set based on experience with the output of the differential circuit 13, and the result is shown in FIG. 2 (1). From this signal, the window circuit 15 outputs A and No. 1 as shown in (2) of the same figure.
Create with. The signal generated by this window circuit 15 (2
) and the output signal (1) of the differential circuit, the missing detection circuit 16
The missing signal shown in FIG. 3(3) is detected, and a DC signal corresponding to the frequency of the detected signal is sent to the adder circuit 18. Similarly, from the above signals (1) and (2), the error detection circuit 17 detects the error synchronization pattern (
A synchronization pattern and π(ru) are detected from the data, and a DC signal proportional to the frequency of the detected signal is sent to the adder circuit 18.

Then, in the adder circuit 18, a certain threshold level setting terminal 1 is set.
The output of the error detection circuit 17 is added to
4 ((5) in FIG. 2).

In this way, if the threshold level input to the comparison circuit 14 is too high and a synchronization signal is lost, the threshold level is lowered, and conversely, if the threshold level is too low and data is mistakenly detected as a synchronization signal, the threshold level is lowered. operates to raise the threshold level, so it is always controlled to an optimal threshold level that does not cause synchronization signal loss or error detection.

(Effects of the Invention) As is clear from the above embodiments, the present invention lowers the threshold of the comparison circuit when a synchronization pattern is missing;
This method has the advantage that when data is mistakenly detected as a synchronization pattern, the threshold value can be raised to reliably detect the synchronization pattern.

That is, the present invention has the advantage that the threshold value can be controlled using a DC signal proportional to the respective frequencies of omissions and errors in the synchronization pattern, so that the synchronization pattern can always be detected using the optimal threshold value.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, and FIG. 3 is a schematic block diagram of a synchronization pattern detection device in a conventional synchronization pattern detection device. FIGS. 2 and 4 are diagrams showing waveforms of each part to explain their operations. 1... Signal input terminal, 2... Shift register,
3...(+) pattern detection circuit, 4...(-) pattern detection 1 path, 5...differential circuit, 6...comparison circuit, 7...threshold level setting terminal, 8...・Sync pattern output terminal, 9...signal input terminal, lO...
・Shift 1 register, 11・(+) pattern detection circuit, 12・(−) pattern detection circuit, 13・differential circuit, 14・comparison circuit, 15・window circuit, 16・- Missing detection circuit, 17... Error detection circuit, 18... Addition circuit, 19... Threshold level setting terminal, 20... Synchronization pattern output terminal. . -1 2nd Ward Lock Gate ζ 1. 5. ' -7-7---1 Figure 3 Figure 4 (5).

Claims (1)

[Claims] A shift register that sequentially shifts the input signal, a pattern detection circuit that detects (+) and (-) patterns of the input signal using this shift register, and a difference between the (+) and (-) patterns of this pattern detection circuit. a differential circuit, a comparison circuit that compares a signal of the differential circuit with a threshold, a window circuit that outputs signals at regular intervals based on an output signal from the comparison circuit, and an output signal of the comparison circuit and the window circuit. a loss detection circuit that compares the output signals of and sends out a DC signal proportional to the frequency of the signal that detects that the signal is absent where the signal should exist, and the output signal of the comparison circuit and the output signal of the window circuit. an error detection circuit that sends out a DC signal proportional to the frequency of the signal that detects the presence of a signal in a place where the signal should not exist; A synchronization pattern detection device includes an adder circuit that adds and subtracts signals respectively, and controls the threshold level of a comparison circuit to more reliably detect a synchronization pattern.