JPS63164768A - Clamp circuit - Google Patents

Abstract

PURPOSE:To surely attain DC level recovery immune to noise in a short time by generating a clamp voltage similar to a part or all of horizontal reference signals included in an input picture signal so as to operate switching at a part or all periods of the horizontal reference signal. CONSTITUTION:A reference amplitude detection circuit 7 detects the reference amplitude from the horizontal reference signal component of the signal subjected to A/D conversion. A pattern generating circuit 8 generates a signal similar to the horizontal reference signal and the level difference of the flat portion of the signal is controlled to be the same as the detected reference amplitude. A picture signal changes between two flat portions during the horizontal reference signal period, the pattern generating circuit 8 generates a waveform similar to the horizontal reference signal and the result is fed to a switch circuit 4 via a D/A converter 9, then the potential difference of the outputs between the D/A converter 9 and a buffer circuit 1 hardly includes the change component of the horizontal reference signal. Thus, the switch circuit 4 is conductive during the horizontal reference signal period and sure clamping is applied in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clamp circuit for a so-called positive polarity synchronization type reproducing device that adds a horizontal reference signal, that is, a synchronization signal, and a DC reproduction reference signal to an image signal with the same polarity and transmits the same. It is related to.

2. Description of the Related Art A conventional clamp circuit has a configuration shown in FIG. 2, for example. 21. 22 is a back 7 circuit, 23 is a capacitor, 24 is a switch circuit, 25 is an A/D converter, 26
is a DC level detection circuit, 28 is a filter circuit, and 29 is D
/A converter, 3QI/'i lamp pulse generation circuit, 3
1 is a synchronization signal detection circuit. FIG. 3a shows an example of a reference signal included in an input image signal, where A is a horizontal reference signal portion and B is a DC level reference signal portion. Third
The figure shows a detail M' of the horizontal reference signal A.

In the conventional clamp circuit configured as described above, the DC level of the image signal is detected from the image signal converted from analog to digital by the A/D converter 25, and from the signal of the portion corresponding to bK in FIG. , filter circuit 27
performs necessary processing such as integration, removes noise components, and outputs the data to the switch circuit 24 via the D/A converter 29.
supply to. The clamp pulse generation circuit 3o is controlled by the synchronization signal detection circuit 31, outputs a pulse for a period corresponding to T1 of the portion a of the reference signal included in the image signal, and controls the opening and closing of the switch circuit 24.

In other words, when the detected DC level is smaller than the specified value, the voltage value of the D/A converter output increases.
If the detected DC level is higher than the specified value, D/
It operates so that the voltage value of the A converter output becomes small. The switch circuit 24 is conductive only during the period T1, and clamps the input analog signal of the buffer circuit 22 to the D/A converter output voltage.

As a result, a closed loop is formed that operates so that the level of the signal b representing the DC level included in the image signal is at a predetermined value.

Problems to be Solved by the Invention However, in the above configuration, the output voltage of the D/A converter is a constant value during the period corresponding to the horizontal reference signal. The period during which the switch 24 is made conductive in order to clamp to the converter output voltage needs to be a short period during which the horizontal reference signal maintains a constant value, that is, only T1. Generally 2
4 is composed of an electronic switch, but its response speed is limited υ, and since such a switch circuit generally has a resistance value r, the capacitor 23 is charged and discharged to operate the clamp. A finite amount of time is required to complete. Therefore, there are many cases where the clamping operation is insufficient with only the time T1, and in such cases, the response of the clamping operation becomes slow, which is a drawback. Furthermore, since the period during which the switch circuit 24 is conductive is as short as T1, there is a drawback that when noise is added to the input image signal, the level to be clamped changes due to the noise added to the portion corresponding to T1. was.

In order to solve such problems in the conventional example, the present invention generates a clamp voltage similar to part or all of the horizontal reference signal included in the input image signal, thereby achieving high-speed and noise-resistant DC level reproduction. The purpose of the present invention is to provide a clamp circuit that can perform the following steps.

Means for Solving the Problems The present invention provides a first buffer circuit, a capacitor connected to the output of the first buffer circuit, a switch circuit connected to the output end of the capacitor, and a switch circuit connected to the output of the capacitor. a second buffer circuit connected to the output terminal;
an A/D converter that converts the output of the Baku77 circuit from analog to digital; a synchronization signal detection circuit that detects a synchronization signal component from a reference signal included in the image signal;
a D converter, a DC level detection circuit that calculates a reference value of a DC level of an output signal, a reference amplitude detection circuit that detects a reference amplitude of the A/D converter output signal, the DC level detection circuit and the reference amplitude; a pattern generation circuit that is controlled by a detection circuit and the synchronization signal detection circuit and generates a predetermined pattern similar to part or all of a reference signal included in the image signal; and a pattern generation circuit that converts the output of the pattern generation circuit into digital/analog. This clamp circuit includes a D/A converter, and a clamp pulse generation circuit that is controlled by the synchronization signal detection circuit and controls opening and closing of the switch circuit.

Function: With the above-described configuration, the present invention converts an input image signal from analog to digital, and detects the DC level and reference amplitude of the A/D converted signal from the DC level reference signal and horizontal reference signal included in the image signal. A pattern similar to the horizontal reference signal controlled by these is generated and supplied to the switch circuit of the clamp stopper via the D/A converter, and the clamp operation is performed by making the switch circuit conductive during the period of the horizontal reference signal. It is something to do. For example, as shown in FIG. 3, the horizontal reference signal is composed of two flat parts and a sloped part connecting these parts, and the reference amplitude detection circuit detects the level difference vq between the two flat parts. The pattern generation circuit generates a signal similar to the horizontal reference signal, and controls the level difference between the two flat parts of this signal to be the same as the detected reference amplitude. The average level of the signal output from the pattern generation circuit is controlled by the output of the DC level detection circuit.

During the horizontal reference signal period, the image signal changes between two flat parts as shown in Figure 3, but the pattern generation circuit creates a waveform similar to the horizontal reference signal, and the image signal is transmitted through the D/A converter. Therefore, the potential difference between the output of the D/A converter and the output of the first back 7 circuit hardly includes any change in the horizontal reference signal. Therefore, the switch circuit can be made conductive during the horizontal reference signal period, and the lamp operation can be performed reliably in a short period of time.

In addition, since the switch circuit can remain conductive for a long time, even when noise is mixed into the signal,
Fluctuations in clamp level due to noise are averaged out and the influence is reduced.

Embodiment FIG. 1 shows a block diagram of a clamp circuit in an embodiment of the present invention. In Figure 1, 1.2 is a buffer circuit, 3 is a capacitor, 4 is a switch circuit, and 5 is an A/
D converter, 6 is a DC level detection circuit, 7 is a reference amplitude detection circuit, 8 is a pattern generation circuit, 9 is a D/A converter, 10
1 is a clamp pulse generation circuit, and 11 is a synchronization signal detection circuit.

The operation of the clamp circuit of this embodiment configured as described above will be explained below.

The input image signal is supplied to the A/D converter 5 via the back 7 circuit 1, the capacitor 3, and the buffer circuit 2'fr: and the DC level of the output signal of the A/D converter 5 is detected by the DC level detection circuit 6. Detect deviations from standard values.

The reference amplitude detection circuit 7 detects the reference amplitude from the horizontal reference signal portion of the A/D converted signal. The horizontal reference signal is the third
As shown in the figure, it is composed of two flat parts and a sloped part connecting these parts, and the reference amplitude detection circuit 7 detects the level difference vg between these two flat parts. The pattern generating circuit 8 generates a signal similar to the horizontal reference signal, and controls the level difference of the flat portion of this signal to be the same as the detected reference amplitude. The average level of the signal output from the pattern generation circuit 8 is controlled by the output of the DC level detection circuit 6.

During the horizontal reference signal period, the image signal changes between two flat parts as shown in FIG. Since the signal is supplied to the switch circuit 4 via the D/A converter 9 and the buffer circuit 1, the potential difference between the output of the D/A converter 9 and the output of the buffer circuit 1 hardly includes a change in the horizontal reference signal. Therefore, switch circuit 4f! : Can be made conductive during the period of the horizontal reference signal, allowing reliable lamp operation in a short period of time. Furthermore, since the time during which the switch circuit is conductive can be extended, even if noise is mixed into the signal, fluctuations in the clamp level due to the noise are averaged out and the influence is reduced.

As described above, according to this embodiment, a Franz signal similar to part or all of the horizontal reference signal included in the input image signal:
By generating a voltage and switching it during part or all of the horizontal reference signal period, it is possible to provide a clamp circuit that can perform direct current level reproduction reliably and resistant to noise in a short period of time.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, it is possible to realize a clamp circuit that can regenerate the DC level of an image signal, operates reliably in a short time, is less susceptible to mixed noise, and is capable of reproducing the DC level of an image signal. , its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clamp circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional clamp circuit, and FIG. 3 is a waveform diagram for explaining the circuit. 1.2,21.22...Buffer circuit, 3,3
3...Capacitor, 4.24.Old...Switch circuit, 5.26...A/D converter, 6,26.
...DC level detection circuit, 7...Reference amplitude detection circuit, 8...Pattern generation circuit, 9,2
9... D/A converter, 10, 30... clamp pulse generation circuit, 11.31... synchronous signal detection circuit, 28... filter circuit. Name of agent: Patent attorney Toshio Nakao and one other person

Claims (1)

[Claims] A clamp circuit for an image signal reproducing device, wherein a reference signal included in the image signal is a predetermined data string serving as a reference for each of the synchronization timing of the image signal, the DC level, and the amplitude of the image signal, the clamp circuit comprising: a capacitor connected to the output of the first buffer circuit, a switch circuit connected to the output end of the capacitor, a second buffer circuit connected to the output end of the capacitor; an A/D converter that converts the output of the second buffer circuit from analog to digital; a sync signal detection circuit that detects a sync signal component from a reference signal included in the image signal; a DC level detection circuit that calculates a reference value of a DC level, a reference amplitude detection circuit that detects a reference amplitude of the A/D converter output signal, the DC level detection circuit, the reference amplitude detection circuit, and the synchronization signal detection circuit. a pattern generation circuit that is controlled by a circuit and generates a predetermined pattern similar to part or all of a reference signal included in the image signal; and a D/A converter that converts the output of the pattern generation circuit from digital to analog;
and a clamp pulse generation circuit that is controlled by the synchronization signal detection circuit and controls opening and closing of the switch circuit.