JPS6348107B2 - - Google Patents

Info

Publication number
JPS6348107B2
JPS6348107B2 JP2966179A JP2966179A JPS6348107B2 JP S6348107 B2 JPS6348107 B2 JP S6348107B2 JP 2966179 A JP2966179 A JP 2966179A JP 2966179 A JP2966179 A JP 2966179A JP S6348107 B2 JPS6348107 B2 JP S6348107B2
Authority
JP
Japan
Prior art keywords
signal
circuit
data
clock
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2966179A
Other languages
English (en)
Japanese (ja)
Other versions
JPS55121769A (en
Inventor
Yoji Sugiura
Masaru Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2966179A priority Critical patent/JPS55121769A/ja
Priority to US06/127,432 priority patent/US4344039A/en
Priority to DE3009713A priority patent/DE3009713C2/de
Publication of JPS55121769A publication Critical patent/JPS55121769A/ja
Publication of JPS6348107B2 publication Critical patent/JPS6348107B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)
JP2966179A 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal Granted JPS55121769A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2966179A JPS55121769A (en) 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal
US06/127,432 US4344039A (en) 1979-03-13 1980-03-05 Demodulating circuit for self-clocking-information
DE3009713A DE3009713C2 (de) 1979-03-13 1980-03-13 Schaltungsanordnung zum Dekodieren eines selbsttaktierenden Informationssignals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2966179A JPS55121769A (en) 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP4941580A Division JPS55146623A (en) 1980-04-14 1980-04-14 Demodulating circuit for self-clocking information signal
JP6513680A Division JPS5623065A (en) 1980-05-15 1980-05-15 Demodulation circuit for self clocking information signal

Publications (2)

Publication Number Publication Date
JPS55121769A JPS55121769A (en) 1980-09-19
JPS6348107B2 true JPS6348107B2 (enrdf_load_stackoverflow) 1988-09-27

Family

ID=12282293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2966179A Granted JPS55121769A (en) 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal

Country Status (1)

Country Link
JP (1) JPS55121769A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS55121769A (en) 1980-09-19

Similar Documents

Publication Publication Date Title
JPH0927171A (ja) 16ビットのディジタルデータ語のシーケンスを17ビットの符号語のシーケンスに符号化する方法
JPH0544206B2 (enrdf_load_stackoverflow)
JPS6412143B2 (enrdf_load_stackoverflow)
JPS6238791B2 (enrdf_load_stackoverflow)
US4344039A (en) Demodulating circuit for self-clocking-information
US3488662A (en) Binary magnetic recording with information-determined compensation for crowding effect
US3852687A (en) High rate digital modulation/demodulation method
US3827078A (en) Digital data retrieval system with dynamic window skew
JPH07118657B2 (ja) 2進デ−タ符号化及び復号化方式
US4157573A (en) Digital data encoding and reconstruction circuit
JPS6117273A (ja) 回転形磁気記録装置
US3562726A (en) Dual track encoder and decoder
EP0090047B1 (en) Encoding and decoding system for binary data
JPH0656958B2 (ja) 情報デ−タ復元装置
CA1061893A (en) Self-clocking, error correcting low bandwidth digital recording system
JPS6235180B2 (enrdf_load_stackoverflow)
JPH0332132A (ja) デジタル信号復号装置
JPS6348109B2 (enrdf_load_stackoverflow)
US3852811A (en) Digital data encoding and reconstruction circuit
JPS6348107B2 (enrdf_load_stackoverflow)
JPH0213494B2 (enrdf_load_stackoverflow)
JPS634269B2 (enrdf_load_stackoverflow)
KR910003378B1 (ko) 디지탈 신호 복조 및 재생장치
JPS6260747B2 (enrdf_load_stackoverflow)
JPS6348108B2 (enrdf_load_stackoverflow)