JPS6348064A - Variable power system for picture data - Google Patents

Abstract

PURPOSE:To enable a variable power through a real-time processing by constituting a variable power control information by data which have been separated into the data to show the relation of the number of the sampling spots of the picture data and the data to show the relation of the positions of the sampling spots before and after the variable power. CONSTITUTION:The variable power control information is constituted by the data which have been separated into the data to show the relation of the number of the sampling spots of the picture data and the data so show the relation of the positions of the sampling spots before and after the variable power. An Xn, expressed by a formula against a variable power rate alpha(%), shows the position of the data after the variable power against the data before the variable power. For instance, the alphashows the number of the sampling spots after the variable power against 100 number of the sampling spots before the variable power, and the Xn has an information of the relation of the number and the relation of the positions of the sampling spots before and after the variable power within it, and for a part of more than 100 number of the sampling spots before the variable power, the consideration of the repeat by every 100 number is enough. Consequently, the variable power through the real-time processing can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a scaling method for WJa data, and more specifically, to a digital copying machine, facsimile, image scanner, etc. that scales digitized image data by digital logic processing. This invention relates to an image data scaling method that can be applied to image editing systems and the like.

(Prior art) Conventional scaling methods for image data in digital image processing devices, etc. include optical scaling, binary image thinning, insertion-based scaling, and scaling using an interpolation function (table method). However, among these magnification methods, the optical magnification method has mechanical structural reasons,
That is, it is difficult to vary the magnification over a wide range due to the size of the device and optical reasons, such as the brightness of the light source and the blur of the image. Further, scaling methods based on thinning and insertion of binary images have drawbacks such as large distortion of image data and poor scaling accuracy. Furthermore, although the scaling method using an interpolation function can handle several types of fixed scaling, it is difficult to handle a wide range of scaling with arbitrary scaling factors.

(Objective) The present invention has been made in view of the drawbacks of the above-mentioned prior art.
The promise is that digital image data can be electrically scaled at any magnification using a simple hardware configuration.
It is an object of the present invention to provide a method for changing the magnification of image data that enables scaling over a wide range with high accuracy and by real-time processing synchronized with an input device or an output device.

(Configuration) In order to achieve the above object, the present invention provides a line memory having a capacity for at least one main scanning line, a scaling control memory in which scaling control information is stored, and data for correcting data during scaling operation. In the image data scaling method, which includes a correction section, and in which the line memory and the data correction section operate based on the scaling information from the scaling control memory to perform a scaling operation, the scaling control information is
The present invention is characterized in that it is composed of data separated into data representing the number relationship of sampling points of image data before and after scaling, and data representing the positional relationship of the sampling points.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

The present invention relates to a method for two-dimensionally scaling digitized image data by digital logic processing. Image data divided into pixel units in the main scanning direction and the sub-scanning direction are arranged in time series in pixel units within one main scan. Furthermore, in the sub-scanning direction, image data is input as first main-scanning data, second main-scanning data, third main-scanning data, etc. arranged in time series in units of main-scanning lines, The number of pixels in the main scanning direction is scaled at a desired magnification and output as new image data. At this time, the input and output have a certain synchronous relationship, and this is so-called real-time processing.

Here, concepts such as pixels, image data, main scanning, sub-scanning, etc. will be explained with reference to FIGS. 1 and 2. In FIG. 1, one image consists of pixels PiJ (i = 0.1, 2.
-・=-n, j=0.1.2. -・--=n), and PO (set of 1 to Pas Po+P+a to PII
Set of I P+ + Pzo”Pz+a set P 2
+'-""- are image data within one main scan, respectively. Hereinafter, for convenience, each main scanning line is shown in FIG. 1 in order in the sub-scanning direction. -・-・-n and
We will call them the 0th line, the 1st line, and the 2nd line.

Fig. 2 is a time chart of signals corresponding to Fig. 1, where LSYNC is the main scanning 3tI+ signal (or line synchronization signal or simply called synchronization signal), P is whether the main scanning line is an even numbered line or an odd numbered line. A signal indicating whether the line is
On even lines, P-'L')·a is an image data signal obtained by reading FIG.

PI, PI, and Pl in the image data signal a are P in FIG.
, P, , Pl, and more specifically, the signal a corresponds to PI
, Pl, and Pl are signals divided into pixel units within each of them.

Next, an embodiment of the image data scaling method according to the present invention will be described with reference to the block diagram of FIG. In the figure, 1 is a first selector, 2 is a data correction section, 3 is a third selector,
4 is a second selector, 5 is a first line memory, 6 is a second line memory, 7 is a fourth selector, 8 is a scaling control memory, and 9 is a memory controller. Further, signal a in FIG. 3 is input image data and has density information of 6 bits and 64 gradations. The signal d is output image data and also has density information of 6 bits and 64 gradations.

The signal i is a signal indicating whether the magnification is enlargement or reduction, and when it is enlarged (including the same size), i=#H#, and when it is reduced, i=“L′.

The signal j contains information necessary for performing the scaling process, and is set in the scaling control memory 8 by a central processing unit (CPU), not shown. This set of scaling information by the CPU is set in advance prior to the scaling operation of image data.

At the signal! ! is a signal for scaling control that is supplied to the data correction section 2 and the memory controller 9 during scaling operation based on the set signal j.

Signals m and n are respectively sent to the first and second line memories 5.
6 control signals, which are address signals, read, and write control signals.

The signal P is a signal indicating whether the main scanning line is an even number or an odd number, as in FIG. Signal CLK is a clock signal for each pixel.

Further, signals S, c, e, f, g, and h are the outputs of the first selector 1, data correction unit 2, second selector 4, fourth selector 7, first line memory 5, and second line memory 6, respectively. Yes, and they are image data. Of course, all of these also have density information of 6 bits and 64 gradations.

Although the setting of magnification information in advance into the magnification control memory 8 will be described later, an outline of the operation of the configuration shown in FIG. 3 during the magnification change operation will be explained with reference to FIG. 4. As shown in FIG. 4, this operation is roughly divided into four operating modes: even-numbered lines and odd-numbered lines during enlargement, and even-numbered lines and odd-numbered lines during reduction. In the figure, the RD mode and W in the columns of the first and second line memories 5.6
T modes represent read mode and recess mode, respectively.

For example, for even-numbered lines during enlargement, the first line memory 5
is in the RD mode, the second line memory 6 is in the WT mode, and the human input signal a to FIG.
→ f → second line memory 6 on the path of second line memory 6
will be written to. In parallel with this operation, successive data from the first line memory 5 is transferred from the first line memory 5→g−+
Fourth selector 7-first selector 1-b-data correction section 2
-n C=output through the path of the third selector 3-d.

In the next scan, since it is an odd number line, the RD and WT modes of the first and second line memories 5.6 are reversed, and the input signal a is changed from a to second selector 4→f to first line memory. 5, while parallel to this operation,
The read data of the second line memory 6 is transferred from the second line memory 6-h to the fourth selector 7-e→first selector 1→b
-Data correction unit 2-hC→third selector 3→d is output. At this time, the data read from the second line memory 6 is the data written to the second line memory 6 during the previous even-numbered line. Similarly, the data written in the first line memory 5 in the current line is read out in the next even line, and after passing through each path, the data is written in the first line memory 5.
is output as

The above is the operation during enlargement, but the person on duty will similarly understand the operation during reduction from FIGS. 3 and 4.

In other words, the above operation can be expressed as follows. That is, (1) When enlarging, data is corrected when reading from the line memory, and when reducing, data is corrected when writing to the line memory.

(2) The first and second line memories perform read and write operations alternately for each scanning line, and when one is in continuous output mode, the other is in storage mode.

(3) The above (1) and (21) are controlled by the enlarged/1M small signal i and the even/odd line signal p.

The outline of the operation of the configuration shown in FIG. 3 has been explained above, focusing on the flow of image data. Since the above description hardly mentions where and how the scaling is performed, the following explanation will focus on scaling and will focus on the configuration and operation of each block in FIG. 3 in detail.

FIG. 5 is a time chart schematically showing the input signal a of FIG. 3 corresponding to the vicinity of the position on the main scanning line. In this chart T.

indicates a pixel unit, and corresponds to one cycle of the signal CLK in FIG. 3. The vertical axis is 6 bits 1-=6411! ! Corresponds to the density level of the tone.

Now, as shown in FIG. 5, the input image data has a pixel pitch indicated by ○ marks T, and density levels A, A□, A1.・・−
...-Ah. Consider enlarging the image shown in FIG. 5 in the main scanning direction, with a pixel pitch of T1. For the sake of simplicity, let us take, for example, 250% enlargement as shown in FIG.

That is, in Fig. 6, mark 0 and Ax, A3, A
4-... are A□, A3, A4 ・- in Fig. 5
・−゛, and has been expanded by 2.5 times in the scanning direction.

On the other hand, the Δ mark is the pitch T1, Bz+, Bz□.

B! i B *+・−・−・− is the density level at each point. At this time, B tl, B zt, B
! 3+ B s+-=- is At, A1. A4-・-
The positional relationship between A and B, that is, the O mark and the Δ mark, and the density level between A and B have a certain relationship.

For example, in Figure 6, A is 2.5 T I period, B is T1
If A2 and SZ+ lose once in the cycle, the subsequent positions of A and B are uniquely determined.

Further, the density level of B is calculated, for example, by the so-called "neighboring pixel distance linear distribution method", which is determined based on the levels of two adjacent A's and the distance to A's.

In the example of FIG. 6, for example, Btt is rl + r from the preceding and following At and A3.

It is determined by

FIG. 7 is a reduced example of FIG. 5, and shows an example where the magnification ratio is 7094. In Fig. 7, the pitch to <0.
7TI, and the scaled pitch of B is as shown by the Δ mark.
Same as A before magnification (Figure 5) (T+). In this case as well, as in the case of enlargement, the positional relationship between the 0 mark and the Δ mark and the density level between A and B are constant. It's decided.

For example, in Figure 7, the level of B2 is rl + rg It is determined by

As described above, if the scaling factor is given, it is possible to determine the positional relationship between data A before scaling and data B after scaling, and from that positional relationship and data A before scaling. It is possible to determine the density level of data B after scaling.

To explain this in relation to FIG. 3, it is the magnification control memory 8 that stores information on the positional relationship between A and B, and sends out this information as necessary.
22. The data correction section 2 determines the level of B by calculations such as and B2.

Furthermore, as is clear from Figures 6 and 7, depending on the magnification and pixel position, there are cases where there is no Δ mark at all, cases where there is only one Δ mark, and cases where there are only two Δ marks between 1 pitch between the O mark and the mark. There are various cases such as Of course, this relationship is also a positional relationship, and is determined by a given magnification ratio. Whether there are no Δ marks or how many Δ marks there are is an extremely important matter for the operation of FIG. Used for address control.

Next, a specific example of information on the positional relationship before and after scaling will be described.

X7 corresponding to the scaling factor α (%) indicates the position of the data after scaling relative to the data before scaling. In other words, it shows a new sampling point for scaling when the data sampling pitch before scaling is 1. Here, the constant corresponds to the phase difference between the old and new sampling or the initial value, and is set to -0 for simplicity. In other words, the position of the first data is made to match before and after scaling. Here, α
By α, given the scaling factor α, the surface is simply 100/α, thus X, in the CPU by calculation or by a read-only memory (ROM) table. is required.

Furthermore, the magnification ratio α (%) is, for example, 50% to 1000%.
In the case where it is set in 1% increments within the range, it can be expressed as.

That is, α indicates the number of sampling points after scaling with respect to 100 sampling points before scaling, K7 has information on the number relationship and positional relationship of the sampling points before and after scaling, and K7 has information on the number relationship and positional relationship of sampling points before and after scaling. For portions with 100 or more sampling points, it is sufficient to consider similar repetition for every 100 sampling points.

Therefore, in the above case, the number of n is most often α-1000, and n=1000.

Next, the properties of X,1 will be explained in more detail. K
7 is expressed by the integer part ■7 and the decimal part J7, X n = I n + J n Here, Ifi indicates the number of sampling points before and after scaling, and J7 indicates the position information of the sampling points before and after scaling. .

For example, when expanding (α≧100%), △I−−1,
l-I,, -1 (however, △t, -, =O) becomes △■7
indicates whether there is a pre-scaling sampling point between sampling points n-1 and n after scaling, and △1. If it is -0, there is no 61. %-1 indicates presence.

For example, in Figure 6, B2□ and B'! There is no A between it and 3, so △1. -0, and since there is A between Bt3 and Bffl, it corresponds to ΔI, l=1.

On the other hand, J7 is, for example, B2. and A2, A
It has information regarding the positional relationship r+ (therefore rz) with respect to 3.

Even during reduction (α<100%), △I, -I, -1, 1-1 (however, △I, 1-, = t)
△I7 represents the presence or absence of sampling points before and after scaling, but in the case of reduction, Xfi increases by 100/α, where 1<100/α≦2 (50%≦α<100%). The value of △■7 is also △■
7-1 or 2, indicating whether there is one or two sampling points before scaling between sampling points n-1 and n after scaling, and Δ1. If =1, there is one, △1. If = 2, there are two, which indicates.

For example, in Figure 7, there is one A3 between B2 and B, so it corresponds to △ = 1, and there are two samplings, A4 and A, between B3 and B. There is a point, so △
1. =2.

On the other hand, for J, , the positional relationship is shown even when reduced, and for example, in FIG. 7, there is information regarding r, (therefore rz).

A11 is information related to the number of sampling points during both enlargement and reduction, but in order to simplify the hardware, especially during reduction, △Il,=2 is decomposed into two and transformed.
Let ΔI, l, −0, ΔI, , = 1.

Through this transformation, both enlargement and reduction are possible. △1. -0 means nothing; If it is 611%-1, then yes, It can be treated as

1 and 2 in FIG. 3 by ΔI, l-0 or 1
The above modification leads to a simplification of the hardware in order to control the incrementing of the address in the line memory 5.6.

From the above, with n-α pieces for expansion and n=100 pieces of △I, 1 (-0 or 1) for reduction,
Data on the number of sampling points for scaling in 1% increments from α-50% to 1000% is obtained.

Next, the decimal part J7 of X, l fog 1tt+Ja will be explained. From their definitions, J and l mean Jll-TI/(rt+rz) in FIGS. 6 and 7.

Here, to simplify the hardware, J7 is divided into four ranks according to its value, and the four ranks are divided into K
1. To! Furthermore, in correspondence with each rank, the density B of the sampling point after scaling is made to correspond to the sampling points Az and A3 on both sides before scaling, as shown in the table below.

Jn rank +Kt B10 ≦J,
<0.25 1 0 0 At0.25≦J, <
0.5 2 0 1 Ax (3/4) + As (1/
4) 0.5≦J, l<0.75 3 1 0 1h
(1/2)+A3(1/2)0.75≦J,<1
4 11 At (1/4) ÷ 1h (3/4) or more, the scaling information such that Xll = I, 1 + J, becomes △I,
, , , , and 2 are expressed as 3-bit digital logic data.

Note that the calculation of the value of B in the above table is performed by the data correction section 2 shown in FIG.

K1 for each ΔIfi. To! At the same time, a 3-bit variable data string of α (when enlarging) or 100 (when reducing) is obtained, but since the data is repeated every α or 100 pieces, n-α+1 or n= In the case of 100+1, it is necessary to restart from n-1, and to indicate this, 1 bit is allocated and designated as K4. That is, K4 is nwa l~α-1 (when expanded) or n=1~
In 99 (when IW is small), it is 4-1 only when Ka -0, n""α 1 or n-100.

Above △1. ．． The four bits Kl, , .

Although the principle of scaling and the content of scaling data have been clarified through the explanations so far, each block of the configuration shown in FIG. 3 will be explained in detail below.

FIG. 8 is a circuit diagram showing the internal logic of the variable magnification control memory 8 of FIG. In the figure, 10 to 13 are latches,
14 is random access memory (RAM), 15-1
7 is a gate, 18 is a selector, 19 is an address counter, and 20 to 25 are gates.

The RAM 14 is a memory in which scaling data given as a signal j from the outside is stored, and the number of pieces of data is α-10.
00% (n=α-1000), and its capacity is 4×1000 bits. Therefore, 4000
If it is a bit or more RAM, 50% to 1000% is sufficient to store data that is scaled in 1% increments. For example, in the case of 200%, only 4×200 bits are effectively used.

In FIG. 8, the signal DLT is a clock signal for taking in the variable magnification data j, and the signal DLT is also sent out in synchronization with the sending out of the signal j from the outside.

In addition to the 4-bit modified data, the signal j also has 1-bit data. This is the first data of the variable magnification data, that is, data indicating the timing of n=1, and the address of the RAM 14 is set to address 0 by this signal. More specifically, this bit data is logic=#1# only when n=1, and is 0 for other n's. Then, at #1'', the address counter 19 for the RAM 14 is reset.

Of the variable magnification data j taken into the latch 10, this start bit clears the address counter 19 via the gate 20.degree.22 as a signal j2.

Signal DST indicates that the mode is in which magnification change data j is received and stored in the RAM 14. When the storage is finished, D
ST becomes level “H#”.

The signal DWT is a signal for writing into the RAM 14, and the clock signal CLK is a clock signal used when reading variable-magnification data from the RAM 14, that is, when actually performing a variable-magnification operation.

Selector 18 selects signal DLT or clock signal CL.
K is selected and address counter 19 is incremented.

That is, when storing the signal j in the RAM 14, the signal j! The address counter 19 is cleared by this, and then counted up by the signal DLT. As the address advances, the signal j becomes the signal jl.

j3 is input and written into RAM 14 via latch 10.11. When the amount corresponding to n=α or n=100 is written, the signal DST becomes “H”,
Writing to RAM 14 is completed. This write operation will be explained using the time chart of FIG. Also, the first
FIG. 0 is a time chart explaining the operation of FIG. 8 in the mode of reading variable magnification data from the RAM 14 for variable magnification operation.
It is.

In FIG. 10, during reading, address counter 19 is incremented by selector 18 in response to signal CLK. The signal CLK is also a pixel clock for image data to be scaled.

At the time of reading, the RAM 14 enters the reading mode at DST-'H'. Further, DWT becomes 'H', and the output of the latch 11 becomes a high impedance state. Therefore, the output signal from the RAM 14 appears as the signal j3.

The addresses advance one after another, and the signal ADH-α-1 (n=α
FIG. 10 shows the timing around when the signal ADH-0 is reached (corresponding to ADH-0) and the signal ADH-0 is stepped again. The contents of the signal j3 (α-4), (α-3) -1, . . . mean the scaled data corresponding to the addresses α-4, α-3, . . . , respectively.

In particular, signal j for signal ADR=α-1.

It becomes j4w'l' in . This signal j4 is the end bit of the scaling data, and this signal j4 is the end bit of the variable magnification data.
The address counter 19 is cleared via 2. When this address counter 19 is cleared, the signal ADH-0
ADR-0, 1, 2, . . . are incremented again.

The signal l is output from the latch 12 as one bit in the signal j, and this signal l corresponds to the bit ΔI, 1 in the scaled data j. .DELTA.I was originally sampling number information, but it is easier to understand the signal l if it is considered as a count control signal for scaling. That is, the counting of addresses in the line memory for scaling is controlled on/off based on this signal l.

Among the outputs of the latch 13, the signals Kt and Ks correspond to 2 bits ``+'' and ``2'' indicating the rank of the sampling position data in the scaled data j, respectively. That is, if only the logic is considered, ignoring the time difference between writing and reading and the difference in signal form.

A signal, a signal! This signal is generated from the count on/off control signal l, and is used by the data correction unit 2 in synchronization with the count on/off control signal
This is a signal for controlling the flow of data in (Fig. 3).

FIG. 11 is a timing chart showing the timing of signals CLK, 1, KI, Kz, and Ks.

FIG. 12 is a circuit diagram of the internal logic of the data correction section 2 of FIG. 3. In the figure, 26 is a latch, 27 is a selector, 2
8, 29, and 30 are adders, and 31 is a selector.

Image data b is shifted by the latch 26 to the signal at + timing, and is separated into b1-b, and -b10. For example, bl is A in FIG. 6, and b7 is A3. Here, the signals input to the selectors 27 and 31 are s, =b, respectively.

bz =1/2 b□1 b3-1/4 bfi-1 b6- b4 + bs =1/2 b +1/4 b
-3/4 b, l-+also by -1/2 b.

bs ”1/4 bFl b++-bq + b+a-1/2 b +1/4
b = 3/4 bfi.

Furthermore, since the truth table of the selectors 27 and 31 is as shown in FIG. 13, the image data b1□+bIIC becomes as follows based on the signals Kz and 3.

That is, input data b, scaling data K1. 2, 3
Corrected data C is obtained correspondingly.

In addition, image data b, therefore, ~b11 is a signal,
However, selection conditions of 2+ and 3 can be obtained at the timing of the clock signal CLK.

Figure 14 shows the first and second line memories 5.6 in Figure 3.
FIG. 15 is a time chart illustrating the operation of the circuit shown in FIG. 14. In the figure, 32.33 is the gate, 5
．． 6 is the first and second line memory, 34.35 is the latch, 9 is the memory controller, 36.37.38.42
is a gate, 39.40 is a counter, and 41 is a selector.

With reference to FIGS. 14 and 15, counter 39.4
0 are address counters for the first and second line memories 5 and 6, respectively, and the count on and off control signals β
Based on the selector 41, the signal 1. ．． 1! orders, and the progress of counters 39, 40 is controlled. selector 4
1 is Il, −1(j!, −'H”) and (1.=l
(L = “H”), but the selection condition is signal l.

p, and therefore depends on the signal il. That is, as shown in FIG. 4, the selection conditions differ depending on the magnification mode (i) and the even/odd number (p) of the scanning line.

For example, in the enlargement mode, the counter on the line memory side in the read mode is controlled by the signal 1, and the counter on the one line memory side is always in the count-up mode with the terminal EN-'H'. Furthermore, the write and read modes are alternately reversed for each scanning line.

In addition, in the reduction mode, the counter on the line memory side in the read mode is always counting up at EN-'H', and the other line memory side is in the write mode, and the count is controlled on and off by the signal l. .

The truth table surrounding the selector 41 is shown in the table below.

Also, below the signal W is a write control signal to the line memory (actually RAM), and according to the signal P, the first and second
Write operations are performed alternately in the line memories 5 and 6, that is, when p = "0#" is an even number line, the second line memory 6 is in the write mode, and when p = "1', the second line memory 6 is in the read mode. The opposite is true.

FIG. 15 is an example of iI-1'', especially i-'1' (-enlargement mode), and p=O (=even line).

Signal l is a signal corresponding to △I7 in scaling data j,
i-'1' corresponds to h-17-"1", and at this time the address counters 39 and 40 are counting on. Conversely, A-"Q" corresponds to Δ■7-"O", and at this time the address counters 39 and 40 are off.

Therefore, the output of counter 39.40, i.e. the first
and address signals ml, n of the second line memory 5.6
, advances as shown in FIG.

Then, the signal f is read out from the first line memory 5. (m, , ), (m, , ), etc. in the signal f mean data corresponding to the addresses m, , , mlg. The signal f is shaped by the latch 34 at the timing of the signal CLK and becomes the signal g.

On the other hand, the signal f2 is written to the second line memory 6. This signal f2 is the input image data f, and the gate 33
The signal is inputted to the second line memory 6 via. At this time,
The output h of the latch 35 is also h-f! -f is output, but
Even if the data signal on the write mode side is output in this way, the selector 7 in FIG. 3 selects the 6s=g side, so h in this case has no meaning. However, when the line is an odd number, it becomes eh, and g becomes meaningless.

FIG. 16 shows that data g (or h) read from the first line memory 5 (or second line memory 6) in FIGS. If sent to
3 is a time chart illustrating the operation of the data correction section 2. FIG. In particular, it corresponds to the example in FIG. 15, and is designated as b-ga-a-'. Here, a -1 is selected by selector 1, and b=a is not selected, but b-g is selected, but if you trace g back, you will end up with the signal a from one line earlier, so a -1 is selected.

Also - (mho), (m++), (mho)
The reason why At 2 , As 2 , and A4 have been appended in correspondence to is that the example near At 2 , As 2 , and A4 in FIG. 6 corresponds well to this case.

Signal KI corresponds to signals /, CL, and K in FIG.
It will look like Figure 6 (latch 13, gate in Figure 8) 24.
25). This signal causes latch 26
The output of (Fig. 12), (therefore B!, B3.B6
) is shown in Figure 16.

On the other hand, the signals Kz and Ky are the signal C as shown in FIG.
Changes at the timing of LK. Therefore, as shown in the figure, the correction data output c(-d) changes at the timing of the signal CLK, and is exactly B□.

B! ! ＋B! As noted as 3+B ffl+B x2, the timing and concentration level correspond to the relationship between A and B in FIG. 6.

FIG. 17 is a diagram for supplementary explanation of the principle and operation at the time of enlargement mentioned above.
n −1, 2, −=
250, the value X, =100/α×n, and further, corresponding to this n, the address (ADR) of the RAM 14 (FIG. 8) and the states of other signals are shown.

Since 100/α-0,4, 100/αxn is a sequence of 250 numbers from 0.4 to 100, as shown. From the integer part of 100/α×n, x'=△1. , -1. −
1fi-, is as shown in the figure. Also, in the decimal part! '＊
2' is also as shown in the figure, and furthermore, j4 indicating the end bit is n-1 to 249, j-10'', n-25
0 and j-"1'.

These pieces of information are written into the RAM 14 as scaling data.

On the other hand, during the actual zooming operation, the contents of the RAM 14 are read out, as shown in FIG.

(-, L indicates the state of each part at the time of reading nxl~250
This is shown in correspondence with . In particular, the values of s, b, and c corresponding to n-5 to 12 are shown in Fig. 6 and 16.
It corresponds to the figure. Further, as explained in FIG. 8, j2 is a signal indicating the opening point from n-1, and in this embodiment, j is treated as a signal for clearing the address of the RAM 14 when writing to the RAM 14. j2 itself is R
It is not written to AM14, so this j2 has no meaning when read.

FIG. 18 and FIG. 19 are diagrams for supplementary explanation of the principle and operation at the time of reduction, and show the case of α-71% as an example.

In FIG. 18, n=5 to 10, correspondingly 100/α×n and Δ1. In Fig. 18, △I7 is transformed (△I,
, =2-△I, ,=O and 1), then z'=△
I, l (after deformation) shows the state of each part in comparison with FIG. 17.

In particular, the values of s, b, and c corresponding to n=5 to 10 are the 7th
This corresponds to the example in the figure. Here, C of cl'J = B
o, B 4. B? etc. do not appear in FIG. 7, and have no particular meaning during actual magnification changing operations.

That is, these C values that occur when l'-'O' are stored in the first (or second) line memory 5 (
or 6), but because A'="O", the 8th
7-'Q' in the figure, and therefore 111 (or 12)-'0# in FIG. 14, and the address of address counter 39 (or 40) does not increment.

That is, returning to FIG. 19, the value of C when z' = 'o'' is written to the first (or second) line memory 5 (or 6), but the same value is written in the next β' = '1''. The value of C corresponding to J'-'1' is written to the address of J'-'1'.In this way, C at β'-'0' is dummy data, and the value itself has no meaning. This is obviously a sampling point that will never be realized.

FIG. 20 is a time chart showing the states of each part corresponding to n=5 to 10 in FIG. 19. In the figure, f, = f-
In c, as shown in the figure, BO+BI+−−−−−・−B,
occurs, but when reading, B as in g in Figure 20.
Dummy data such as o and Ba disappear, and B+, B2,
B3, Bs ---.

The principle, operation, and configuration of the magnification change according to the present invention have been described above, and one typical example of the application of the present invention will be described with reference to FIGS. 21 and 22.

FIG. 21 is a schematic diagram of the image reading device, 43 is a contact glass, 44 is a document, 45.46 is a light source, 47, 48
．． 49 is a reflecting mirror, 50 is an imaging lens, 51 is a CCD
(charge-coupled device) reading section including a line sensor, 52
is an image processing section.

In this image reading device, the main scan is electronically scanned by a CCD line sensor in the direction perpendicular to the plane of the paper in the figure, and the sub scan is carried out by a light source 45, 46 and a reflecting mirror 47, 48, 49 as shown in the figure. Scan by moving in the direction of the arrow.

The image data read by the reading unit 51 is processed by the image processing unit 52.
After the image is processed, it is output externally.

Here, the magnification changing operation in the main scanning direction is performed according to the above-described invention, and the magnification changing operation in the sub-scanning direction is performed by suppressing the sub-scanning tg.

FIG. 22 is a functional block diagram of a portion of FIG. 21 that particularly relates to read data. In the figure, 44 is the manuscript;
45 and 46 are light sources, 51 is a reading unit, 51a is a CCD line sensor, 51b is an amplifier, 51c is an A/D converter,
52 is an image processing unit, 52a is a shading correction, 52
b is magnification, 52c is MTF (modulation transfer function) correction, 52
d indicates binarization. In this configuration, the original 44 is illuminated with light g4s, 46. The image of the original 44 is read by a CCD line sensor 51a and converted into 6-bit, 64-gradation digital data via an amplifier 51b and an A/D converter 51c. Thereafter, inside the image processing section 52, shading correction 52a is first performed, and then magnification changing operation 52b is performed. After further MTF correction 52c, binarization 52
d and output to the outside as binary image data.

FIG. 23 is a block diagram showing another application example of the present invention.
3 is image memory, 54 is variable magnification 81! ! The groove 55 indicates an output device. In this application example, when the image data stored in the image memory 53 is read out and printed by the output device 55 such as a laser beam printer, the modification according to the present invention is installed between the image memory 53 and the output device 55. A magnification mechanism 54 is provided to perform real-time magnification change at a speed that follows the speed of the output device.

(Effects) As described above, according to the present invention, a line memory having a capacity for at least one main scanning line, a scaling control memory in which scaling control information is stored, and data for correcting data during scaling operations are provided. In the image data scaling method, which includes a correction section, and in which the line memory and the data correction section operate based on the scaling information from the scaling control memory to perform a scaling operation, the scaling control information is changed. It is proposed that the image data be composed of data separated into data representing the number relationship between sampling points of image data before and after scaling, and data representing the positional relationship of the sampling points.

By doing so, the present invention can electrically change the magnification of digital image data by using a simple hardware configuration, and can change the magnification in a wide range of magnification ratios, change the magnification at any magnification ratio, and change the magnification with high precision. , it is possible to provide a scaling method for image data that enables scaling by real-time processing synchronized with an input device or an output device.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram explaining pixels, image data, main scanning, sub-scanning, etc., FIG. 2 is a time chart of signals corresponding to FIG. 1, and FIG. A block diagram showing one embodiment, FIG. 4 is an explanatory diagram explaining an overview of the operation of the configuration in FIG. 3, and FIG. 5 is an input signal a of FIG. 3.
Fig. 6 is a time chart similar to Fig. 5 but showing an enlarged example, Fig. 7 is a time chart showing a reduced example of Fig. 5, and Fig. 8 is a time chart showing a reduced example of Fig. 3. Circuit diagram showing the internal logic of the variable magnification control memory, No. 9
The figure is a time chart explaining the write operation, and Fig.
A time chart explaining the operation shown in the figure, Fig. 11 shows the signal C.
L.K.! ! , to. Figure 12 is a circuit diagram showing the internal logic of the data correction section in Figure 3, Figure 13 is the truth table of the selector, and Figure 14 is the timing chart for Figure 3.
A circuit diagram showing the internal logic of the first and second line memories and the memory controller in the figure, FIG. 15 is a time chart explaining the operation of the circuit in FIG. 14, and FIG. 16 is an explanation of the operation in the data correction section. Time chart, No. 17
The figure is an explanatory diagram to supplementally explain the principle and operation when enlarging. Figures 18 and 19 are explanatory diagrams to supplementary explain the principle and operation when reducing. Figure 20 is n of Figure 19. =
21 is a schematic diagram showing an image reading device as an application example of the present invention; FIG. 22 is a functional block diagram of the portion related to read data in FIG. 21; FIG. 23 is a block diagram showing another example of application of the present invention. L 3, 4.7...Selector, 2...Data correction unit, 5.6...Line memory, 8...Magnification control memory, 9...Memory controller, 14...
RAM. Figure 1 Figure 2 Figure 5 Figure 12 Figure 13 Figure 14

Claims (4)

[Claims] (1) A line memory having a capacity for at least one main scanning line, a scaling control memory in which scaling control information is stored, and a data correction section that corrects data during scaling operation; In an image data scaling method in which the line memory and the data correction unit operate based on scaling information to perform a scaling operation, scaling control information is used to sample image data before scaling and after scaling. A scaling method for image data, characterized in that it is constituted by data separated into data representing the number relationship of points and data representing the positional relationship of the sampling points. (2) The image data scaling method according to claim 1, wherein the scaling control memory is a read-only memory. (3) Claim (1) characterized in that the scaling control memory is a random access memory.
Image data scaling method listed at the top. (4) Prior to the scaling operation, scaling control information is formed in advance by a central processing unit or the like, and this scaling control information is stored in the random access memory. The image data scaling method described in .