JPS6348031A - Centralized exchange system - Google Patents

Abstract

PURPOSE:To vary the share of communication capacity for a packet exchange call and a line exchange call at each call by using a bus operating control line in a bus type network. CONSTITUTION:A bus operating arbitration circuit 3 arbitrates a request represented through packet bus operating request signal lines 1P7-nP7 from packet exchange data transmission/reception means 1P-nP and allows the use of a bus to any of the packet exchange data transmission/reception means. Furthermore, the bus operating arbitrator circuit 3 hunts a time slot not in use. A bus operating control line 31 is set at a time of a time slot assigned for line exchange of data transmission/reception and the use of the time slot for the line exchange call is informed to packet exchange data transmission/ reception means 1P-nP and line exchange data transmission/reception means 1C-nC. When a wait signal is set, a packet transfer control circuit awaits the packet data transfer during present transfer and restarts the transfer when the wait signal is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated switching system, and more particularly to an integrated switching system that performs circuit switching and packet switching in a bus type network.

[Conventional technology]

Conventionally, integrated switching methods that integrate this type of circuit switching and packet switching include a first method in which all circuit-switched calls are converted into packets and all communication channels in the switch are packet-switched; Alternatively, there is a second method in which the communication path for packet switching and the communication path for circuit switching are separated based on instructions from a maintenance person, and the packet switching and circuit switching are made to coexist inside the exchange.

[Problem that the invention seeks to solve]

However, in the conventional method described above, in the first method, the process of converting circuit switched calls into packets or inversely converting them is complicated and time-consuming, which leads to a decrease in the processing capacity of the switching equipment and an increase in the complexity of the equipment. There were drawbacks. In addition, in the second method, when the traffic ratio of packet-switched calls and circuit-switched calls changes over time, the capacity of the communication network for packet-switched calls and circuit-switched calls is changed with a sufficiently fast response time. The drawback was that it could not be done.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to make it possible to change communication capacity allocation between packet-switched calls and circuit-switched calls on a call-by-call basis without reducing the throughput of switching equipment or complicating equipment. The objective is to provide an integrated switching system for packet and circuit switching.

[Means for solving problems]

The integrated switching system of the present invention provides a switching device comprising a plurality of data communication transmitting/receiving means, a data transfer bus for interconnecting these means for data transfer, and a bus arbitration circuit for arbitrating requests for use of the data transfer bus. A data transfer bus is divided into n time-division channels, and the data transfer bus has a bus use control line that defines how to use the time-division channels, and the time-division channel is controlled when the bus use control line is on. When the bus use control line is off, the data transfer bus is Provides a communication path for time-division data exchange between the data communication transmitting and receiving means, provides a communication path for time-division data exchange when the above is off, and provides a communication path for performing data exchange between the data communication transmitting and receiving means when the above is on. It is characterized by temporarily suspending packet data transfer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system block diagram showing an embodiment of the present invention;
2 is a circuit block diagram showing an example of the data transmitting/receiving means in FIG. 1, and FIG. 3 is a time chart of the data transfer bus and bus use control lines in FIG. 1.

In FIG. 1, the system includes packet-switched data transmitting/receiving means IP, ~nP, and line-switching data transmitting/receiving means I.
C, to nC, a data transfer bus 2, and a bus use arbitration circuit 3. Each packet exchange transmitting/receiving means (for example, I
P> is the packet transmission buffer IP1 as shown in FIG.
．． Packet reception buffer IP2. Packet transfer control circuit IP3° consists of a 2-input AND circuit IP4 in which one of the two inputs is inverted, the 2-input AND circuit IP4 is connected to the packet data transmission line IP5, and the packet reception buffer IP2 is connected to the packet data reception line IP6
The packet transfer control circuit IP3 is connected to the bus use arbitration circuit 3 through a packet bus use request signal line IP7 and a bus use permission line IP8.

In addition, the circuit switching data transmitting/receiving means (for example, IC> is the second
As shown in the figure, it consists of a line exchange data multiplexing circuit IC11, a concave line exchange data separation line IC2, a multiplexing/separation circuit control circuit IC3, and a 2-input AND circuit IC4.The 2-input AND circuit IC4 is connected to a line data transmission line IC5. , and the line switching data separation circuit IC2 is connected to the line data receiving line I.
It is connected to the data transfer bus 2 by C6, and the multiplexing/separation circuit control circuit IC3 is connected to the bus use arbitration line 3 by a line exchange time slot request/release signal line IC7 and a line exchange time slot allocation instruction signal line IC8. There is. Furthermore, one input of each of the two-input AND circuits IP4 and IC-4 is connected to the bus use arbitration circuit 3 by a bus use control line 31.

Next, the operation of this embodiment will be explained with reference to FIG.

When the packet exchange data transmission/reception means IP transfers packet data to the packet exchange data transmission/reception means nP, the packet exchange data transmission/reception means IP transmits information to the bus use arbitration circuit 3 by turning on the packet data transmission line IP5. request to use the bus. The bus use arbitration circuit 3 includes packet bus use request signal lines IP7, . ~nP7 is arbitrated, and the request with the highest priority is assigned the bus permission line IP8. - nP8 is turned on to permit any one of the packet exchange data transmitting/receiving means to use the bus.

Furthermore, when the line-switching data transmitting/receiving means IC transfers data to the line-switching data transmitting/receiving means nC, the line-switching data transmitting/receiving means IC transmits data to the bus use arbitration circuit 3 by turning on the line data transmitting line IC5. It requests time slot allocation and reports the communication partner. The bus use arbitration circuit 3 manages time slot occupancy on the data transfer bus 2, hunts for unused time slots, and transfers the hunted time slot number to the line switching time slot allocation instruction signal line I.
C8, the information is reported to the multiplexing/demultiplexing circuit control circuit IC3 (shown in FIG. 2) and the communication partner (for example, line switching data transmitting/receiving means nC). The line-switched data transmitting/receiving means IC activates the line-switching data multiplexing circuit IC19 and the line-switching data separation circuit IC2 only in the designated time slot, and also activates the line-switching data multiplexing circuit IC19 and the circuit-switching data separation circuit IC2 only in the designated time slot.
Similarly, in C, the bus use arbitration circuit 3 turns on the bus use control line 31 at the time of the time slot assigned to circuit switching for transmitting and receiving data, and indicates that this time slot will be used for a circuit switched call. is notified to the nodes of the packet switching data transmitting/receiving means IP, ~nP and the line switching data transmitting/receiving means IC~nC. The bus use control line 31 is connected to the bat transfer control circuit IP3. ~nP3, and is used as a wait signal for these circuits.

When this wait signal is turned on, packet transfer control circuit IP3. ~nP3 waits the packet data transfer currently being transferred, and restarts the transfer when this wait signal is turned off.

In FIG. 3, <a) is a time slot diagram of the data transfer bus 2 in FIG. 1, from time slot 1 to time slot! This constitutes one frame. Further, (b) is a diagram illustrating how time slots are used, where C indicates that they are used for circuit switching and p indicates that they are used for packet switching. Furthermore, (C) is a time chart of the bus use control line 31 in FIG. 1, in which ON indicates that line switching is being performed, and OFF indicates that it is used for BACKS 1 to exchange.

[Advantageous Effects of the Invention] As explained above, the present invention uses a bus control line to avoid deterioration of the throughput of the switching equipment and complication of the equipment, and moreover allows the switching of packet-switched calls and circuit-switched calls for each call. This has the effect of making it possible to change communication capacity allocation.

[Brief Description of the Drawings] Fig. 1 is a system block diagram showing one embodiment of the present invention;
2 is a circuit block diagram showing an example of the data transmitting/receiving means in FIG. 1, and FIG. 3 is a time chart 1 of the data transfer bus and bus use control lines in FIG. 1. IP, ~nP... exchange data transmitting/receiving means for packet 1, IC, ~nC... data transmitting/receiving means for circuit exchange, 1
1] 1...Packet)-transmission buffer, IP2...Packet i-reception buffer, IP3...Packet transfer control circuit, 1P4. IC4...2 input AND circuit, IP5
．． ~nP5...Packet data transmission line, IP6. ~n
P6...Packet data reception line, IP7. ~nP7・
...Packet bus use request signal line, IP8. ~nP
8... Bus use permission line, IC1... data multiplexing circuit for line switching, IC2... data separation circuit for line switching, IC3... multiplexing/separating circuit control circuit, IC5...
Line data transmission line, IC6...Line data reception line, 1
c7, ~nC7...Circuit switching time slot request/
Release signal line, IC8, ~nC8... Time slot allocation instruction signal line for line exchange, 2... Data transfer bus, 3
...Bus use arbitration circuit, 31...Bus use control line. Fuck l concave $ 2 hard

Claims (1)

[Claims] In a switching device comprising a plurality of data communication transmitting/receiving means, a data transfer bus for interconnecting these means for data transfer, and a bus arbitration circuit for arbitrating requests for use of the data transfer bus, the data transfer bus is The data transfer bus is divided into time-division channels, and the data transfer bus has a bus use control line that defines how to use the time-division channels, and when the bus use control line is on, the time-division channels are divided into m (m
<n) When the time division channel and the bus use control line are off, the data transfer bus is separated into (n-m) time division channels, and when it is on, the data transfer bus is time division between the data communication transmitting and receiving means. providing a communication path for exchanging data; when the off state is off, the communication path is providing a communication path for exchanging packet data; and when the on state is on, the packet data transfer being performed between the transmitting and receiving means is temporarily interrupted. Features an integrated exchange method.