JPS60108952A - Data transfer control system - Google Patents

Abstract

PURPOSE:To simplify a transfer mechanism by inputting data transfer clocks to a signal line common to respective apparatuses, and every input of the clock to each apparatus, transferring data from a source apparatus to a destination apparatus. CONSTITUTION:A data transfer control system is provided with a data transfer controller 1 and a data transfer clock generator 3 is connected to the controller 1 through a PCU bus a1. In addition, data transferring apparatuses 21-2n to be the source and destination apparatuses are connected to the bus a1. A data transfer clock line a4 and a signal line a3 sending a busy signal are connected to respective apparatuses 21-2N and the generator 3. A data transfer bus a2 is also connected to the respective apparatuses 21-2N. Data transfer clocks are supplied from the generator 3 to the respective apparatuses 21-2N through the line a3, and every input of each clock to respective apparatuses 21-2N, data are transferred from the source apparatus to the destination apparatuses. Thus, the mechanism of the control system is simplified.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a data transfer control method for transferring data between arbitrary data transfer devices. [Technical Background of the Invention and Problems thereof] Data Transfer device traps include those that only have the function of transmitting data, those that have the function of transmitting and receiving data,
There are also devices that have the function of only receiving gator messages.

Among such devices, for example, a device in a transmitting state by an external control means is called a source device, and an IA device in a receiving state is called a destination device.

Conventionally, when transferring data, a method has been adopted in which the data transfer device designated as the source device generates a data transfer lock and transfers the data to the data transfer device designated as the destination device. A data transfer device that can serve as a source device must have a clock generation means for data transfer and a control means for controlling this clock circuit. For this reason, the data transfer equipment became expensive and the connections between the equipment became complicated, making the system not economical and rational as a whole.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to improve the economic efficiency of data transfer equipment and to provide a rational data transfer control system.

[Overview of the invention]

To achieve the above object, the present invention provides a data transfer control method for transferring data between a source device in a transmitting state and a destination device in a receiving state among a plurality of data transfer devices. A data transfer lock generator is connected to this signal line, and each time the data transfer clock generated from the data transfer lock generator is input via the 4g line, a destination signal is sent from the source device. The feature is that data is transferred to the nation device.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data transfer control method of the present invention. In the same figure, 1 controls this method = v
-r data transfer controller, CPU (Central
l Processing Unit) Specify the data transfer device 2□ to 2N to be transferred via bus a1, specify the number of data transfer locks to the data transfer lock generator 3, and input the data transfer start command. . Each data transfer device 2□~2N is a data transfer bus a2
Send and receive data via. - The data transfer lock generator 3 transmits the generated data transfer lock to each data transfer device 21 to 2 via the data transfer lock line a3, which is the signal line, although its detailed configuration will be described later.
When the number of data transfer locks specified by the data transfer controller 1 matches the number of data transfer locks generated, a data transfer end signal and an end interrupt signal are output to the data controller 1. In addition, a4 is bu
sy line, and 7 of data transfer devices 2 to 2N.
This is a signal line for sending a busy signal to the data transfer lock generator 3 if the device designated as the destination device or the device designated as the destination device is unable to transmit or receive data for some reason.

Next, the configuration of the data transfer lock generator 3 will be described in detail with reference to FIG.

? ! , 2 is a block diagram showing an embodiment of the data transfer lock generator 3. In the same figure, 4 is a basic tarlock generator which is an interface for compatibility with the information transmitted by the CPU bus a1; The data transfer lock S□ (hereinafter also referred to as a busy clock) generated by this is output to the clock generating section 6. This clock generator 6
transfers the generated clock S1 to the lock line &
3 to each data transfer device 21 to 2N, and also counts the number of generated clocks and transfers the data via CPU bus a1 and interface 4. Lock number storage unit (hereinafter simply referred to as storage unit) When the number of clocks 82 specified by the data transfer controller 1 stored in the data transfer controller 1 matches the clock count 82 stored in the data transfer controller 1, a 7 match signal S3 is output to the data transfer end status generator (hereinafter simply referred to as the end status generator) 8. Exit status generator 8
Based on this coincidence signal S3, the end signal S4 is generated by the clock generator 6. Data transfer end interrupt generation unit (hereinafter simply referred to as end interrupt generation unit 5)9. and output to the gator transfer controller 1 via the interface 4. The end interrupt generating section 9 outputs the end interrupt signal S6 to the data transfer controller 1 via the interface 4.

The operation of the present invention configured as described above will be explained.

First, the data transfer controller 1 specifies in advance the source device and the destination device among the data transfer devices 2□ to 2N, specifies the number of data transfer locks 82, and stores the number in the storage unit 7. It also outputs a data transfer start command S5 to the end status generating section 8. The end status generating section 8 resets the count value of the number of clocks generated by the clock generating section 60 in response to the start command S5.

Each data transfer device 2, to 2N transmits and receives data via the data transfer bus a2 with a pre-specified source device and destination device every K when a clock S is generated from the basic clock generator 5. When the generated clock number and the clock number 82 designated by the data transfer rate device 1 match, the clock generation unit 6 generates the designated clock number 82, and determines that the clock is completed and sends a match signal S3 to the end status. Output to the generating section 8. Then, the end status generating section 8 outputs the end number 16 S4 to the clock generating section 6, and stops supplying the clock S1 to the data transfer lock line a3. This termination signal S4 is also output to the interface 4 and the termination interrupt generation section 9, and the termination interrupt generation section 9 generates a termination interrupt to the data transfer controller 41 through the interface 4. Signal S4 is data transfer controller 1
It is cleared by the data transfer lock generation start command S5, and the operations described in ii) are performed again.

In addition, if a situation occurs in the source device or the destination device and transmission/reception becomes impossible, the destination device outputs a busy signal and interrupts clock generation from the data transfer generator 3. Xf becomes possible. - In this way, the clock generated from the data transfer lock generator 3 is output to each data transfer device 2□~/2N via a common signal line, and data is transferred between the source device and the destination device. Therefore, each source device does not need to be equipped with a clock generation means, a means for controlling it, etc., so the device becomes simple and there is no need for complicated connections.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and includes various modifications within the scope of the gist of the present invention.

〔Effect of the invention〕

As described in detail above, according to the present invention, the configuration of the data transfer device is simplified and complicated connection relationships are not required. Control method can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer control system according to an embodiment of the present invention, and FIG. 8g2 is a block diagram of a data transfer lock generator. ■...Data transfer controller, 21-2N...Data transfer equipment, 3...Data transfer lock generator, 4...
・Interface, 5...Basic clock generator, 6
... Clock generation section, 7... Data transfer lock number storage section, 8... Data transfer end status generation section, 9
...Data transfer end interrupt generation unit, J...CPU
path, a2...data transfer bus, a3...data transfer lock line, a4...busy line.

Claims (1)

[Claims] In a data transfer control method that transfers data between a source device in a transmitting state and a destination device in a receiving state among multiple data transfer devices, a common signal line is provided for each device, and this signal line is A data transfer lock generator is connected, and data is transferred from the source device to the destination device every time the data transfer lock generated from the data transfer lock generator is input via the signal line. Characteristic data transfer control method.