JPS6347777A - Electronic counter device - Google Patents

Abstract

PURPOSE:To prevent a CPU from malfunction at the time of the runaway of the CPU and to protect data in an EE-PROM by permitting the CPU to write data only when specific data are sent. CONSTITUTION:In case of writing data for the number of prints in the EE- PROM (electrical erasable programmable read-only memory) 4, a write control circuit 16 controls the EE-PROM so as to permit it to write data only for an allowable period. Specific data are sent to a write control circuit 16 through an address bus 5 and also sent to the EE-PROM 4 prior to the writing of data for the number of prints. Since the EE-PROM is constituted so as to be permitted to write data only when the specific data are sent, data writing in the EE-PROM is inhibited when a situation such as the runaway of the CPU 1 due to noise e.g. is generated, so that data writing in error can be completely removed and the data in the EE-PROM 4 can be surely protected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a counter device for counting numerical values, and particularly to an electronic counter device suitable for counting the number of prints of an electrophotographic copying machine or a page printer.

[Traditional technique]

Conventionally, as this type of device, a mechanical counter that is a combination of an electromagnetic counter and a cam has been used, but recently, microcomputer-controlled electronic counters have become popular.

This counter uses 0MO3 RA as a storage means for counting values.
M (random access memory) or C of 0MO3
Using the RAM built into the PU (processor circuit),
Moreover, data in this RAM disappears when the power is cut off, so
It is powered by lithium batteries, etc. Also, R.A.
EE-FR that can write and erase data instead of M
OM (electronic eraser blue programmable read only memory) is also used. EE-F
If a ROM is used, as is well known, batteries for the Banokwa Knob are not required. Since the data of these counters can be displayed using a 7-segment display made of light emitting diodes, the display quality is better than that of mechanical counters, and it has the advantage of being able to exchange data with other devices.

[Problems with conventional technology]

However, with counter devices using 0MO3 RAM or EE-FROM as described above, they are controlled by the CPU, so if a situation where the CPU goes out of control occurs, the contents of the counter may be written incorrectly. There is a risk of destruction. A watchdog timer is known as a means of detecting a runaway CPU, but it takes a certain amount of time to detect a runaway CPU, so if the CPU runs out of control within that time, There is still a risk of data destruction as mentioned above. Therefore, even if a watchdog timer is used, it is difficult to reliably protect the contents of the counter.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide an electronic counter device that reliably protects data even when the CPU goes out of control.

[Key points of the invention]

According to the present invention, the above object is achieved as described in 1. α means and cough,
An electronic counter device characterized by having a writing means for corrupting count data in the means, and a control means for permitting the writing means to write data to the storage means when a specific signal is output. This is achieved by providing

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a counter device of the present invention. The present embodiment will be explained by taking as an example a counter device used in an electrophotographic copying machine.

In FIG. 1, reference numeral 1 denotes a CPU (processor circuit), which controls the operation of the electrophotographic copying machine according to a control program stored in a ROM (read only memory) 2. As shown in FIG. 3 is RAM (random access memory), 4 is EE-
FROM, which has the function of electrically erasing and writing data, and is a counter that counts the number of sheets printed by the electrophotographic copying machine by sending and receiving data through the data bus 5 using the RAM 3 and CPUI, as described later. Configure the device.

Further, 6 is an address decoder, and an address bus 7
It is connected to the ROM2, RAM3, EE-PROM4, output latch 8.9, input cover sofa 10.11, and write control circuit 16.

The address decoder 16 is configured to decode the addresses of each part based on instructions from the CPUI. The output signal from the output channel 8 is input to a 7-segment display 12 using light emitting diodes, and the number of prints is displayed in accordance with instructions from the CPUI, as will be described later. The output of the output latch 9 is outputted to a load 12, that is, each component such as a photoreceptor driving device, a developing device, etc., which performs an electrophotographic process. Furthermore, sensor outputs and the number of prints are input to the input cover sofa 10.11 from an input unit 15 consisting of various sensors 14 and a keyboard on an operation panel. C
The PUI controls the printing of a set number of sheets based on this input, and also controls the operating conditions based on the sensor output.

Although the write control circuit 16 will be described in detail later, the write control circuit 16 is an EE-PR
This is a circuit that controls to permit data writing only within a permitted period when writing print number data to the OM4.

FIG. 2 is a circuit diagram showing a specific configuration of the write control circuit 16.

In the figure, 17 indicates a flip-flop circuit (hereinafter referred to as FF circuit) 18 that uses specific data sent from the CPUI.
This is an AND circuit that sends out a DDEC signal to the DDEC signal. The specific data is sent to the write control circuit 16 through the address bus 5, and this data is sent before the CPUI writes the print number data to the EE-PROM 4. Further, as the specific data, in this embodiment, 55H is used in hexadecimal notation, and 01010101 is used in binary notation. D? of each input terminal of the AND circuit 17 from the higher order of this specific data? , D6
．． They are input in the order of D5...Do.

In this case, the input terminal D+ of the AND circuit 17.

D3. D5. Since each D7 is provided with an inverter circuit 19, when data 55H is input, the output of the AND circuit 17 rises to a high level. To explain this operation using the time chart shown in FIG.
When U1 writes data 55H @ to address ADECI, data 55H shown in FIG.
(is sent out, and as shown in FIG. 3 fb), the AND circuit 1
A high level DDEC signal is sent from the FF circuit 7 to the FF circuit 18.

On the other hand, since the CPUI accessed the address ADEC1, the output of the address bus 7 is decoded by the address decoder 6, and as shown in FIG.
l becomes low level. ADECl is input to the CK (clock) terminal of the FF circuit 18, and when the CPU accesses the next address, when this ADECl rises, the DDEC (high level) is input to the FF circuit 18.
Incorporate into. As a result, as shown in Fig. 3 (dl), F
A WEN (write enable) signal is outputted from the Q output of the F circuit 18, which allows the CPU to write data into the EE-PROM 4, and the state is set to a standby state for data writing to the EE-FROM 4. The WEN signal is output to the NAND circuit 20, and in this state, the CPU 1 outputs the WR (
By outputting the write) signal to the NAND circuit 20,
From the NAND circuit 20 to EE-P as shown in FIG.
The WR signal is output, and the data being output from the CPU via the data bus 5 is written into the EE-PROM 4.

Furthermore, after writing data to the EE-FROM 4 as described above, the CPU accesses the address ADEC2, and the address decoder 6 receives and decodes this, thereby converting the data to the ADEC2 as shown in FIG. 3(a). falls to low level.The ADEC2 signal falls to the AND circuit 21
is input to the R (reset) terminal of the FF circuit 18 through the
The output of the F circuit 18 (WEN signal) falls to a low level (FIG. 3(d)). Therefore, the low level WEN signal is input to the NAND circuit 20, so the NAND circuit 20 becomes closed. , data writing to EE-FROM4 is prohibited.

Therefore, when writing data to the EE-PR0M4, the configuration allows data writing only when specific data is sent, so if a situation such as the CPU going out of control due to noise occurs, the above-mentioned problem will occur. The data write conditions will not be satisfied. In this case, EE-FR
Since writing data to OM4 is prohibited,
There is no possibility that data will be written to EE-FROM4 by mistake, and the EIF and -PROM will be reliably written.
4 data can be protected.

Note that in FIG. 2, the RES signal is a reset signal for setting the write control circuit 16 to the initial state when the device is powered on.

〔Effect of the invention〕

As explained above, according to the present invention, when writing data to EE-FROM, writing of data is permitted only when specific data is sent, so a situation where the CPU goes out of control may occur. In this case, data writing to the EE-FROM can be prohibited. Therefore, the CPU
This prevents malfunctions such as erroneous data being written to the EE-PROM when the EE-FRO goes out of control.
M's data can be protected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the main part of the present invention, and FIG.
) to (g) are time charts showing the operation of the above embodiment. 1...CPU. 2...ROM. 4...EE-PROM. 6... Address decoder, 16... Write control circuit. Patent Applicant: Casio Computer Co., Ltd. Above: Casio Electronics Co., Ltd. (Procedural Amendment Written Form) November 10, 1985 2, Title of Invention Electronic Counter Device 3, Relationship with the Person Who Makes the Amendment Case Patent Applicant Address: Tokyo 2-6-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Name (
144) Tadashi Kashio, Representative of Casio Computer Co., Ltd.
Address: 2-229 Sakuragaoka, Higashiyamato City, Tokyo Name
Casio Electronics Co., Ltd. Representative Tadao Kashio 4, Agent 8102 = (03) 238-0031 Address 6-1-18-7 Kojimachi, Chiyoda-ku, Tokyo, Line 1 of the 10th column of the statement of contents of the amendment ~In the second line, “Figure 3 (al~
fg) is a time chart showing the operation of the above embodiment. "Figure 3 is a time chart showing the operation of the above embodiment, where f8) is a waveform diagram of the specific data 55H, (bl is a waveform diagram of the DDEC signal output from the AND circuit 17, and (C1 is the ADHC input to the FF circuit 18
I signal waveform diagram, (dl is a waveform diagram of the WEN signal output from the FF circuit 18, (e) is a WR multiplied signal waveform diagram output from the CPU 1, (fl is the EEPWR (8 Waveform diagram of No. (g) is AND circuit 2
FIG. 1 is a waveform diagram of a τ-ding-ding τ-ding signal inputted into the circuit 1; ” he corrected.

Claims (1)

[Scope of Claims] A storage means, a writing means for writing count data into the storage means, and a control means for permitting the writing means to write data to the storage means when a specific signal is output. An electronic counter device comprising: