JPH05197627A - Eeprom write protecting method and information processor - Google Patents

Abstract

PURPOSE:To prevent data in an EEPROM from being destroyed by the run-away of a program or the like by canceling a write inhibit state only when a specified key is set from a central processing unit. CONSTITUTION:This information processor with the built-in EEPROM is composed of a CPU 1, EEPROM 2 readable/writable from the CPU 1, decoder 3 to control read/write to the EEPROM 2 and register 4 to be set from the CPU 1 and only when a specified key code (Rxx) 15 is set from the CPU 1 to the register 4, a write signal (WE) 16 to the EEPROM 2 is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM (Ele
ctric Erasable Programmable
The present invention relates to an EEPROM write protection method which is used in an information processing apparatus having an e-Read Only Memory (electrically erasable / writable read-only memory) and is controlled by key setting from a central processing unit.

[0002]

2. Description of the Related Art An EEPROM is an electrically erasable / writable ROM. Therefore, it can be easily written from a processor in a state where it is incorporated in a system, and since the written data is stored even after the power is turned off, it is widely used as a non-volatile memory.

Since the control circuit of the EEPROM can be easily manufactured like other general memory devices, the write protection circuit has not been conventionally provided.

[0004]

As described above, in the conventional EEPROM control circuit, no protection circuit is provided for the write operation from the processor.
If the EEPROM area is erroneously written due to a program runaway or the like, there is a drawback that the data in the EEPROM may be destroyed.

An object of the present invention is to provide an EEPROM write protection method and a data processing apparatus using the same, which eliminates the above-mentioned drawbacks and prevents data destruction of the EEPROM due to program runaway or the like.

[0006]

According to the EEPROM write protection method of the present invention, an EEPROM in an information processing apparatus including a central processing unit, a memory control unit and an EEPROM is provided.
In the M write protection method, the memory control device outputs a write signal to the EEPROM when a specific signal for permitting writing is input from the central processing unit.

The information processing apparatus of the present invention comprises a central processing unit and an EEP which can be read and written by the central processing unit.
In an information processing device comprising a ROM and a memory control device for outputting a read / write signal to and from the EEPROM, a specific signal which is set by the central processing unit and permits the memory control device to write is specified. The memory control device includes a signal generating circuit, and the memory control device includes means for outputting a write signal to the EEPROM when the specific signal is input.

In the information processing device of the present invention, it is preferable that the memory control device is a decoder and the specific signal generating circuit is a register.

[0009]

The memory controller outputs the write signal to the EEPROM only when the specific signal for permitting the write is input from the central controller.

As a result, E due to program runaway, etc.
Erroneous writing to the EPROM is eliminated, and data destruction of the EEPROM can be prevented.

As an information processing apparatus to which this is applied, for example, a decoder is used as a memory control device, and a register is provided as a specific signal generating circuit for generating a specific signal for permitting writing by setting from a central processing unit. Will be realized in.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the essential parts of an embodiment of the information processing apparatus of the present invention.

In this embodiment, a central processing unit (hereinafter, CPU
Say. ) 1, an EEPROM 2 readable / writable from the CPU 1, and a decoder 3 as a memory control device for outputting a read signal (RE) 17 and a write signal (WE) 16 to the EEPROM 2, CPU, which is a feature of the present invention
The decoder 3 is provided with a register 4 as a specific signal generating circuit that outputs a key code (R _XX ) 15 as a specific signal which is set by 1 and permits writing to the decoder 3.
Includes means for outputting a write signal 16 to the EEPROM 2 when the key code 15 is input.

The CPU 1 has an address bus 11, a data bus 12 and a read / write signal (RW) 14.

Next, the operation of this embodiment will be described.

In the present embodiment, the area of the EEPROM 2 is allocated on the address map of the CPU 1, and the decoder 3 decodes the upper address to decode the EEPROM.
It is determined whether the address space is M2. Furthermore, CPU
The area of the register 4 is allocated on the address map 1 and the CPU 1 can set arbitrary data in the register 4 via the data bus 12, and the register 4 stores the set value. The value stored in the register 4 is input to the decoder 3 as the key code 15 and compared with the key code in the specific decoder 3. If the access code of the CPU 1 is the address space of the EEPROM 2 and the write operation is performed, and the key code 15 from the register 4 matches the key code in the decoder 3, the EEPR
The write signal 16 is output to OM2.

On the other hand, the CPU 1 accesses the EEPROM
If the address space is 2, the write operation is performed, and the key code 15 from the register 4 does not match the key code in the decoder 3, the write signal 16 to the EEPROM 2 is not output.

The access of the CPU 1 is EEPROM
In the case of the address space of 2 and the read operation, the read signal 17 is output to the EEPROM 2 regardless of the value of the register 4.

Further, the initial value of the register 4 is cleared to "0" by the reset signal 14, and the key code is set to a value other than "0" to prevent erroneous writing of the EEPROM at the time of start-up. ing.

Next, the EEPROM access procedure is shown in FIG.

In the case of writing in step S1, CPU1
First sets a key code in the register 4 (step S2). Next, the data is written to an arbitrary address of the EEPROM 2 (step S3). Finally, the register 4 is cleared (step S4).

In the case of reading, the CPU 1 does not operate the register 4 and simply reads the data at any address of the EEPROM 2 (step S5).

By observing the above EEPROM access procedure, the data in the EEPROM 2 can be protected from erroneous writing.

For example, if the program runs out of control, CP
U1 often accesses an undefined address. CP
When U1 accesses an undefined address, a bus error occurs, and the CPU 1 performs exception processing, so stack saving is performed. At this time, if the stack pointer value is invalid, the stack saving operation causes further undefined access. Cause a bus error. Stack addresses are sequentially incremented because stack saving is performed indefinitely due to repeated bus error exceptions. Eventually E
The address of EPROM2 is reached and the contents of EEPROM2 are destroyed.

However, according to this embodiment, even if the EEP
Even if the writing operation to the ROM 2 is performed, the logical expression of the decoder 3 is as follows: WE = A _XX · RW ₁ · R _XX (where A _XX is the address data of the EEPROM 2, R
W ₁ is an inverted signal of RW), and since the key code is not set in the register 4, the write signal 16 to the EEPROM 2 is not generated. This allows EEPRO
It is possible to prevent erroneous writing to M2.

[0027]

As described above, according to the present invention,
To prevent the data destruction of the EEPROM due to the program runaway etc. by providing the register which can be set by the CPU and configured the decoder that can output the write signal to the EEPROM only when the value of this register matches the key code. Can be done, and the effect is great.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of an information processing apparatus of the present invention.

FIG. 2 is a flowchart showing an access procedure of the EEPROM.

[Explanation of symbols]

1 central processing unit (CPU) 2 EEPROM 3 decoder 4 register 11 address bus 12 data bus 13 read / write signal (RW) 14 reset signal 15 key code (R _XX ) 16 write signal (WE) 17 read signal (RE)

Claims (3)

[Claims] 1. Central processing unit, memory control unit and E
EEPROM in information processing device having EPROM
In the write protection method, the memory control device receives the specific signal from the central processing unit to permit writing, and the memory control device receives the EEPRO.
EEPR characterized by outputting a write signal to M
OM write protection method. 2. A central processing unit, an EEPROM readable / writable from the central processing unit, and this EEPROM.
In a data processing device including a memory control device for outputting a read / write signal to M, a specific signal generation circuit for outputting a specific signal set by the central processing unit and permitting writing to the memory control device is provided. The information processing apparatus, comprising: the memory control device including means for outputting a write signal to the EEPROM when the specific signal is input. 3. The memory controller is a decoder,
The information processing apparatus according to claim 2, wherein the specific signal generation circuit is a register.