JPS6346813A - Timing generator circuit - Google Patents

Abstract

PURPOSE:To contrive to attain stable and high speed operation by counting an output signal of a count period generating circuit 5 as a clock and using a low speed counter so as to operate the count of the count period generator cyclicly by the number of count data. CONSTITUTION:An output of the count period generating circuit 5 is given to one data input of shift registers V1-V8 of an added time shift register 6 in common. Then a positive pulse is outputted to the inverse of Q of a gate circuit t1 being a component of a dummy period generator 4. Its output is a rate clock. Then the rate clock output is a load signal to a low speed stage counter 2 and an added time register 8 and also given to a gate circuit t2 of the 2nd stage of the generator 4. Then the output of the circuit t2 is given to a gate circuit S1 of the generator 5 to start the next rate. The operation above is repeated and the rate clock is outputted one after another.

Description

[Detailed description of the invention]

・A. ``Object of the invention'' (7jc Industrial application field) The present invention relates to an improvement of a timing generator circuit. (Prior art) A timing generator circuit is used in a digital ■C tester, etc. , for example, is a circuit that has the function of generating a 1:% main operating frequency Wlffi signal (hereinafter referred to as rate clock).In addition to the rate clock, it also has the function of generating an arbitrary delay and width for this signal. It also has an 8M capability to generate format clocks and strobe clocks with a rate ratio of 1.
Because it is a circuit with the same function as the means of generating Kotoku,
In this specification 1g, the rate

The present invention will be explained by taking as an example a circuit that avoids the occurrence of [=1]. FIG. 5 shows a conventional rate converter circuit. In the figure, there are a few (for example,
16 sets) of time width designation data (shi~[...data) are stored, and one rate data of this width is designated and read out using the rate selection signal. This leh 1
~・Data is clocked at a high speed clock (e.g. 500MHz
) and a low-speed counter 53 consisting of a 4-bit ripple-through down counter driven by a synchronous down counter of approximately 20 bits.
It will be pitted. The most significant digit of the high speed counter 52 is the clock of the low speed counter 53 (31,25M Ll z
). When the operating speed of the circuit is maintained, the high-speed stage control circuit 54J3 and the low-speed stage control circuit 55 start the rate clock at the IC where both counters 52 and 53 count down at 4100 MHz and the counter frequency becomes zero. Outputs a pulse that increases, and at Ji1, the next rate...
Set data value. In Figure 6, 1. ! , shows how rate signals with a resolution of 2+16 are sequentially generated by such operations. In FIG. 6, rate 1 and rates 1-4 have the same rate memory contents designated by rate selection IJ'J 4B %. [Problems to be Solved by the Invention] However, the 41 means has the following problems. In real circuits, the highest speed operation is possible [:CL logic A
Even if you use zeta, the maximum guru frequency is 600
M N z PI Maro is the limit. control circuit, 54;
55 is also constituted by a gate element etc. with a propagation delay time of 0.5 to 10S. Therefore, theoretically, even if the next operation is started after accurate and reliable zero detection, the timing is actually already slow due to the propagation time of the gate element, etc. 3. Therefore, In particular, regarding the Pi speed control circuit 54, there are many delay lines (5 theory PJ!
It is constructed by combining elements and detects a chain several counts before zero, assuming a delay, instead of zero detection. In addition, in order to set the rate data without disturbing the clock count of 20b, critical control is required on the r mink.
Especially li! There is a problem with the screen that needs to be fixed. There is also the problem that it includes Kyoko, which is not suitable for IC implementation such as delay lines. An object of the present invention is to provide a timing generator circuit that is capable of high-speed operation, does not include elements such as delay lines that cannot be integrated into an IC, and does not require individual adjustment. ``Structure of the Invention'' (Means for Solving the Problems) In order to solve the above problems, the present invention stores counter data (N) and addition (14-interval data (1)) at F8. A dummy period optical generator that generates a dummy period (-'A), a count period generator that generates a count period ('I's), and a period between (=11B) (=11B). -r-c) is introduced and a counter filter (N) is introduced, and the output signal from the photogenerator is used as a clock for a count of 1υJ, and the counter is divided into four numbers.・There is a low-speed Q counter that circulates the 4 numbers of the data generator and 14 times the number of data. (Actual drop example) Below are the drawings. The present invention will be explained in detail using Figure 1. Figure 1 is a block diagram showing a practical example of the present invention, and Figure 2 is a diagram showing the concept of shortening the time width. , the present invention will be explained using FIG. 2. In the present invention, each time width of the rate clock is
It is divided into a time period A, a time period 1B, and a cutting time C. The TA during the dummy period is the rate
The operation of loading the next rate into the low-speed stage counter 2 and the additional time register 8 takes 17 to 1 νJ. This IIIJ space A usually only needs to be about 4 ns, and in the following explanation, this dummy period is set to −rA=4 ns. Moraron, 500M)-12 glue L: If the knock frequency is set to another frequency, this dummy 1g1 interval will be different. The count period Ta is a count period between the clock I and the generator 55.
For example, at a high speed of 500MHz,
The number of times specified in memory 1 is N. C) 81 losses were repeated.
It is between ill. b.] Addition time Tc is the desired rate time (To) by 1
′, it constitutes a fraction of time. Therefore, dc=To-dcA-T-a47r! There is a person in charge of Il. In FIG. 1, 1 is a rate memory, which stores data constituting each rate time, that is, the number of times N of counting is repeated with the photogenic crystal during the counting period, and the data of additions 11 and 1c between '1' and 11, which are written in bamboo. te Jj ＜It is a thing. 2 is a low speed stage counter, for example, a 20-bit synchronized booth counter. This low speed gear counter 2 is set with data representing the number of times N for repeating the rate dials 1 to 5. Then, an output signal from a count period generator, which will be described later, is introduced and the set N is counted. When the signal becomes N-0, this signal is detected by the zero detection circuit 3 at the next stage. Reference numeral 4 denotes a dummy period generator, which transfers a signal introduced from an additional time generator, which will be described later, to the next stage after a delay in the dummy period generator A or U described in FIG. Further, a desired rate clock is output from the dummy period generator 4. Incidentally, this rate clock is applied as a load signal to the additional time register 8 which is synchronized with the low speed stage counter 2. Reference numeral 5 denotes a generator 281111, which delays the signal introduced from the dummy period generator 4 by a count period TB and transfers it to the next stage. 7 is a switch, and when the zero detection circuit 3 detects 0 and the signal C is not generated, as shown in FIG. That's what I do. Then, when a signal indicating that 0 is detected, the output of the count period generator 5 is changed to
9115 to transfer to the shift register for the first time. 6 is an additional time shift register, and 8 is an additional time register. The additional time shift register 6 and additional time register 8 constitute an additional time generator 9. The additional time register 8 is read from the rate memory 1 in FIG. 2, +!
1111 "1711 Time Tc is optically inputted with data D, and this data D is input into the additional time shift register 6 at a predetermined timing. Count period generator 5 and A high-speed clock of, for example, 500 MHz is applied to the additional time shift register 6. Fig. 3 is a diagram showing a specific example of the circuit shown in Fig. 1. However, the description of the rate memory 1 in Fig. 1 is are omitted. In Figure 3, 1 and 2 are low speed counters, and the first
This is explained in the figure. However, the low speed counter 2 shown in FIG. 3 also includes the function of the zero detection circuit 3 shown in FIG.
1) Drive the gate flip-flop S7- which will be described later. 1.1. t2 is a gate circuit constituting the first dummy period generator 4. 51 to S8 are data 1- constituting the count period generator 5.
It is a circuit RF. s7- is a data flip-flop having a function corresponding to the switch 7-7 in FIG.
is controlled by the output 1-I Z RO. ■1 to v8 are the additional time left registers 6 in Fig. 1.
This is a group of gate circuits that make up the . d1 to d8 are a group of gate circuits constituting the 6I addition time register shown in FIG. This gate circuit artN~
Additional time data D is set in d8 from the rate memory 1 at a predetermined timing. In addition, in FIG. 3, there is J3, the opening that constitutes the dummy period generator 4, t2, and the count period generation product 5, and the M4 forming sl.
~sJ3, additional 1F! f rr'a generator 9 to ml-
yyl~y8゜(11~([For each gate circuit element in 8, (a) and (b) in Fig. 3 are used. D2〉, this is the case where there are two clock signals (C1, C2), and these four signals are received by two OR gates and introduced into a D type flip-flop (hereinafter simply referred to as -FF). ([1) is the case where there is one data ε clock signal each, and D-FF is used. In (), for example, sl, S8. ([1) is used for dl and t2. InnoJ5, shown in Fig. 3, No. 1 IN[T is a signal to bring the circuit to the initial state, and in the following operation explanation, it will not be particularly These are unrelated signals. Figure 4 is a time chart showing the signal waveforms of each part of the circuit in Figure 3, and the symbols at the left end of each waveform match the component numbers in Figure 3. Note that S7 Those with bars as shown in the figure indicate the meaning of the signals in 6 of the flip-flop.
The operation of the circuit shown in FIG. 4 will be explained with reference to FIG. The clock signal that operates Figures 1 and 3 is 500M
Hz (see CI-OCK in FIG. 4). Therefore, the period II of one clock is 2 ns. The count period generator 5 (S1 to s8 in FIG. 3) is 2n
It constitutes a shift register, and in the tXs3 diagram,
An example of the configuration of n-3 is shown. Of course, it is limited to n=3, not 1. When a positive pulse is applied from the gate circuit [2 of the dummy period generator 4 to the gate circuit S1 of the count period generator 5,
This pulse is the output 1 of the low speed counter 2
Unless RO becomes (in Figure 4, output IZERO
(as long as °″h i g h ”) count period occurs:
'95 (shift registers 51 to S8). For the shift from Sl- to S8, 2 ns x 8 stages - 1 ens (62,5 MHZ)
It takes. The output of the gate circuit S8 is the low speed counter 2.
clock. Low speed counter 2 is rate memory 1
From the value of the counter data N introduced from , it counts down every 16 nS, and finally, the output of the low speed counter 2 becomes . As a result, when the signal H2ERO becomes "low" (see t-IZERO in FIG. 4), the gate time 'tFIs7
-1fi Reset by 1 clock time. As a result, the Q of the gate circuit S8, into which the Q of the gate circuit S7 and the Q of s7' are introduced as data, becomes 0'', so the circulation of the count period generator 5 is stopped.Then, s7' of FIG.
The pulses are applied to the additional time shift register 6 (shift registers v1 to v8). On the other hand, the additional time register 8 (register from old to d8) is set with additional data (D) read from the rate memory 1.The timing of the setting is as shown in FIG. This is the rising edge of the pulse.The value of this additional time data (D) is connected to one side of the clock terminals ■1 to v8, so if "1'° is hit, the value of the additional time data (D) is determined by the gate circuit ■1. ~v8 clock input [IW]
D-FF glue shown in Figure 3 (A) [1 click input]
is always “1°”, so the clock is inhibited. The output of the count period generator 5 (in Fig. 3, the gate circuit s
The outputs Q) of 7' are commonly connected to one side of the data inputs of the shift registers v1 to v8. For example, if the additional time data (D) is d1 to d8-11111000, the gate circuit s
At the next clock after the positive pulse of v6. v7
゜v8 is set, and ■1 to v5 remain reset because the clock inputs of D, -FF shown in (a) of Fig. 3 are at a high level. Therefore, (1-v8 = QQ...0111). Due to the subsequent clock, 000...011 → 000...00
1 → 000...000 will be shifted 1 hair. Since the gate circuit 1 constituting the dummy period generator 4 uses the gate circuits ■7 and ■8 as data inputs, it is reset only at the next clock when v8 changes from "1°2 to "0". A positive pulse is output to Q of the gate circuit t1.Then, this output becomes the rate clock.The rate clock output serves as a load signal for the low-speed counter 2 and the additional time register 8, and at the same time is used as a dummy period generator. The output of the gate circuit [2 is given to the gate circuit s1 of the count period generator 5 to start the next one note. By repeating the above operation, , the rate clock can be outputted one after another. Figure 4 shows that the rate clock is 40 ns and 1 sec.
[This shows the stand used.] The breakdown of this rate time is as follows. Dummy period TA: '40S Count period 1'B: 32ns (16nsx
N, N-2>Additional time T (H: 4nS) In the above, the number of bits of the dummy period generator 4 is set to 2, but the same applies to 1, 3, 4, etc. Effects'' As described above, according to the present invention, the following effects can be obtained: ■ The upper limit frequency of the operation of the entire timing generator circuit is determined by the high-speed stage counter 52 and the high-speed stage side 111 in the conventional circuit shown in FIG. In the present invention, it is determined by the speed of the count period generator 5. In the present invention, this part of the count period generator 5 is shifted and
Since it consists only of registers, high-speed operation is possible. That is, the -F limit frequency of the circuit of the present invention is determined only by the operating limit characteristics of the shift register and the signal propagation time through the wiring. ■ No adjustment required like in conventional circuits. (2) Since it does not include a delay line, the present invention is suitable for IC implementation. Compared to the conventional circuit, the number of elements is increased by #Il, but when integrated into an IC, this point hardly becomes a problem. ■ It operates stably because there are no timing critical parts like conventional circuits.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of a timing generator circuit according to the present invention, FIG. 2 is a diagram showing the concept of the present invention, and FIG.
The figure shows a specific example of the timing generator circuit according to the present invention, and FIG.
FIG. 5 is a block diagram of a conventional timing generator circuit, and FIG. 6 is a diagram showing a rate clock generation state. 1...Rate memory, 2...Low speed counter, 4
...Dummy period generator, 5.Count period generator, 6.Additional time shift register, 7.Switch, 8.Additional time register, 9.Additional time generator. ]

Claims (1)

[Claims] A rate memory in which counter data (N) and additional time data (D) are stored, a dummy period generator that generates a dummy period (T_A), and a count period (T_B). By introducing a count period generator, an additional time generator that generates an additional time (T_C), and counter data (N), and counting the output signal from the count period generator as a clock, the number of counter data can be calculated. A timing generator circuit comprising: a low-speed counter for cyclically operating a count of a count period generator.