JPS634665A - Composite transistor - Google Patents

Composite transistor

Info

Publication number
JPS634665A
JPS634665A JP14713486A JP14713486A JPS634665A JP S634665 A JPS634665 A JP S634665A JP 14713486 A JP14713486 A JP 14713486A JP 14713486 A JP14713486 A JP 14713486A JP S634665 A JPS634665 A JP S634665A
Authority
JP
Japan
Prior art keywords
gate
transistor
mosfet
mos
bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14713486A
Other languages
Japanese (ja)
Inventor
Yasumichi Yasuda
安田 保道
Tomoyuki Tanaka
知行 田中
Mutsuhiro Mori
睦宏 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14713486A priority Critical patent/JPS634665A/en
Publication of JPS634665A publication Critical patent/JPS634665A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase working speed by including a circuit element automatically inverting the phase of signal voltage applied to a gate for one MOSFET and the phase of signal voltage applied to the other MOSFET without phase shift. CONSTITUTION:A gate terminal G3 for an MOSFET 4 is connected to a gate G1 for an MOSFET 2. A drain in the MOSFET 4 is connected to a DC power supply through a resistor 5 while being connected to a gate G2 for an MOSFET 3. A source in the MOSFET 4 is grounded or connected to an emitter in a bipolar transistor 1. When a control signal is transmitted over the gate G3 for the MOSFET 4, the phase of the gate G1 connected to the gate G3 and the gate G2 can be inverted, thus easily turn-ON or turn-OFF controlling an MOS bipolar composite type transistor positively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複合型トランジスタ、例えばMO S F E
Tの如きスイッチング半導体装置にかかわり.%に。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a composite transistor, such as a MOSFET.
Involved in switching semiconductor devices such as T. %.

バイポーラトランジスタのベースとエミッタ、コレクタ
間に、それぞれM08FBTを並列接続して複合−体化
したMQS複合型トランジスタに関するO 〔従来の技術〕 トランジスタ等の半導体装置が電力用スイッチング回路
に用いられる場合、耐圧、オン抵抗、及びスイッチング
速度は重要な性能要素である。
O related to an MQS composite transistor in which a M08FBT is connected in parallel between the base, emitter, and collector of a bipolar transistor. [Prior art] When a semiconductor device such as a transistor is used in a power switching circuit, the breakdown voltage , on-resistance, and switching speed are important performance factors.

単体のMOSFETやバイポーラトランジスタでは、こ
れらの性能を丁べて満足することが極めて困難なため、
近年、  MOSFETとバイポーラ素子を組合せたM
OSバイポーラ複合素子の開発が進められている(特開
昭57−196560号公報)。
It is extremely difficult to satisfy these performances with a single MOSFET or bipolar transistor, so
In recent years, M which combines MOSFET and bipolar elements
Development of an OS bipolar composite device is underway (Japanese Patent Application Laid-open No. 196560/1983).

第3図は従来の複合型素子の等価回路を示す。FIG. 3 shows an equivalent circuit of a conventional composite type element.

lはコレクタCおよびエミッタEを備えたバイポーラト
ランジスタ、2はMOS )ランジスタである・ MOS  トランジスタ2のゲートGに正の電圧信号を
加えると、MOS トランジスタ2が導通し。
1 is a bipolar transistor with a collector C and an emitter E, and 2 is a MOS transistor. When a positive voltage signal is applied to the gate G of MOS transistor 2, MOS transistor 2 becomes conductive.

MOS  1”ランジスタ2が導通し、MOS  トラ
ンジスタ2を通してバイポーラトランジスタ1にベース
電流が供給される。すなわち、バイポーラトランジスタ
1のベースに少数キャリアが注入される。
The MOS 1'' transistor 2 becomes conductive, and a base current is supplied to the bipolar transistor 1 through the MOS transistor 2. That is, minority carriers are injected into the base of the bipolar transistor 1.

これによって、バイポーラトランジスタlが導通する。This causes the bipolar transistor l to conduct.

一方バイボーラトランジスタlがターンオフする場合は
、ベースに注入された前記少数キャリアの蓄積効果によ
り、ターンオフタイムが遅延する傾向がある。これを短
縮するには、前述の蓄積効果を低減しなければならない
On the other hand, when the bibolar transistor l turns off, the turn-off time tends to be delayed due to the accumulation effect of the minority carriers injected into the base. To shorten this, the accumulation effect mentioned above must be reduced.

第4図は、ベース中の蓄積キャリアを引き抜く回路を付
加した従来のMOSFET複合スイッチング牛導体装置
の等価回路を示す(第17回、固体素子・材料コンファ
レンスの拡大アブストラクト:Extended  A
bstracts  of  the  17 th 
 eonfer−ence  on  5olid  
8tate  Devices  and  Mata
rI−als、 TOk7(le 1985年第389
〜392頁)。
Figure 4 shows an equivalent circuit of a conventional MOSFET composite switching conductor device with an added circuit for extracting accumulated carriers in the base (Extended A of the 17th Solid State Elements and Materials Conference).
bstructs of the 17th
eonfer-ence on 5olid
8tate Devices and Mata
rI-als, TOk7(le 1985 No. 389
~392 pages).

第4図の回路において、バイポーラトランジスタlをタ
ーンオンさせる場合は、MOS  トランジスタ2のゲ
ー)Gllこ正の電圧を加えてこれを導通させると同時
に1MOS1−ランジスタ3のゲートG、はエミッタと
同電位に制御してこれを非導通状態に保持する。
In the circuit shown in Fig. 4, when turning on the bipolar transistor 1, a positive voltage is applied to the gate of MOS transistor 2, Gll, to make it conductive, and at the same time, the gate G of MOS transistor 1 becomes the same potential as the emitter. It is controlled to maintain it in a non-conducting state.

一方、ターンオフ時及び定常オフ時には。On the other hand, during turn-off and steady-state off.

MO3FET2のゲートG1はエミッタと同′亀位とし
てこれを非導通状態にすると同時に、MOSFET3の
ゲートG2に正の電圧を印加し1M08FI!tT3を
導通させる。
The gate G1 of MO3FET2 is placed at the same level as the emitter to make it non-conductive, and at the same time, a positive voltage is applied to the gate G2 of MOSFET3 to 1M08FI! Make tT3 conductive.

これによって、バイポーラトランジスタlのベース中の
蓄積キャリアがMO13FBT 3  を通してエミッ
タEに導びき出され、バイポーラトランジスタ1はター
ンオフされる。
As a result, accumulated carriers in the base of the bipolar transistor 1 are led out to the emitter E through the MO13FBT 3 , and the bipolar transistor 1 is turned off.

以上から明らかなように、第4図の装置のターンオン、
ターンオフを実行するときは、2つのMOSFET2.
3のゲートG、 、 G、に、たがいに逆位相の制御電
圧を印加する必要がある。
As is clear from the above, the turn-on of the device shown in FIG.
When performing turn-off, two MOSFETs 2.
It is necessary to apply control voltages with opposite phases to the gates G, , G, of the three gates.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

そのため、従来は 2(@の信号発生器を用い、位相お
よび1王の異なる2つの制御信号を発生していたが、2
つの制御信号に位相のずれが生じ易いという問題があっ
た。2つの制御信号に位相ずれを生ずると、明らかなよ
うに、ターンオンおよびターンオフの応答が遅くなり、
動作の高速化が妨げられる欠点を生ずる。
Therefore, in the past, a 2(@) signal generator was used to generate two control signals with different phases and 1
There is a problem in that a phase shift is likely to occur between the two control signals. Obviously, if the two control signals are out of phase, the turn-on and turn-off responses will be delayed.
This results in the drawback that speeding up the operation is hindered.

本発明の目的は、MO3バイポーラ複合トランジスタの
一方のMOSFETのゲートに加える信号電圧の位相と
、他方のMOSFETのゲートに加える信号電圧の位相
を自動的に、かつ位相ずれ無しに逆転させる回路要素を
含む複合型トランジスタを提供するにある。
An object of the present invention is to provide a circuit element that automatically reverses the phase of a signal voltage applied to the gate of one MOSFET of an MO3 bipolar composite transistor and the phase of a signal voltage applied to the gate of the other MOSFET, without any phase shift. To provide a composite transistor including the present invention.

〔問題点を解決するための手段〕[Means for solving problems]

前記問題点を解決するために1本発明においては、第4
図の従来例のように、バイポーラトランジスタのベース
−コレクタおよびベース・エミッタ間にそれぞれ並列に
第1および第2 MOSFETを接続してなる複合型ト
ランジスタにおいて、第2M08FET のゲートとバ
イポーラトランジスタのエミッタ間に第3M08FET
 を並列接続し、第3M03FETのゲートを第1 M
OSFE’l’ のゲートと共通接続すると共に、抵抗
、あるいは、第3M08FET と相補型の第4M08
FET を介して、第2M08F’ETのゲートを直流
電源に接続する構成を採用した。
In order to solve the above problems, in the present invention, the fourth
As in the conventional example shown in the figure, in a composite transistor in which first and second MOSFETs are connected in parallel between the base and collector of a bipolar transistor and between the base and emitter, respectively, there is a connection between the gate of the second MOSFET and the emitter of the bipolar transistor. 3rd M08 FET
are connected in parallel, and the gate of the third M03FET is connected to the first M03FET.
Commonly connected to the gate of OSFE'l', and connected to a resistor or a fourth M08 which is complementary to the third M08 FET.
A configuration was adopted in which the gate of the second M08F'ET was connected to a DC power supply via an FET.

〔作用〕[Effect]

第3 MOSFgT gよぴ第1 MOSFFi’l’
 が、オン状態にあるとき、第2M08FETのゲート
電位は低レベルになるので、第2M08FETはオフ状
態となり、バイポーラトランジスタはオン状態となる〇 一方、第3M08FETおよび第1M08FETが。
3rd MOSFgT gyopi 1st MOSFFi'l'
is in the on state, the gate potential of the second M08FET is at a low level, so the second M08FET is in the off state and the bipolar transistor is in the on state. On the other hand, the third M08FET and the first M08FET are in the on state.

オフ状態にあるとき、12M08FET のゲート電位
は高レベルになるので、第2M08FET  はオン状
態となり、バイポーラトランジスタはオフ状態となる。
When in the off state, the gate potential of the 12M08FET is at a high level, so the second M08FET is in the on state and the bipolar transistor is in the off state.

すなわち、第1および第2M08FETのゲートに印加
される信号電圧の位相は、自動的に、かつ位相ずれを生
ずることなしに、常に反対位相を保つことになり、ター
ンオン、ターンオフ時の動作おくれを生ずることがなく
なる・ また、第3M08FET  と相補型の第4M08FE
Tを介して、第2M08FBT  のゲートを直流′1
源に接続する構成とすれば、第2M08FBT  のゲ
ートが直流電源およびバイポーラトランジスタのエミッ
タのいずれか一方に、選択的に切換接続されることにな
り、制御回路部に抵抗成分を含まないので、この部分で
の電力損失を極めて小さくすることができる。
In other words, the phases of the signal voltages applied to the gates of the first and second M08FETs are automatically and always kept in opposite phases without causing a phase shift, resulting in a delay in operation during turn-on and turn-off. In addition, the 4th M08FE, which is complementary to the 3rd M08FET,
DC'1 is applied to the gate of the second M08FBT via T.
If the configuration is such that the gate of the second M08FBT is selectively connected to either the DC power source or the emitter of the bipolar transistor, the control circuit section does not include a resistance component. It is possible to extremely reduce power loss in this section.

〔実施例〕〔Example〕

第1図は、2個のMOSFETを有する複合型トランジ
スタと、それぞれのMOSF ETのゲートに加える電
圧信号の位相を互に反転する回路要素とを含む1本発明
の一実施例の回路構成を示す−4および5は1MOSバ
イポーラ複合型トランジスタのゲートG2に〃Ωえる信
号゛感圧の位相を反転する回路を構成するMOSb’E
T および抵抗器を示す。
FIG. 1 shows a circuit configuration of an embodiment of the present invention, which includes a composite transistor having two MOSFETs and a circuit element that mutually inverts the phases of voltage signals applied to the gates of the respective MOSFETs. -4 and 5 are MOSb'E that constitutes a circuit that inverts the phase of the pressure-sensitive signal applied to the gate G2 of the 1MOS bipolar composite transistor.
T and resistor are shown.

図に示すように、MOSFET 4のゲート端子G。As shown in the figure, the gate terminal G of MOSFET 4.

はMOSFIET2のゲートGIに接続される。is connected to the gate GI of MOSFIET2.

MOSFET4 のドレインは抵抗器5を介して直流電
源に接続されると共に、MOSFET3  のゲートG
2に接続される。
The drain of MOSFET4 is connected to the DC power supply via resistor 5, and the gate G of MOSFET3 is connected to the DC power supply via resistor 5.
Connected to 2.

MO3FET 4のソースは、接地されるか、または、
バイポーラトランジスタlのエミッタに接続される。
The source of MO3FET 4 is grounded or
Connected to the emitter of bipolar transistor l.

このような構成において%MOSFET4 のドレイン
に抵抗器58介して直流電圧(約5v)を印加し、ゲー
トG8に10〜15Vの制御電圧を加えると、MOi9
FET 4が導通ずる。
In such a configuration, if a DC voltage (approximately 5V) is applied to the drain of %MOSFET4 through the resistor 58 and a control voltage of 10 to 15V is applied to the gate G8, MOi9
FET 4 becomes conductive.

その結果、ゲートG2  の電圧はゲートしきい値電圧
以下となり、MOSFET3がオフとなる。これと同時
に%MOSF’ET2  は導通し、バイポーラトラン
ジスタ1のベースに電流が供給されるので。
As a result, the voltage of the gate G2 becomes lower than the gate threshold voltage, and the MOSFET 3 is turned off. At the same time, %MOSF'ET2 becomes conductive and current is supplied to the base of bipolar transistor 1.

バイポーラトランジスタ1が導通する。Bipolar transistor 1 becomes conductive.

−方バイボーラトランジスタlを阻止状態にする場合は
、ゲートG3に加える制御信号の電圧を。
- When the bipolar transistor l is placed in a blocking state, the voltage of the control signal applied to the gate G3 is set as follows.

ゲートしきい値電圧以下にする。MOfJFgT 4 
がオフとなり、ゲートG、には抵抗器5を通して直流電
圧が印加されるので、MOSFET3が導通する。これ
と同時に、MOSF’ET 2がオフ状態となるので、
バイポーラトランジスタlは急速にオフ状態にされる。
Make it below the gate threshold voltage. MOofJFgT 4
is turned off, and a DC voltage is applied to the gate G through the resistor 5, so that the MOSFET 3 becomes conductive. At the same time, MOSF'ET 2 turns off, so
Bipolar transistor l is quickly turned off.

このように、制御信号をMOSFET4のゲートG3 
 に加えると、これに接続されたゲートG1 とゲート
G、の位相を反対にすることができるので。
In this way, the control signal is applied to the gate G3 of MOSFET4.
By adding this, the phases of gate G1 and gate G connected to this can be reversed.

MOS  バイポーラ複合型トランジスタは容易かつ確
実にターンオンまたはターンオフ制御できるようになる
MOS bipolar composite transistors can be easily and reliably controlled to turn on or turn off.

MOS バイポーラ複合型トランジスタと、前記位相反
転回路要素とから成る本発明の構成において&MO3F
ET4  として日立製作所mMO13FmiiT28
K 296を用い、抵抗器5の抵抗値を5oΩ。
In the configuration of the present invention comprising a MOS bipolar composite transistor and the phase inverting circuit element &MO3F
Hitachi mMO13FmiiT28 as ET4
Using K296, the resistance value of resistor 5 is 5oΩ.

電源電圧を5vとし、位相反転回路を用い、コレクタ・
ベース間の耐圧s o o v、電流容量5人クラスの
MOS バイポーラ複合トランジスタを制御した結果、
MOS  バイポーラ複合壓トランジスタのオフ時のコ
レクタ・エミッタ電圧はコレクターベース耐圧に等しい
耐圧が得られ、オン電流密度は30人/dでありた。
The power supply voltage is 5V, a phase inversion circuit is used, and the collector
As a result of controlling a MOS bipolar composite transistor with a base-to-base withstand voltage S O V and a current capacity of 5 people,
The collector-emitter voltage of the MOS bipolar composite transistor when off was equal to the collector-base breakdown voltage, and the on-current density was 30 people/d.

また、ターンオフ時間は抵抗負荷において0.5μs、
綽導性負荷の場合0.8μsであった◎第2図は、第1
図における位相反転用のMOSFETを、MOSバイポ
ーラ複合複合型ンジスタと同一のシリコンチップ上に一
体化構成した。
In addition, the turn-off time is 0.5 μs in a resistive load.
In the case of a conductive load, the time was 0.8 μs. ◎Figure 2 shows the first
The MOSFET for phase inversion shown in the figure is integrated on the same silicon chip as the MOS bipolar composite transistor.

本発明によるスイッチング半導体装置の断面構造を示す
1 shows a cross-sectional structure of a switching semiconductor device according to the present invention.

+ n 基板11の一主面上にn−層12が生長され、この
n−I@ 12内に、p 領域!3,14゜15が、選
択拡散によって形成される。さらに。
An n- layer 12 is grown on one main surface of the +n substrate 11, and within this n-I@12, a p region! 3,14°15 are formed by selective diffusion. moreover.

前記の各p 領域13〜15の中に1図示のように、 
n 領域21〜26が選択拡散によって形成される・ その後、エミッタ電極31.コレクタ[極32゜および
その他の電極が形成され、さらにPET 2〜4のゲー
ト線像膜(図示は省略)およびゲート電極が、既知の適
切な手段によって形成される。
As shown in each of the above p regions 13 to 15,
n regions 21 to 26 are formed by selective diffusion. Then, emitter electrodes 31. Collector [pole 32° and other electrodes are formed, as well as gate line image films (not shown) and gate electrodes of PET 2-4, by known and suitable means.

第2図の装置が、第1図の回路構成を有し、前述の動作
をすることは、当業者には、容易に理解されるところで
ある。
It will be readily understood by those skilled in the art that the device of FIG. 2 has the circuit configuration of FIG. 1 and operates as described above.

第2図に示した構造では、信号電圧の位相を反転する回
路部分(MOSPET4の部分)は、MOSバイポーラ
トランジス5部分1.2.3からpa接合分離され、同
一チップ内に形成されている。
In the structure shown in FIG. 2, the circuit portion (MOSPET 4 portion) for inverting the phase of the signal voltage is separated from the MOS bipolar transistor 5 portion 1.2.3 by a pa junction and formed within the same chip.

以上のように1本発明の回路要素は複合−体化構造の実
現が容易であり、 MOS バイポーラ複合をトランジ
スタのゲート制御が確実に実行できる。
As described above, the circuit element of the present invention can easily realize a composite structure, and can reliably perform gate control of transistors in a MOS bipolar composite structure.

第1図の実施例では、MOSFET3 のゲート制御信
号を位相反転するために、 MOSF’h:T 4 お
よび抵抗5を用いている。
In the embodiment of FIG. 1, MOSF'h:T 4 and resistor 5 are used to invert the phase of the gate control signal of MOSFET 3.

このために、MOSFET4のオン状態において。For this purpose, in the ON state of MOSFET4.

抵抗5に流れる1流による損失を生ずるの^ならず、ま
た、MOSFET4 がオンからオフに切換わるとき1
MOSFgT3 の実効容量を光域する電流によっても
損失を生ずるなど、電力損失が大きくなる1頃向がある
There is no loss due to the single current flowing through resistor 5, and when MOSFET 4 switches from on to off, 1
There is a tendency for power loss to become large, such as a loss caused by a current that passes through the effective capacitance of MOSFgT3.

これをさけるためには、第1図の抵抗5を。To avoid this, use resistor 5 in Figure 1.

MO!9FET 4と相補型のMOSFET で置換し
、そのゲートをMOSFET4 のゲートG、と共通接
続するのが良い。
MO! It is preferable to replace 9FET 4 with a complementary MOSFET and connect its gate in common with the gate G of MOSFET 4.

明らかなように、この場合は、抵抗成分が無いので、゛
電力損失を生ずることはない。さらに、前記の置換を行
なえば、必要なすべての回路素子を集積化できる利点が
ある。
As is clear, in this case, since there is no resistance component, no power loss occurs. Furthermore, the above substitution has the advantage that all necessary circuit elements can be integrated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるMOSバイポーラ複合
トランジスタの回路図、第2図は本発明の前記実施例を
一つのシリコンチップ上に一体化構成した例を示す断面
図、第3図は従来のMOSバイポーラ複合トランジスタ
の等価回路図%第4図はターンオフ特性を改良した従来
のM OSバイポーラ複合型トランジスタの等価回路図
である。 l・・・バイポーラトランジスタ、2.3.4・・・M
OSトランジスタ、5・・・抵抗器 代理人 弁理士  平  木  道  人第1図 ヒ 第 2 図
FIG. 1 is a circuit diagram of a MOS bipolar composite transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an example in which the embodiment of the present invention is integrated on one silicon chip, and FIG. Equivalent circuit diagram of a conventional MOS bipolar composite transistor Figure 4 is an equivalent circuit diagram of a conventional MOS bipolar composite transistor with improved turn-off characteristics. l...Bipolar transistor, 2.3.4...M
OS transistor, 5... Resistor agent Patent attorney Michi Hiraki Figure 1 H Figure 2

Claims (4)

【特許請求の範囲】[Claims] (1)バイポーラトランジスタと、そのベース・コレク
タ間に並列に接続された第1のMOSトランジスタと、
前記バイポーラトランジスタのベース・エミッタ間に並
列に接続された第2のMOSトランジスタとから成る複
合型トランジスタにおいて、第2MOSトランジスタの
ゲートとバイポーラトランジスタのエミッタとの間に第
3MOSトランジスタのソース・ドレイン回路を並列接
続し、第3MOSトランジスタのゲートを第1MOSト
ランジスタのゲートに接続し、 第2MOSトランジスタのゲートを回路素子を介して直
流電源に接続したことを特徴とする複合型トランジスタ
(1) a bipolar transistor and a first MOS transistor connected in parallel between its base and collector;
and a second MOS transistor connected in parallel between the base and emitter of the bipolar transistor, wherein a source-drain circuit of a third MOS transistor is provided between the gate of the second MOS transistor and the emitter of the bipolar transistor. A composite transistor characterized in that the transistors are connected in parallel, the gate of the third MOS transistor is connected to the gate of the first MOS transistor, and the gate of the second MOS transistor is connected to a DC power supply via a circuit element.
(2)前記回路素子は抵抗であることを特徴とする前記
特許請求の範囲第1項記載の複合型トランジスタ。
(2) The composite transistor according to claim 1, wherein the circuit element is a resistor.
(3)前記回路素子は、第3MOSトランジスタと相補
型の第4MOSトランジスタであり、第3および第4M
OSトランジスタのゲートは共通に接続されたことを特
徴とする前記特許請求の範囲第1項記載の複合型トラン
ジスタ。
(3) The circuit element is a fourth MOS transistor complementary to the third MOS transistor, and the third and fourth MOS transistors are complementary to the third MOS transistor.
2. The composite transistor according to claim 1, wherein the gates of the OS transistors are connected in common.
(4)バイポーラトランジスタおよび第1〜第3MOS
トランジスタが同一の半導体チップに一体化構成された
ことを特徴とする前記特許請求の範囲第2項または第3
項記載の複合型トランジスタ。
(4) Bipolar transistor and first to third MOS
Claim 2 or 3, characterized in that the transistors are integrated into the same semiconductor chip.
Composite transistor described in section.
JP14713486A 1986-06-25 1986-06-25 Composite transistor Pending JPS634665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14713486A JPS634665A (en) 1986-06-25 1986-06-25 Composite transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14713486A JPS634665A (en) 1986-06-25 1986-06-25 Composite transistor

Publications (1)

Publication Number Publication Date
JPS634665A true JPS634665A (en) 1988-01-09

Family

ID=15423334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14713486A Pending JPS634665A (en) 1986-06-25 1986-06-25 Composite transistor

Country Status (1)

Country Link
JP (1) JPS634665A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2638899A1 (en) * 1988-11-10 1990-05-11 Sgs Thomson Microelectronics Bipolar power transistor associated with turn-on and turn-off MOS transistors
JPH06213789A (en) * 1992-09-29 1994-08-05 F Hoffmann La Roche Ag Device for attaching cytological substance to microscope slide and for dyeing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2638899A1 (en) * 1988-11-10 1990-05-11 Sgs Thomson Microelectronics Bipolar power transistor associated with turn-on and turn-off MOS transistors
JPH06213789A (en) * 1992-09-29 1994-08-05 F Hoffmann La Roche Ag Device for attaching cytological substance to microscope slide and for dyeing

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