JPS6346597B2 - - Google Patents

Info

Publication number
JPS6346597B2
JPS6346597B2 JP9081178A JP9081178A JPS6346597B2 JP S6346597 B2 JPS6346597 B2 JP S6346597B2 JP 9081178 A JP9081178 A JP 9081178A JP 9081178 A JP9081178 A JP 9081178A JP S6346597 B2 JPS6346597 B2 JP S6346597B2
Authority
JP
Japan
Prior art keywords
insulating layer
gold
layer
ceramic
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9081178A
Other languages
Japanese (ja)
Other versions
JPS5565499A (en
Inventor
Nobuo Kamehara
Seiichi Yamada
Koichi Niwa
Kyohei Murakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9081178A priority Critical patent/JPS5565499A/en
Publication of JPS5565499A publication Critical patent/JPS5565499A/en
Publication of JPS6346597B2 publication Critical patent/JPS6346597B2/ja
Granted legal-status Critical Current

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  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明は半導体集積回路装置等を実装するため
の多層回路基板に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer circuit board for mounting semiconductor integrated circuit devices and the like.

高速電子機器に用いられる半導体集積回路装置
を実装するための多層回路基板は誘電率が小さく
熱伝導率が大きな絶縁材料と電気低抗の小さな導
体材料とから構成され、かつ導体層へ配線パター
ンが寸法精度良く、高密度に形成できることが要
求されている。従来の多層回路基板は、高温で焼
成したセラミツク基板表面全面に導体ペーストと
絶縁ペーストとを交互にスクリーン印刷塗布し、
各層毎に焼成を行ない、バイヤホール、配線パタ
ーン等を形成する工程をくり返して積層形成する
方法により製造されている。
Multilayer circuit boards for mounting semiconductor integrated circuit devices used in high-speed electronic devices are composed of an insulating material with a low dielectric constant and high thermal conductivity and a conductive material with a low electric resistance, and a wiring pattern is formed on the conductor layer. It is required to have good dimensional accuracy and to be able to form at high density. Conventional multilayer circuit boards are made by screen-printing conductive paste and insulating paste alternately over the entire surface of a ceramic board fired at high temperatures.
It is manufactured by a lamination method in which each layer is fired and the steps of forming via holes, wiring patterns, etc. are repeated.

このような多層回路基板の導体材料としては、
導体抵抗が小さく、酸素雰囲気中での焼成が可能
な金が主として用いられ、絶縁材料としては誘電
率が低く、熱伝導率の高いガラス、結晶化ガラ
ス、ガラス・セラミツク等が用いられている。
Conductive materials for such multilayer circuit boards include:
Gold, which has a low conductor resistance and can be fired in an oxygen atmosphere, is mainly used, and as the insulating material, glass, crystallized glass, glass ceramic, etc., which have a low dielectric constant and high thermal conductivity, are used.

しかし、従来金導体層と、例えば誘電率が低
く、熱電導率の高いガラス・セラミツク等の絶縁
層とを印刷して積層焼成する際に、該金導体層表
面にふくれが発生する問題があつた。すなわち、
該ふくれは通常1Cm2当り10個程度発生し、導体
層と絶縁層との間の剥離および導体回路の断線の
要因となりまた、焼成回数が増し、多層化が進む
につれて発生しやすくなる傾向があり、従つて5
〜6層以上の従来の多層セラミツク回路基板は著
しく信頼性の低いものであつた。
However, when conventionally printing a gold conductor layer and an insulating layer such as glass or ceramic, which has a low dielectric constant and high thermal conductivity, and then laminating and firing them, there has been a problem that blistering occurs on the surface of the gold conductor layer. Ta. That is,
These blisters usually occur around 10 per 1cm2 , and can cause peeling between the conductor layer and insulating layer and breakage of the conductor circuit.They also tend to occur more easily as the number of firings increases and the number of layers increases. , therefore 5
Conventional multilayer ceramic circuit boards having six or more layers have extremely low reliability.

本発明は上述のふくれの発生を防止した信頼性
の高いセラミツク多層回路基板を提供するもの
で、絶縁基板面上に順次積層される導体層と絶縁
層との間に前記絶縁層とのぬれ性の良い金属薄膜
を介在させたことを特徴とするものである。
The present invention provides a highly reliable ceramic multilayer circuit board that prevents the occurrence of the above-mentioned blistering. It is characterized by the interposition of a thin metal film with good properties.

本発明は、ふくれの発生の原因がガラス、結晶
化ガラス、ガラス・セラミツク等の酸化物を主成
分とした誘電率が小さく、熱伝導率が大きな絶縁
層と金導体層との高温焼成時のぬれ性が悪く、金
導体層と絶縁層との接触角度が大きく、接触面積
が小さいためであると考え、金導体層よりも前記
絶縁層とのぬれ性の優れた金属薄膜を金導体層と
絶縁層との間に介在させたところ、ふくれの発生
が減少することを発見したことに基づくものであ
る。
The present invention discloses that the cause of blistering is the high temperature firing of an insulating layer, which is mainly composed of oxides such as glass, crystallized glass, glass/ceramic, etc., and has a low dielectric constant and high thermal conductivity, and a gold conductive layer. We believe that this is because the wettability is poor, the contact angle between the gold conductor layer and the insulating layer is large, and the contact area is small. Therefore, we used a metal thin film with better wettability with the insulating layer than the gold conductor layer with the gold conductor layer. This is based on the discovery that the occurrence of blisters is reduced when it is interposed between an insulating layer and an insulating layer.

本発明で、高温焼成時の金導体層と絶縁層のぬ
れ性の良否は、焼成後の金導体層と絶縁層との間
の付着力の良否に対応する。
In the present invention, the wettability between the gold conductor layer and the insulating layer during high-temperature firing corresponds to the quality of the adhesion between the gold conductor layer and the insulating layer after firing.

高温焼成により融点近傍に加熱された金が絶縁
層の表面に溶融状態に近い金の凝集力と、絶縁層
と金との間の付着力との大小に依存して、絶縁層
と金との付着力が、金の凝集力よりも大であれば
拡がり接触面積が大となり、焼成後付着性が良く
なり、絶縁層と金との付着力が、金の凝集力より
も小であれば拡がらず接触面積が小となり、焼成
後付着性が悪くなる。本発明で金導体層よりも、
絶縁層とのぬれ性の優れた金属薄膜を金導体層と
絶縁層との間に介在させることにより、高温焼成
時、絶縁層と金属薄層とのぬれ性が良く金属薄層
と絶縁層との接触角が小で、付着性が良好とな
る。又、金属薄層と金導体層とのぬれ性は良い。
The gold heated to near the melting point by high-temperature firing is applied to the surface of the insulating layer.The bond between the insulating layer and the gold depends on the cohesive force of the nearly molten gold and the adhesion between the insulating layer and the gold. If the adhesion force is greater than the cohesive force of gold, it will spread and the contact area will be large, resulting in good adhesion after firing. If the adhesion force between the insulating layer and gold is smaller than the cohesive force of gold, it will spread. The contact area becomes small, resulting in poor adhesion after firing. In the present invention, rather than the gold conductor layer,
By interposing a thin metal film with excellent wettability with the insulating layer between the gold conductor layer and the insulating layer, the insulating layer has good wettability with the thin metal layer during high-temperature firing. The contact angle is small, resulting in good adhesion. Further, the wettability between the thin metal layer and the gold conductor layer is good.

従つて、金属薄層を介在させた金導体層と絶縁
層との付着性は良好となる。金導体層と絶縁層と
の間に介在させる金属としては、絶縁層とのぬれ
性が優れかつセラミツク多層回路基板の導体層の
電気的特性及び絶縁層の電気的、熱的、機械的特
性に悪い影響を及ぼさないものでなければならな
い。このような金属としては、例えば、銅、ニツ
ケル、クロル等が望ましい。
Therefore, the adhesion between the gold conductor layer and the insulating layer with the metal thin layer interposed therebetween is good. The metal to be interposed between the gold conductor layer and the insulating layer should have excellent wettability with the insulating layer and be suitable for the electrical properties of the conductor layer of the ceramic multilayer circuit board and the electrical, thermal, and mechanical properties of the insulating layer. It must have no negative impact. Desirable examples of such metals include copper, nickel, and chloro.

本発明を次の実施例に基づき詳細に説明する。 The present invention will be explained in detail based on the following examples.

実施例 1 第1図は、本発明による多層回路基板の製造の
一部工程図を示すものである。
Example 1 FIG. 1 shows a partial process diagram for manufacturing a multilayer circuit board according to the present invention.

(a) 先ず、ベースとなる焼成されたセラミツク基
板1としては、誘電率が低く、熱伝導率の高い
材料が望ましく、また、導体および絶縁体の焼
成の際に安定で熱変形および機械的強度の低下
等を生じない材料であることが必要である。こ
のようなセラミツク材料として、アルミナ、ム
ライト、マグネシア等が用いられる。
(a) First, for the fired ceramic substrate 1 that will serve as the base, it is desirable to use a material with a low dielectric constant and high thermal conductivity, and also to be stable and resistant to thermal deformation and mechanical strength during firing of conductors and insulators. It is necessary to use a material that does not cause a decrease in the temperature. Alumina, mullite, magnesia, etc. are used as such ceramic materials.

ベースとなるセラミツク基板1に、ドリル又
はレーザ等により孔(バイア・ホール)2を形
成し、金導体層3を該孔に印刷法により埋込
む。(第1図a参照) (b) 次に、孔埋めされたベース・セラミツク基板
上の全面に金導体ペースト印刷し、900〜950℃
の酸素雰囲気中で焼成し金導体層3を形成した
後電解メツキ法により銅の薄い被膜4を金導体
層3表面に形成する。(第1図b参照) (c) 銅被膜4表面にレジストパターン5を形成
し、このレジスト5をマスクとして、ピロリン
酸系エツチング液により、前記銅被膜4をエツ
チングし、続いてヨウ素系エツチング液を用い
て、前記金導体層3をエツチングして、導体回
路を形成する。(第1図c参照) (d) 前記導体回路パターン表面に、ホウケイ酸ガ
ラス及びアルミナを主成分とするガラス・セラ
ミツク・ペーストを印刷塗布して焼成し絶縁層
6を形成する。(第1図d参照) このようにして形成されたセラミツク回路基板
の銅メツキ層の厚さとふくれの発生数及び電気抵
抗との関係を第2図に示す。
A hole (via hole) 2 is formed in a ceramic substrate 1 serving as a base by a drill or a laser, and a gold conductor layer 3 is filled into the hole by a printing method. (See Figure 1a) (b) Next, print gold conductor paste on the entire surface of the base ceramic substrate with the holes filled, and heat it at 900 to 950℃.
After firing in an oxygen atmosphere to form a gold conductor layer 3, a thin copper coating 4 is formed on the surface of the gold conductor layer 3 by electrolytic plating. (See Figure 1b) (c) A resist pattern 5 is formed on the surface of the copper film 4, and using this resist 5 as a mask, the copper film 4 is etched with a pyrophosphoric acid-based etching solution, and then an iodine-based etching solution is used. The gold conductor layer 3 is etched to form a conductor circuit. (See FIG. 1c) (d) A glass ceramic paste containing borosilicate glass and alumina as main components is printed and coated on the surface of the conductive circuit pattern and fired to form an insulating layer 6. (See FIG. 1d) FIG. 2 shows the relationship between the thickness of the copper plating layer of the ceramic circuit board thus formed, the number of blisters, and the electrical resistance.

第2図から明らかなように、ふくれの発生数は
銅被膜の厚さが0.05μm以上で著しく減少する傾
向があるが、一方銅被膜の厚さが厚くなるに従つ
て、電気低抗が増加する傾向にあるので、銅メツ
キ被膜の厚さは0.05〜2μmが望ましい。
As is clear from Figure 2, the number of blisters tends to decrease significantly when the thickness of the copper coating is 0.05 μm or more, but on the other hand, as the thickness of the copper coating increases, the electrical resistance increases. Therefore, the thickness of the copper plating film is preferably 0.05 to 2 μm.

尚、導体層及び絶縁層を積層して多層回路基板
を形成する場合には、下に絶縁層6にフオトリン
グラフイーを適用して孔(バイア・ホール)を形
成し、金導体層3を該孔に印刷法により埋込む工
程((a)′工程と呼ぶ)、続いて前記(b)及至(d)の工程
をくり返し行なう。
In addition, when forming a multilayer circuit board by laminating a conductor layer and an insulating layer, apply photolithography to the insulating layer 6 below to form a hole (via hole), and then layer the gold conductor layer 3. The step of filling the hole by a printing method (referred to as step (a)') is followed by repeating the steps (b) to (d).

実施例 2 実施例1と同様にして、ベース・セラミツク基
板1に孔(バイア・ホール)2を形成し、次いで
導体層3を印刷。焼成し、実施例1)における銅
メツキ被膜に代わりニツケルメツキ被膜を導体層
全面に被着し、フオトリソグラフイーを用いて導
体回路を形成し、絶縁ペーストを印刷。焼成し
て、絶縁層を形成しセラミツク回路基成を形成す
る。
Example 2 In the same manner as in Example 1, holes (via holes) 2 were formed in the base ceramic substrate 1, and then a conductor layer 3 was printed. After baking, a nickel plating film was applied over the entire conductor layer instead of the copper plating film in Example 1), a conductor circuit was formed using photolithography, and an insulating paste was printed. Firing forms an insulating layer and a ceramic circuit board.

このようにして形成されるセラミツク回路基板
のニツケルメツキ被膜の厚さとふくれの発生数及
び電気抵抗との関係を第3図に示す。
FIG. 3 shows the relationship between the thickness of the nickel plating film of the ceramic circuit board thus formed, the number of blisters, and the electrical resistance.

第2図及び第3図から明らかなように、本発明
によれば絶縁層の誘電率及び導体層の電気抵抗等
セラミツク回路基板の性能を低下させることな
く、ふくれの発生のない、信頼性の高い多層回路
基板が得られる。
As is clear from FIGS. 2 and 3, according to the present invention, the performance of the ceramic circuit board, such as the dielectric constant of the insulating layer and the electrical resistance of the conductive layer, can be maintained without degrading the performance of the ceramic circuit board. A high-quality multilayer circuit board can be obtained.

本発明は上記実施例に限らず、他の絶縁材料及
び導体材料から成る多層回路基板であつて、各絶
縁材料とぬれ性の優れた金属薄膜を介在させても
良い。
The present invention is not limited to the above-mentioned embodiments, but may be a multilayer circuit board made of other insulating materials and conductive materials, in which a metal thin film having excellent wettability with each insulating material is interposed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による回路基板の一部工程図、
第2図及び第3図は本発明によるセラミツク基板
のふくれの発生数及び電気抵抗の変化を示すもの
である。第2図及び第3図において、実線は金属
被膜の厚さに対するふくれの発生数の変化を、被
線は、金属薄膜の厚さに対する電気抵抗の変化を
表わす。 1…ベース・セラミツク基板、2…孔(バイ
ア・ホール)、3…導体層、4…金属薄膜、5…
絶縁層。
FIG. 1 is a partial process diagram of a circuit board according to the present invention;
FIGS. 2 and 3 show the number of blisters and changes in electrical resistance of the ceramic substrate according to the present invention. In FIGS. 2 and 3, the solid line represents the change in the number of blisters occurring with respect to the thickness of the metal film, and the covered line represents the change in electrical resistance with respect to the thickness of the metal thin film. DESCRIPTION OF SYMBOLS 1... Base ceramic substrate, 2... Hole (via hole), 3... Conductor layer, 4... Metal thin film, 5...
Insulating layer.

Claims (1)

【特許請求の範囲】[Claims] 1 セラミツク絶縁基板面上に順次積層、焼成さ
れる金導体層とガラス、結晶化ガラス、ガラス・
セラミツクから選択される絶縁層との間にふくれ
発生を減少させる銅、ニツケル、クロムから選択
される金属薄膜を介在させたことを特徴とする多
層回路基板。
1 Gold conductor layers, glass, crystallized glass, glass, etc. are sequentially laminated and fired on the surface of a ceramic insulating substrate.
A multilayer circuit board characterized in that a metal thin film selected from copper, nickel, and chromium is interposed between an insulating layer selected from ceramic and a metal thin film selected from copper, nickel, and chromium to reduce the occurrence of blistering.
JP9081178A 1978-07-25 1978-07-25 Multilayer circuit board Granted JPS5565499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9081178A JPS5565499A (en) 1978-07-25 1978-07-25 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9081178A JPS5565499A (en) 1978-07-25 1978-07-25 Multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS5565499A JPS5565499A (en) 1980-05-16
JPS6346597B2 true JPS6346597B2 (en) 1988-09-16

Family

ID=14008972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9081178A Granted JPS5565499A (en) 1978-07-25 1978-07-25 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS5565499A (en)

Also Published As

Publication number Publication date
JPS5565499A (en) 1980-05-16

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