JPS6346449B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key input identification circuit that operates a key input switch and outputs a corresponding signal. In particular, the present invention relates to improvements in circuits that prevent malfunctions caused by chattering or double pressing of key input switches.

Many configurations have been known for malfunction prevention circuits for key input switches. In general, improving the accuracy of malfunction prevention will increase the number of circuit elements.
It is expensive and large. On the other hand, a circuit with a small number of elements cannot sufficiently prevent malfunctions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new circuit that has a relatively simple configuration and uses inexpensive elements to prevent malfunctions with high precision.

In other words, in the conventional circuit, if the signal from the key input switch is taken in twice and the contents of the two times are compared to prevent malfunctions, the contents of the two times are memorized and stored separately. However, in the present invention, only the content captured at the first timing is stored, and the output signals are directly compared without storing the content captured at the second timing. It is characterized by having been. As a result, the circuit is functionally equivalent to the conventional circuit, and the number of circuit elements can be reduced to approximately half.

The present invention is characterized by a scanning circuit that provides a scanning signal to a key selection circuit having a plurality of key switches, an input detection circuit that detects the operation of a key switch and generates a detection signal, and a scanning circuit that detects the data corresponding to the operated key switch. a data latch circuit that latches in response to a signal; a means for prohibiting the input detection circuit from generating the detection signal after latching the data; and a scanning circuit that applies a scanning signal to the key selection circuit during the next scanning period. and a comparison circuit for comparing the data corresponding to the operated key switch obtained by the data latch circuit with the latch data of the data latch circuit.

The embodiment drawings will be explained in detail.

FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention. Reference numeral 1 denotes a key selection circuit in which a large number of push button type contact keys are arranged, and signals selected by pressing the keys are applied to an input detection circuit 2 and a data latch circuit 3. The output of the input detection circuit 2 is applied to the clock input of the data latch circuit and the input of the sequence circuit 4. The output of this sequence circuit 4 is applied to a clock terminal of a comparator circuit 5. Scanning circuit 6
is a circuit that supplies a scanning signal to the key selection circuit 1;
The synchronization signal is led to a data latch circuit 3 and a comparison circuit 5. In addition to this synchronization signal, the output of the data latch circuit 3 and the output of the key selection circuit 1 are coupled to the input of the comparison circuit 5.

FIG. 2 is a diagram showing the circuit of the embodiment in more detail. Circuit blocks 1-6 shown in broken lines in FIG. 2 correspond to those in FIG. That is, the input detection circuit 2 is composed of two NAND circuits. The data latch circuit 3 is composed of two D-type flip-flops, and the sequence circuit 4 is composed of two RS flip-flops and three NAND circuits (or seven NAND circuits). Comparison circuit 5 is composed of two exclusive OR circuits, five NAND circuits, and two inversion circuits. Further, the scanning circuit 6 is composed of three T-type flip-flops, three AND circuits, and one inverting circuit. As described above, the circuit of the present invention is characterized in that it can be realized using very general circuit elements and a small number of elements.

Next, the operation of this circuit will be explained with reference to the operation waveform diagrams shown in FIGS. 3 and 4. Figure 3 a~
g, and FIGS. 4c to 4o are waveform diagrams of points with corresponding symbols indicated by crosses in FIG. 1.

A clock input signal a is applied to the scanning circuit 6, and three T-type flip-flops 11, 12, 1
3, this clock input signal is frequency-divided, and the AND circuits 14, 15, 16 output signals e, f,
Obtain the synchronization signal waveform shown in g. This frequency-divided scanning signal and its inverted signal are applied to the key selection circuit 1.

Although only four key switches of the key selection circuit 1 are shown in FIG. 2, an example will be described in which the key switch _K1 to which the frequency-divided scanning signal c' is applied is operated. FIG. 4 is an explanatory diagram of this operation. The time axis in FIG. 4 is shortened to one half of that in FIG. 3 for convenience of drawing. c shown in FIG. 3 corresponds to c in FIG. 4, and c' is its inverted signal. Turn the key switch at A in Figure 4.
Assume that K ₁ has been operated.

The scanning signal is applied to the input detection circuit 2 via the key switch _K1 and further via the inversion circuit 17, and the pulse shown in FIG. 4h is obtained at its output.
As a result, the data corresponding to this key switch _K1 is latched in the D-type flip-flops 28 and 29 of the data latch circuit 3. At the same time, an RS flip-flop is set by NAND circuits 21 and 22, and NAND gate 23 is set by NAND gates 25 and 26 at the timing of signal g.
Set the RS flip-flop.

This completes data acquisition for one scanning period. When this scanning period ends, the output of the NAND circuit 26 is given to the NAND circuit 20, and even if there is any further input, it is prohibited from taking it in, and the contents of the data latch circuit 3 are held. Therefore, even if the NAND circuit 19 generates a signal based on the noise input after the data is latched, the latched data in the D-type flip-flops 28 and 29 will not change.

Here, the comparator circuit 5 operates at the timing shown in FIG.
Compare the contents latched to the If only one key input switch _K1 is pressed, and the key input switch K1 is pressed firmly, the output will continue to appear only in the inverting circuit 17, and this should match the latched content. As a result, a coincidence output m is sent out, and the latched data is used as output data.

At this time, the key input switch _K1 is pressed unreliably, and at the timing shown in FIG.
If the output from the comparator circuit 7 has already disappeared, the comparator circuit 5 will not output any output. At this time, it is determined that chattering has occurred, and the above operation is repeated as many times as necessary until the contents of the data latch circuit 3 and the current output of the key selection circuit 1 match. Even if the key input switch is pressed twice, the latched data and the current output of the key input switch do not match, so malfunctions can be similarly prevented.

As described above, according to the circuit of the present invention, 1
Just by latching the timing data of 2 times,
Since the operation of the key input switch can be compared over multiple timings, a highly accurate malfunction prevention circuit can be obtained. In the circuit of the present invention, there is no need to store data at the second timing, so the circuit required for this can be omitted, and the circuit is simplified. Furthermore, all the circuit elements necessary for the circuit of the present invention can be constructed from common and inexpensive integrated circuits, so the circuit has the advantage of being miniaturized and inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a circuit according to an embodiment of the present invention. FIG. 2 is a detailed configuration diagram of the same embodiment circuit. Figures 3 and 4
The figure is an operation waveform diagram of the same embodiment. 1...Key selection circuit, 2...Input detection circuit, 3
...Data latch circuit, 4...Sequence circuit,
5... Comparison circuit, 6... Scanning circuit.

Claims (1)

[Claims] 1. A key selection circuit having a plurality of key switches, a scanning circuit that provides a scanning signal to the key selection circuit, and an input detection circuit that detects that the key switch has been operated and generates a detection signal when the scanning signal that scans the key switch is generated. a data latch circuit that uses the detection signal to latch data determined by a combination of a signal from an operated key switch and a scanning signal; and means for prohibiting the input detection circuit from generating the detection signal after latching the data. and a comparison circuit that compares the data corresponding to the operated key switch obtained by the scanning circuit applying a scanning signal to the key selection circuit in the next scanning period and the latch data of the data latch circuit. A key input identification circuit characterized by: