JPS5858641A - Keyboard device - Google Patents

Abstract

PURPOSE:To simplify the constitution, by sending out a discriminating output to the second scanning means from the first scanning means, and holding a scanning output by the second scanning means, so that key input operating information in the keyboard part can be discriminated by the body part, when a key which has executed an input operation has been discriminated by the first scanning means. CONSTITUTION:When a clear signal CLEAR (b), which is a scanning synchronizing signal from a body part 1 side, becomes an L level from its previous H level, a clear state is released, and frequency dividing circuit 11 and a counting circuit 14 start to count a clock pulse (a). An output level of output terminals QD, QE of the frequency dividing circuit 11, and an output level of an output terminal Q0 of a decoding circuit 12 are in an L level during the first 8 piece portion after counting of the clock pulse (a) has been started. At the first point of time when the output terminal Q0 is in an L level, an 8 bit parallel data is loated to a parallel-series converting circuit 13 at the time of a level variation H L of the Q0 output of the frequency dividing circuit 11, therefore, only an input terminal A among input terminals A-H of the parallel-series converting circuit 13 becomes an L level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a keyboard device in which a keyboard portion and a main body portion into which key information from the keyboard portion is input are separated, in which a signal is transmitted between the keyboard portion and the main body portion. This relates to a device that allows Honroku to identify whether an input operation has been performed using the keys on the board by connecting the keys with lines.

As shown in FIG. 1, a keyboard device normally has a main body section 1 and a keyboard section 2 separated from each other at 5, with several signal lines 3 connecting them.

An example of the configuration of a conventional keyboard section is shown in a block diagram in FIG. In the figure, the keyboard unit connects a keyboard 5 in which keys 4 are arranged in a matrix (operation of the key 4 closes the gap between the two intersecting signal lines), an output latch 6 and an input latch. A total of 10 signal lines are connected between the keyboard section and the It is connected to a main body (not shown).

In this conventional method, although the hardware configuration is simple, there are as many as 10 signal lines, so it is easy to connect the wrong signal line, and the connectors for connecting the signal lines are special. Tie the line 1
Even if it were made into a book, the signal line would be quite thick, which caused a major obstacle when moving the keyboard.

Therefore, the conventional configuration shown in FIG. 3 is a configuration in which the number of signal lines is reduced and only one signal line is used to connect the main body and the keyboard. In the figure, the key 4 is a microprocessor (MPU), and the keyboard 5 arranged in an IJ rack is a microprocessor (MPU).
The configuration is such that the MPU 5 is connected to the input/output terminal of a, and the MPU 5 is operated by a clock signal from a clock generation circuit 10 using a crystal oscillator 9. With this configuration, MPU8
By matching the operation program of the main unit with the operation program of the main unit, it became possible to connect only one input/output signal line (SI/80). However, although the number of signal lines is small in this method, an operation program is required not only for the main body but also for the keyboard, making the operation program complicated. This method has drawbacks such as not only requiring a clock generating circuit 10 with a high frequency accuracy, but also requiring high frequency accuracy.

SUMMARY OF THE INVENTION An object of the present invention is to provide a keyboard device that eliminates the above-mentioned drawbacks of the prior art and can considerably reduce the number of signal lines connecting a main body and a keyboard by using simple hardware. .

In order to achieve the above object, the present invention provides a keyboard device in which a keyboard section and a main body section into which key information from the keyboard section is input are separated, in which the keyboard section is synchronized with an input clock signal. A first scanning means is provided in the main body to scan each key of the keyboard section to identify which key has been inputted; A second scanning means consisting of an output counter is provided, and first, a synchronizing signal for starting scanning is transmitted between the first scanning means and the second scanning means.
scanning means to start scanning by both scanning means at the same time, and when the key operated by the first scanning means is identified, the data is sent from the first scanning means to the second scanning means. The identification output is sent out, the scanning (count) output by the scanning means of M2 is held at that time, and the key λ key operation information on the keyboard section can be determined in the main body from the held output. be.

The present invention will be explained below with reference to the drawings. Fig. 4 is a block diagram showing one embodiment of the present invention. In the figure, the i-board section 2 includes a frequency divider circuit 11 that divides the clock signal (pulse) CLOCK input from the main body section 1, a frequency divider circuit 11 that divides the frequency of the clock signal (pulse) CLOCK inputted from the main body section 1, a frequency divider circuit 11 that divides the frequency of the clock signal (pulse) CLOCK input from the main body section 1, a frequency divider circuit 11 that divides the frequency of the clock signal (pulse) CLOCK, Zhou, 1/
The three frequency outputs Qn, Qi, and Qy divided by 64 are generated by three people A.
, B, c, a decoder circuit 12. A parallel-to-serial conversion circuit 13 that serially outputs 8-bit input data (A-H,) one bit at a time QH;
are the output lines of the decoder 12 and the input lines of the parallel-to-serial conversion circuit 13 in a matrix? It consists of a keyboard, C5, placed on the intersection. The frequency divider jlrll is a circuit that generates frequency division value outputs (Qa, QD, QE tQlF) as shown in Table 1 based on the clock pulse count value.

The decoder circuit 12 in Table 1 decodes the input values at input terminals A, B, and C, and outputs the values at output terminal Q as shown in Table 2.

This is a circuit that generates a decoded output whose output level is @L'' at only one terminal of Q7.

The parallel-to-serial conversion circuit 13 converts 5 pulses every 8 input clock pulses.
8-bit parallel data (
This circuit takes in the signals A to H) and outputs one bit in series from the QH terminal for each clock pulse. Also,
The keyboard interface circuit of the main body part 1 consists of two circuits: a counter circuit 14 that counts the input clock pulse CLOCK, and a latch circuit 15 that latches the output of the counter circuit 14 at that point in time based on the data signal DATA from the keyboard part 2. The operation when pressing the key 4 arranged at the intersection of the output terminal Qo of the decoder circuit 12 and the input terminal Qo of the parallel-to-serial converter circuit 13, which constitutes the scanning means, is as shown in FIG. This will be explained using a timing chart. First, the clear signal CLEAR (b) which is the scanning synchronization signal from the main body 1 side is
When the level changes from "level" to "L", the clear state is released and the frequency divider circuit 11 and counter circuit 14 start counting clock pulses (ml).The output levels of the output terminals QD and QB of the frequency divider circuit 11 are Figure 5 (C), (
d), so the clock pulse (Jl
) The output level of the output terminal Qo of the decoder circuit 12 is at the 1L" level for the first 8 minutes after the start of counting. Since the 8-bit parallel data is loaded into the parallel-to-serial converter circuit 13 triggered by the QO ratio output level change (H4L) of the frequency divider circuit 11, the input terminals A to H of the parallel-to-serial converter circuit 13 are When this state is output as serial data, the count value of the clock pulse (a) becomes 7 and 1, and the 'L' level becomes the scanning synchronization signal DATA (Fig. 5C). It is output from the Qo1 child of the parallel-to-serial conversion circuit 13 as . Therefore, in the main body 1, when the counter circuit 14 counts 7, that is, when the output terminal QA t QB of the counter circuit 14
*When the output levels (f), (2), and (h) of Qo (see FIG. 5) reach "H#,""H," and "H" levels, the latch circuit 15 is activated by the synchronizing signal DATA ( If latching is performed using FIG. It will be possible to earn money.

Another embodiment of the main body side of the present invention is shown in FIG.

In the figure, a counter circuit 14, a lip-flop circuit 16, and a gate circuit 17 constitute scanning means.

When the flip-flop circuit 16 receives the scanning synchronization signal DATA from the keyboard section, it changes the output level of the output terminal Q to the "H" level and the "L" level, and turns off the gate circuit 17. Therefore, the counter circuit 1
The clock signal inputted to 4 is limited to the period from the start of counting until the scanning synchronization signal DATA from the keyboard section is inputted. In this embodiment, the final count value (information representing the pressed position of the key) is sent to the address terminal (A) of the ROM circuit 18.

~As), and outputs the pressed position of the key from the data terminal (Dg-D7) as a code-converted keypad according to the contents stored in advance in the ROMK.

Further, by using the output signal CLOCK' of the 1 gate circuit 17 as the clock signal supplied to the keyboard section, it is possible to read out the human power of several keys by 1. The counting operation of the count circuit 14, which starts counting in response to the scan synchronization signal CLEAR from the main body side, is performed by the scan synchronization signal from the keyboard side. At the same time as the count is stopped by the DATA signal, a strobe signal is generated from the Q terminal of the flip-flop 16 to notify that a key has been input to a central processing unit (not shown) in the main body. The central processing unit reads the code of the key at this time and generates a count continuation signal for searching for the next key input. This count continuation signal is logically summed with the clear signal CLEAR by the OR circuit 19, and the logical sum output is input to the CLEAR terminal of the flip-flop circuit 16. That is,
The counting circuit 14, which started counting by the clear signal CIJAR, stops counting every time the data signal DATA is input, and when it continues counting by the counting continuation signal, the central processing unit starts counting the plurality of keys on the keyboard. You can know the key input.

FIG. 7 is a block diagram showing another embodiment of the keyboard section of the present invention. A frequency division circuit 11 that divides the clock signal CLOCK (pulse) input from the main body, a 1/2 frequency division from the frequency division circuit 11, a 14 division division,
A decoder circuit 12 that converts the three divided outputs QA and QB-Qa into three outputs A, B, and C divided by 14, and a decoder circuit 12 that divides the frequency by 1/16 from the frequency dividing circuit 11? "/32 frequency division"/6
Key scanning identification means consisting of a multiplexer 20 with 8 outputs and 1 output, which converts the 3 frequency division outputs QD, Ql, and QF into the 3 outputs A, B, and C as select signals, and the keys 4 are arranged in a matrix. The present embodiment is constructed from a keyboard 5 which is designed as follows.

Regarding the branch circuit 11 and the decoder circuit 12, the fourth
Since it has already been described when explaining the embodiment shown in the figure, the explanation will be omitted here.

i Lunaplexer 20 has select signal input terminals A and B.
, C selects one of the input data Do-D7 as shown in Table 3.

Clear signal CLEA which is a scanning synchronization signal from the main body side
When R reaches @L# level, the clear state is released and the dividing operation of the frequency divider circuit 11 starts @clock pulse CLO
Every time CK is input, the output of the decoder 12 is Qo=
Only one of the terminals of Q-pin becomes "L" level, and 8
It is designed to complete one cycle every clock pulse.

The multiplexer 2G in Table 3 has the following values for every 8 clock pulses:
Since the data input terminal no-D7 to be selected is switched and outputted to the output terminal Y, key scanning of the keyboard 5 is completed with 64 pulses.

As explained above, according to the present invention, in a sliding keyboard device in which the keyboard portion and the main body portion are separated, the number of signal twins connecting the keyboard portion and the main body portion is small, and when the keyboard portion is moved. It does not cause any interference, the hardware of the keyboard interface circuit is simple, the clock signal in the keyboard section and the clock signal in the main body are the same, and it is economical because there is no need for a special PTS signal for the keyboard. ,The key human power related software is simple and has other effects.

Further, it goes without saying that the advantages of the conventional embodiments shown in FIGS. 2 and 3 are directly incorporated into the present invention.

Note that in the above-described embodiments, explanations and illustrations of the ground line common to the power supply line and each signal line are omitted.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a keyboard device, FIG. 2 is a block diagram showing an example of the structure of a conventional keyboard section, FIG. 3 is a block diagram showing an example of the structure of another conventional keyboard section, and FIG. 4 is a block diagram showing an example of the structure of another conventional keyboard section. A block diagram showing one embodiment of the present invention, FIG. 5 is a timing chart of signals of each part to explain the operation of the embodiment of FIG. 4, and FIG. 6 is a block diagram showing another embodiment of the present invention. , FIG. 7 is a block diagram showing still another embodiment of the present invention. Code explanation 1... Body part, 2... Jin/Keyboard part, 3...
Song/signal line, 4...Key switch, 5...
... Keyboard, 11 ... Frequency division circuit, 12
... Decoder circuit, 13 ... Parallel-to-serial conversion circuit, 14 ... Counter circuit, 15 ...
・Latch circuit, 16...Flip-flop circuit, 17...Gate circuit, 20...Multiplexer agent Patent attorney Akio Namiki Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7

Claims (1)

[Scope of Claims] 1) A keyboard section and a first scanning means that scans each key of the keyboard section in synchronization with a key human input clock signal from the keyboard section and identifies which key has been inputted. and the main body section is provided with a second scanning means consisting of a counter that counts (scans) the clock signal and outputs the count value, and first, a synchronization signal for starting scanning is sent to the first scanning section. scanning means and second scanning means to simultaneously start scanning by both scanning hands RK, and when the key on which the input operation was performed in the first scanning means is identified, the first scanning means sends a signal to the second scanning means. The wrinkle identification output is sent to the scanning means of the second scanning means, and the scanning (count) output by the second scanning means at that time is held, so that the key manual operation information on the keyboard part can be determined in the main body part from the wrinkle holding output. A keyboard device characterized by: 2. The keyboard device according to claim 1, wherein the first scanning means includes a division circuit that divides the frequency of an input clock signal, and a decoder circuit that decodes the frequency-divided output from the frequency division circuit. and a multiplexer circuit that receives different decoded outputs from the decoder circuit to the data input terminal with different tie configurations depending on which key is input operated, and the second scanning means 1. A keyboard device comprising: a counter for counting clock signals; and means for holding a count value in the counter when an output signal from the multiplexer circuit arrives.