JPS634621A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS634621A JPS634621A JP14893086A JP14893086A JPS634621A JP S634621 A JPS634621 A JP S634621A JP 14893086 A JP14893086 A JP 14893086A JP 14893086 A JP14893086 A JP 14893086A JP S634621 A JPS634621 A JP S634621A
- Authority
- JP
- Japan
- Prior art keywords
- damaged layer
- gaas substrate
- mask pattern
- hole
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000002253 acid Substances 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000007800 oxidant agent Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特にバイア
ホールを有するGaAs(砒化ガリウム)集積回路の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a GaAs (gallium arsenide) integrated circuit having via holes.
第2図(a) 〜(c)はGaAs集積回路における従
来のバイアホール形成の主要工程を示す断面1図で、こ
れらの図において、1はGaAs基板、2はガラス板、
3はマスクパターン、4は/くイアホールをそれぞれ表
している。FIGS. 2(a) to 2(c) are cross-sectional views showing the main steps of conventional via hole formation in GaAs integrated circuits. In these figures, 1 is a GaAs substrate, 2 is a glass plate,
3 represents a mask pattern, and 4 represents an ear hole.
第2図(a)はGaAs基板1をガラス板2にワックス
を使ってはり付けた状態である。この状態の後、写真製
版等によってマスクツくターン3を形成しく第2図(b
)’)、続いて、酸と酸化剤との混合液をエッチャント
した湿式エツチングによりバイアホール4を形成する(
第2図(C))。FIG. 2(a) shows a GaAs substrate 1 bonded to a glass plate 2 using wax. After this state, mask-cut turns 3 are formed by photolithography, etc., as shown in Figure 2 (b).
)') Then, via hole 4 is formed by wet etching using a mixed solution of acid and oxidizing agent (
Figure 2 (C)).
第2図(C)に示したGaAs基板1の湿式エツチング
は、エッチャント中の酸化剤(過酸化水素1等)がGa
Asを酸化し、上記酸化反応による生成物を酸(硫酸、
酒石酸等)が溶解させることにより進行する。またガラ
ス板2へのGaAs基板1のはり付けは、前記湿式エツ
チングの工程において、GaAs基板1のマスクパター
ン3のない側の面が前記エッチャントによってエッチン
グされるのを防止する効果を有する。In the wet etching of the GaAs substrate 1 shown in FIG. 2(C), the oxidizing agent (hydrogen peroxide, etc.) in the etchant is
As is oxidized and the product of the above oxidation reaction is treated with an acid (sulfuric acid,
The process progresses by dissolving tartaric acid, etc.). Furthermore, gluing the GaAs substrate 1 to the glass plate 2 has the effect of preventing the surface of the GaAs substrate 1 on the side where the mask pattern 3 is not provided from being etched by the etchant in the wet etching process.
従来の半導体装置の製造方法において、酸と酸化剤との
混合液をエッチャントとした湿式エツチングによりバイ
アホール4の形成を行うと、サイドエツチングが大きく
、はぼ等方的にエツチングが進むため、バイアホール4
の仕上り幅は深さの約2倍程度にも広がる。したがって
、GaAs基板1を貫通するためには、設計上基板厚の
約2倍程度のバイアホールの仕上り幅を見込まなければ
ならない。In the conventional semiconductor device manufacturing method, when the via hole 4 is formed by wet etching using a mixed solution of acid and oxidizing agent as an etchant, the side etching is large and the etching progresses almost isotropically. Hall 4
The finished width is approximately twice as wide as the depth. Therefore, in order to penetrate the GaAs substrate 1, the finished width of the via hole must be designed to be approximately twice the thickness of the substrate.
第3図(a)、(b)は従来の製造方法における問題点
の一例を示した断面図で、これらの図で、第2図(a)
〜(C)と同一符号はそれぞれ同一部分を表している。Figures 3(a) and 3(b) are cross-sectional views showing an example of problems in the conventional manufacturing method.
The same reference numerals as those in (C) represent the same parts.
上述のような湿式エツチングは、−段に乾式プロセスに
比べ制御性が悪いため、特にバイアホールエツチングの
ようなディープエツチングでは、エツチング量の基板面
内でのばらつきが生じ易い、エツチング量が基板面内で
ばらつくと、第3図(a)のように貫通している穴と未
貫通の穴ができる。未貫通の穴を貫通させるべく追加エ
ツチングを行うと、第3図(a)の状態で貫通していた
穴の仕上り幅はさらに広がり、したがって、バイアホー
ル4の仕上り幅は基板面内でばらついてしまう(第3図
(b))。Wet etching as described above has poor controllability compared to dry etching, so in deep etching such as via hole etching, the amount of etching tends to vary within the substrate surface. If there is variation within the hole, there will be holes that are through and holes that are not through, as shown in Figure 3(a). When additional etching is performed to penetrate the unpierced holes, the finished width of the holes that were penetrated in the state shown in FIG. (Fig. 3(b)).
以上のように、従来の半導体装置の製造方法によると、
バイアホール4の仕上り幅が大きくなり1回路パターン
の微細化の障害となるばかりか、仕上り幅がGaAs基
板1面内でばらつくという問題点があった。As described above, according to the conventional semiconductor device manufacturing method,
There was a problem in that the finished width of the via hole 4 became large, which not only became an obstacle to miniaturization of one circuit pattern, but also that the finished width varied within one surface of the GaAs substrate.
この発明は、上記のような問題点を解決するためになさ
れたもので、バイアホールの仕上り幅を小さく押え、・
かつバイアホールの仕上り幅のGaAs基板面内でのば
らつきを防止することを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to reduce the finished width of the via hole,
Another purpose is to prevent variations in the finished width of the via hole within the surface of the GaAs substrate.
この発明に係る半導体装置の製造方法は、GaAs基板
の面上に形成されたマスクパターンの開口部を通して、
あるいは収束性イオンビーム(FIB)によってGaA
s基板面上のバイアホールを形成する部分に、比較的質
量数の大なるイオンを高エネルギーで選択的に注入し、
イオン注入によるダメージ層を酸でエツチングするよう
にしたものである。A method for manufacturing a semiconductor device according to the present invention includes: passing through an opening of a mask pattern formed on a surface of a GaAs substrate;
Alternatively, GaA using focused ion beam (FIB)
s selectively implanting ions with a relatively large mass number at high energy into the portion where the via hole is to be formed on the substrate surface,
The layer damaged by ion implantation is etched with acid.
この発刷においては、GaAs基板面上のバイアホール
を高エネルギーで選択注入し、イオン注入部分にダメー
ジを与えてアモルファス層(ダメージ層)とすることか
ら酸のみでエツチングが可能となる。In this printing, via holes on the surface of the GaAs substrate are selectively implanted with high energy to damage the ion-implanted area and form an amorphous layer (damaged layer), making etching possible with only acid.
第1図(a)〜(e)はこの発明の一実施例による半導
体装置の製造方法における主要製造工程を示す断面図で
、これらの図において、1はGaAs基板、1aはイオ
ン注入によるダメージ層、3はマスクパターンを示し、
矢印は注入するイオンの入射方向を表している。FIGS. 1(a) to 1(e) are cross-sectional views showing the main manufacturing steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention. In these figures, 1 is a GaAs substrate, and 1a is a damaged layer caused by ion implantation. , 3 indicates the mask pattern,
The arrow represents the direction of incidence of ions to be implanted.
次に製造工程について説明する。Next, the manufacturing process will be explained.
第1図(a)に示すように、GaAs基板1の面上に密
度の大きい、つまりイオン阻止能の高い金属(例えばA
u、Pt、W等)のマスクパターン3を形成した後、第
1図(b)に示すように、マスクパターン3の開口部を
通して、GaAs基板1面上の所望する部分(バイアホ
ールを形成する部分)に比較的質量数の大なるイオン(
例えばA r 、 X e等)を高エネルギーで選択的
に注入し、イオン注入によるダメージ層1aを形成する
0次に、第1図(C)に示すように、GaAs基板1の
ダメージ層1aのみを、酸によって選択的にエツチング
する。以下、第1図(b)のようなイオン注入工程およ
び第1図(C)のようなエツチング工程を交互に繰り返
して行い、第1図(d)および第1図(e)に示す最終
イオン注入工程、最終エツチング工程を経て、基板貫通
部分(バイアホール4)を得る。As shown in FIG. 1(a), a metal with a high density, that is, a high ion-stopping ability (for example, Al
After forming a mask pattern 3 of (U, Pt, W, etc.), as shown in FIG. ion) with a relatively large mass number (
For example, Ar, Xe, etc.) are selectively implanted at high energy to form a damaged layer 1a by ion implantation. Next, as shown in FIG. 1(C), only the damaged layer 1a of the GaAs substrate 1 is implanted. is selectively etched with acid. Thereafter, the ion implantation process as shown in FIG. 1(b) and the etching process as shown in FIG. 1(C) are repeated alternately to form the final ion implantation process shown in FIG. Through an implantation process and a final etching process, a substrate penetrating portion (via hole 4) is obtained.
以上のような工程で半導体装置の製造を行うと、イオン
注入によってGaAs基板1のダメージ層1aの深さお
よび幅広がりを適当に制御しながら(特i幅広がりは小
さく押えながら)、ダメージ層1aのみを選択的にエツ
チングできる。加えて、従来法に示したような、GaA
s基板1裏面の保護を目的としたガラス板2へのはり付
は工程(第2図(b))は当然不要となる。When a semiconductor device is manufactured through the steps described above, the depth and width of the damaged layer 1a of the GaAs substrate 1 are appropriately controlled by ion implantation (especially while keeping the width expansion small). It is possible to selectively etch only. In addition, as shown in the conventional method, GaA
Of course, the process of gluing the glass plate 2 to the glass plate 2 for the purpose of protecting the back surface of the s-substrate 1 (FIG. 2(b)) is unnecessary.
なお、上記実施例では、GaAs基板1上へのイオンの
選択注入はマスクパターン3の開ロ部ヲ通して行ったが
、収束性イオンビーム(F I B)を用いたマスクレ
ス注入でもよい。In the above embodiment, ions were selectively implanted into the GaAs substrate 1 through the opening of the mask pattern 3, but maskless implantation using a focused ion beam (FIB) may also be used.
この発明は以上説明したとおり、マスクパターンの開口
部を通してまたは収束性イオンビームによってGaAs
基板面上のバイアホールを形成する部分にイオンを高エ
ネルギーで選択的に注入してダメージ層を形成する工程
と、このダメージ層をエツチング除去する工程とを繰り
返して行うようにしたもので、サイドエツチングを押え
ることができ、かつエツチング量の制御も容易となるた
め、バイアホールの仕上り幅と仕上り幅のばらつきを小
さく押えることができるという効果がある。As explained above, this invention enables GaAs to be produced through the openings of a mask pattern or by a focused ion beam.
This process involves repeating the process of selectively implanting ions with high energy into the area on the substrate surface where the via hole is to be formed to form a damaged layer, and the process of removing this damaged layer by etching. Since etching can be suppressed and the amount of etching can be easily controlled, the finished width of the via hole and the variation in the finished width can be kept small.
第1図(a)〜(e)はこの発明の半導体装置の製造方
法の一実施例の主要工程を示す断面図、第2図(a)〜
(C)は従来の製造方法の主要工程を示す断面図、第3
図(a)、(b)は従来の製造方法における問題点を説
明するための断面図である。
図において、1はGaAs基板、1aはイオン注入によ
るダメージ層、3はマスクパターンである。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 (ほか2名)第1図
第2図1(a)-(e) are cross-sectional views showing the main steps of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2(a)-(e)
(C) is a cross-sectional view showing the main steps of the conventional manufacturing method;
Figures (a) and (b) are cross-sectional views for explaining problems in the conventional manufacturing method. In the figure, 1 is a GaAs substrate, 1a is a damaged layer due to ion implantation, and 3 is a mask pattern. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (and 2 others) Figure 1 Figure 2
Claims (1)
砒化ガリウム基板面上に形成されたマスクパターンの開
口部を通して、または収束性イオンビームによって前記
バイアホールを形成する部分に比較的質量数の大なるイ
オンを高エネルギーで注入してダメージ層を形成する工
程と、前記イオン注入によるダメージ層を酸で選択的に
エッチングする工程とを繰り返して行うことによって、
前記砒化ガリウム基板にバイアホールを形成する工程を
含むことを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device having a via hole,
A damaged layer is formed by implanting ions with a relatively large mass number at high energy through the opening of a mask pattern formed on the surface of the gallium arsenide substrate or by using a focused ion beam into the portion where the via hole is to be formed. By repeating the step and the step of selectively etching the damaged layer caused by the ion implantation with acid,
A method for manufacturing a semiconductor device, comprising the step of forming a via hole in the gallium arsenide substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14893086A JPS634621A (en) | 1986-06-24 | 1986-06-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14893086A JPS634621A (en) | 1986-06-24 | 1986-06-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS634621A true JPS634621A (en) | 1988-01-09 |
Family
ID=15463840
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14893086A Pending JPS634621A (en) | 1986-06-24 | 1986-06-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS634621A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7199055B2 (en) * | 2003-03-03 | 2007-04-03 | Cypress Semiconductor Corp. | Magnetic memory cell junction and method for forming a magnetic memory cell junction |
-
1986
- 1986-06-24 JP JP14893086A patent/JPS634621A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7199055B2 (en) * | 2003-03-03 | 2007-04-03 | Cypress Semiconductor Corp. | Magnetic memory cell junction and method for forming a magnetic memory cell junction |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH10260523A (en) | Production of silicon stencil mask | |
JPS60128622A (en) | Etching method | |
US5556797A (en) | Method of fabricating a self-aligned double recess gate profile | |
US4863556A (en) | Method for transferring superfine photoresist structures | |
JPS63299144A (en) | Method of separating interface sealed by oxide protective layer for pad | |
JPS634621A (en) | Manufacture of semiconductor device | |
US4411929A (en) | Method for manufacturing semiconductor device | |
JPH08335543A (en) | Formation of alignment pattern | |
JPH0654778B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2586431B2 (en) | Method for manufacturing semiconductor device | |
JP3010650B2 (en) | Method for manufacturing semiconductor device | |
KR100187676B1 (en) | Method of forming field oxide film in a semiconductor device | |
KR960014453B1 (en) | Manufacturing method for field oxide film | |
JPS61114536A (en) | Manufacture of semiconductor device | |
KR0125312B1 (en) | Field oxidation method of semiconductor device | |
JPH118222A (en) | Method of processing silicon substrate | |
JPS60240131A (en) | Manufacture of semiconductor device | |
KR100223282B1 (en) | Semiconductor field oxidation film manufacturing method | |
JPH0582502A (en) | Etching method for insulating film | |
JP2863216B2 (en) | Method for manufacturing semiconductor device | |
KR100232212B1 (en) | Method of manufacturing semiconductor device | |
JPH0461123A (en) | Method of semiconductor isolation | |
JPH06275576A (en) | Manufacture of semiconductor device | |
JPS61107747A (en) | Manufacture of semiconductor device | |
JPS60130173A (en) | Manufacture of semiconductor device |