JPS6345909A - Attenuator for digital audio signal - Google Patents

Abstract

PURPOSE:To contrive to reduce the cost and to save the space by using a multiplication circuit in common use with a multiplication circuit of a digital filter and multiplying an input digital audio signal fed to the multiplication circuit with a coefficient signal from an up-down counter. CONSTITUTION:A coefficient signal 2a (coefficient K=1, 2, 3...) corresponding to a mute signal is outputted from an output terminal of an up-down counter 2 and fed to a multiplier circuit 3, which is used in common for a multiplier circuit of a digital filter and receives an input digital audio signal 8 (data) via an input terminal T2. The data Din and the coefficient signal K are multiplied by the multiplier circuit 3 as Dout=KXDin and the result is fed to a contact (b) of the switching means 5. A contact (c) is connected to an input terminal T2 receiving the data Din, and a common contact (a) is connected to an output terminal T20 giving an output data Dout. The output terminal is connected to a digital-analog conversion circuit for a CD player or the like.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to CD (compact disc) players and DA
The present invention relates to a digital audio signal attenuation device suitable for use in a magnetic recording/reproducing device for T (digital audio tape), etc.

[Summary of the invention]

The present invention provides a digital audio signal attenuation device suitable for application to a CD player, etc., which includes a multiplication circuit and an up/down counter for generating coefficient signals in which the coefficients are gradually increased or decreased. doubles as the multiplication circuit of the digital filter, and in this multiplication circuit, the digital audio signal input to it is multiplied by the coefficient signal from the up/down counter to gradually decrease or increase the signal, and when the signal is interrupted, playback starts. This is to prevent clicks that occur at the time of switching or switching.

[Conventional technology]

During playback of continuous analog audio signals such as music,
When the signal is interrupted, the time t1 when the reproduction signal (1) is paused or stopped, as shown in FIG. 5A.
Then, at time t2 when the pause or stop is released and the reproduction signal (1) is reproduced again, that is, when the reproduction signal level is thick at the falling edge and the rising edge, a click sound is generated. Furthermore, a click sound is also generated at the time of signal switching, that is, at the moment when the first reproduction signal (la) is switched to the second reproduction signal (1b) at time t3 as shown in FIG. 5B. Fade in to prevent licks from occurring like this.

By performing a fade-out, the playback signal is gradually reduced.

It is well known that titration is used.

[Problem that the invention seeks to solve]

As described above, when an analog signal is to be faded in or out, it is possible to do so relatively easily using a variable resistor or the like.

However, it is necessary to attenuate the clicks that occur due to interruptions and switching in the signal at the digital stage before it is input to the digital-to-analog converter circuit of CD players, DAT magnetic recording and reproducing devices, etc., which have recently begun to be widely used. had the disadvantage of requiring many parts.

The present invention has been made in view of the above drawbacks, and the present invention replaces the large-scale multiplication circuit used in digital filters in CD players and the like with a multiplication circuit that gradually decreases or increases gradually when the digital signal is interrupted. , which aims to reduce costs and save space.

[Means for solving problems]

The digital audio signal attenuation device of the present invention, as shown in the principle diagram of FIG. The multiplication circuit (3) is also used as the multiplication circuit of the digital filter, and the input digital audio signal (8) is applied to the multiplication circuit (3).
) and the coefficient signal (2a
).

[Effect]

The digital audio signal attenuation device of the present invention shares the multiplication circuit (3) of the digital filter, multiplies the input digital audio signal (8) and the coefficient signal (2a) from the up/down counter (2), and outputs the result. Now it is possible to fade in or out the click sound when the digital signal is interrupted or switched.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. FIG. 1 is a system diagram of the digital audio signal attenuation device of the present invention, and FIG. 2 is a waveform explanatory diagram.

In FIG. 1, (2) is an up/down counter circuit for generating coefficient signals, and a soft mute signal (6) for soft muting is applied to one input terminal T14 of the up/down counter circuit. This soft mute signal (6) causes the counter circuit to count up when it is "off" and to count down when it is "on".

Furthermore, another input terminal is a clock terminal CK, but the muting time can be externally controlled by passing the clock signal through an OR gate circuit OR without directly applying the clock signal. That is, the count clock signal (46) from the timing oscillation circuit (see FIG. 4 (22)) is applied to one input terminal T24 of the OR gate circuit OR, and the count clock signal (46) is applied to one input terminal T24 of the OR gate circuit OR.
A hold signal (7) is added to 15 so that muting time can be changed and fader control with gradual changes can be performed, and the clock signal obtained by changing the count clock (46) to an appropriate period is an up/down counter (2). is applied to the clock terminal CK of. Up/down counter (2)
A coefficient signal (2) corresponding to the mute signal is output from the output terminal of
a) (Coefficient = 1.2.3...) is output and added to the multiplication circuit (3).

This multiplier circuit (3) also serves as a multiplier circuit for a digital filter, and an input digital audio signal (8) (hereinafter referred to as data) is input to it via an input terminal T2, and this data Din and a coefficient signal Dout=KX
It is multiplied by the multiplier circuit (3) like Din and applied to the contact point of the switching means (5). Contact C is data Di
is connected to the input terminal T2 to which n is applied, and the common contact a
is connected to the output terminal T20 from which the output data Dout is output. This output terminal is connected to a digital-to-analog conversion circuit (not shown) of a CD player or the like.

The movable contact piece of the switching means (5) is controlled via the control circuit (4) when the muting in the up/down counter (2) is "off", and the movable contact piece is moved to the C side to read the data Di.
n is directly applied to the output terminal T20. This prevents the data Din from being requantized.

According to such a digital audio signal attenuation device, as shown in FIG. ), or it does not reach zero immediately at the stop time t1 and is multiplied by the multiplier circuit (3) like Dout = KXDin (K = 1.2.3...) according to the data Din until it reaches tl-1. It gradually attenuates and reaches the zero level, and at t2
'('Even when the pause is released, the playback waveform (1) does not reach the predetermined level immediately, but gradually increases according to the data Din and reaches the predetermined level within the period from t2 to t2-1. Become.

The first and second reproduction signals (la) shown in FIG. 2B.

(1b) also, from the switching time t3 to t3-1
, the data Din which is the first reproduction signal (1a)
are multiplied by coefficient signals K that sequentially decrease and are gradually attenuated, and at time t3-1, data Din, which is the second reproduced signal (1b), is multiplied by coefficient signals K that sequentially increase and are gradually summed. , and the second reproduction signal is switched to L3-2, so that Dout with smooth movement is obtained.

The up/down counter (2) mentioned above has a count output of 1.
Or, when it reaches zero, the counting operation is stopped, so when stopping a CD player etc. as shown in Figure 2A, the coefficient signal is 1, and when it is interrupted (pausing or muting), it is 1. →0, and when muting is canceled, it becomes 0→1, and as shown in FIG. 2B, when switching, it becomes 1→0→1.

The multiplication circuit of the above-mentioned digital audio signal attenuation device utilizes the multiplication circuit arranged in the integrated circuit for the oversampling filter, so the oversampling filter characteristics and the oversampling filter are explained using FIGS. 3 and 4. A system diagram of the integrated circuits (ICs) that constitute the device will be explained.

In a CD player, when stereo left and right channel signals are sampled at a sampling frequency fs -44, 1 kHz, as shown in FIG. 3A, in addition to the original signal (10), fs.

Fundamental wave centered around 2fs, 3fs, 4fs...and odd and even harmonics (11), (12)
.

(13), (14)... occur. These harmonics (11), (12), (13)
To filter , (14), use Figure 3B.
As shown in the figure, the odd-order harmonics of the fundamental wave (44, 1 kHz) (11) and the third harmonic (44, 1 kHz x 3) (13) are eliminated by the 83rd-order first oversampling filter, and this A 21st-order second oversampling filter connected to the first oversampling filter as a cassgate eliminates even-order harmonics of the second-order AM wave (44, 1kHz x 2) (12) as shown in Figure 2C. . This is the fourth harmonic (
44,1kHz x 4) (14) is eliminated by the frequency characteristics of the analog low-pass filter shown by the broken line (15) in the third diagram, which is added after digital-to-analog conversion, so it is not removed here. .

That is, the fundamental wave and the second and third harmonics are attenuated or eliminated by the first and second oversampling filters, as shown in the third diagram.

Such a digital filter IC is shown in (16) in FIG. T1 to T23 indicate input/output terminals of the IC, and the input circuit (17) receives data from the input terminal T2.
(81 is inputted serially and applied to one input terminal of the exclusive OR gate circuit EOR, the phase inversion control signal (18) is applied to the input terminal T1, and the other input terminal of the exclusive OR gate circuit EOR Exclusive OR gate circuit EOR
The reversibility of the output can be changed such that if the phase inversion control signal (18) is at "H" level, it is inverted, and if it is at "L" level, it is not inverted. Output terminal T2 of digital filter IC (16)
0 (hereinafter referred to as D/
A) has voltage output type and power output type.
If a current output type D/A is used in a system where the data Din is stopped in phase using a voltage output type D/A, the output will be in reverse phase, and vice versa, so D/A selection is required. However, by adding this input terminal T1, there are no restrictions on A/D selection. In CD players, etc., if all bits are O or l, I2's complement J (2's comp
By using the property that the polarity of the data is inverted when all bits are inverted, the polarity of the audio output can be easily changed using the phase inversion control signal. It is designed to be switchable.

The serial data from the exclusive OR gate circuit FOR is sent to the error correction circuit (21) as parallel data through the serial-parallel conversion circuit SP.

Note that the input terminal T3. of the input circuit (17). A bit clock (19) and a left/right signal discrimination clock (2o) in the human-powered digital audio signal are added to T4. This left/right signal discrimination clock (2o) is a timing oscillation circuit (2o).
2) has also been added.

The error flag (23) is given from the input terminal T of the error correction circuit II (2], ), and the data (8) undergoes error correction, but is actually multiplied by the multiplication circuit/accumulator (3). Various error corrections are performed. The first switching means (25) has contacts a and b.

C is shown, but it is a memo IJ (R
AM) (24>. This data RAM (
24) has a data RAM (24a) for the 83rd order and a data RAM (24b) for the 21st order.
The M output is applied to the multiplication circuit (3) described in FIG.

This multiplication circuit (3) includes an accumulator, and has a coefficient R
Coefficient K1. from OM(26). The two columns are input to the accumulator of the multiplier circuit (3) via one switching path ba of the second switching means (27).

The coefficient ROM (26) also includes coefficients I ROM (2fia) and (26b) for the 83rd order and the 21st order.

The coefficient ROM (26) stores two types of coefficients K1. Coefficient switching signals (2B) are used to switch between these coefficients.

(29) is applied to the terminals TIG and TIT as necessary to switch the coefficients stored in the coefficient ROM (26). The multiplier circuit/accumulator (3) has input terminals T1s and Tls, an offset signal (30) is input to the input terminal T1g, and a zero level ±1% offset signal (30) is input to the input terminal 1-19. 31
) is added.

The output of the multiplication circuit/accumulator (3) is applied as a parallel output to an overload limiter circuit (32), overshoot is suppressed, and the output is applied to an output circuit (33).

The output of the overload limiter circuit (32) is the line (
34) through the other switching path C of the first switching means.
−+ a to the data RAM.

A mute signal (3) is connected to the input terminal T6 of the output circuit (33).
5), the input terminal T7 receives the serial/parallel data switching signal (36), the input terminal T8 receives the format switching signal (37), and the input terminal Ts receives the 16-bit/18-bit switching signal (38). It is designed so that each can be added.

In addition, the output terminal T20 of the output circuit (33) has D1 to D+.
The data shown in 6 and the bit clock and word clock (
39), the left and right (1-, R) clocks (40) are output to the output terminal T21, the left aperture clock (41) to the output terminal T22, and the right aperture clock (42) to the output terminal T23. Ru.

Here, the left and right aperture clocks (41) (42)
is a clock for controlling the signal sampling and holding circuit, and the word clock is twice the frequency of the LR clock.

The input terminal TIO of the timing oscillation circuit (22) is input/output when the power is turned on, and the initialization signal (42) for phase alignment of the LR clock is input, and the crystal input signal (45) is input to the input terminal T13. The system clock (43) is connected to the output terminal Tit, and the crystal output signal (43) is connected to the output terminal T12.
4) can be taken out.

Furthermore, the up-down counter circuit (2) mentioned in FIG. A soft mute signal (6) is applied to the up/down counter (2) from the input terminal T14, and a hold signal (7) from the input terminal T15 is applied to one side of the OR gate circuit OR. Further, a count clock (46) from a timing generation circuit (22) is applied to the other input of the OR gate circuit OR.

The output of the OR gate circuit OR is an up/down counter (2
) is applied to the clock terminal CK.

In the above configuration, when performing the function as a digital filter, the first and second switching means (25)
, (27) is in contact with one switching path a-b side, and data (8) is transmitted using the multiplier circuit/accumulator (3).
ζ Error correction is performed in the previous process, and the data RAM
In order to perform 83rd-order filtering on the data stored in (24), the output of the 83rd-order RAM (24a) is added to the multiplier circuit (3), and this data is multiplied by one column of coefficients for the 83rd order of the coefficient ROM. Teri.

One multiplication is performed for each R data signal, 22 times for a total of 44 times. As a result, filtering as shown in FIG. 3B is performed.

The result of such multiplication is sent to data RA through the line (34) and another switching path c-a of the first switch means (25).
In addition to M(24), the output of the 21st-order RAM (24a) is added to the multiplication circuit/accumulator +3) and multiplied again with the coefficient string stored in the 21st-order coefficient ROM. This multiplication is performed 22 times for each R data signal, a total of 4
This is repeated four times, filtering as shown in FIG. 3C is performed, and data having characteristics as shown in FIG. 3 is obtained at the output of the output circuit (33). The multiplication circuit/accumulator (3) described above is 22μ, which is one cycle of CD data.
96 multiplications are possible during S, 96-88=8
You can afford to do multiple multiplications.

When performing the soft muting operation of the present invention,
It is only necessary to multiply the data of H twice, once each, and the second switching means (27) is connected to the other switching path C-a.
The soft mute signal (6) applied to the up/down counter (2) switches between up and down counting, and the count down or count up corresponds to the coefficient signal (2a) which gradually decreases or increases according to the clock signal. Outputs the count value. Such a coefficient signal (2a) is multiplied by the R data, and the second
As shown in Figures A and B, fade-in or fade-out is performed according to the data of R, and the output terminal T is passed through the overload limit circuit (32) and output circuit (33).
Data is outputted to 20, converted into analog by a D/A (not shown), and a fourth-order frequency spectrum component shown in the third diagram is removed by a low-pass filter provided in the analog stage.

In this way, in the present invention, the multiplication circuit/accumulator for filtering or error correction can be used for fade-in or fade-out during muting, so that the multiplication circuit can be shared at the same time as eliminating clicks during muting, thereby saving space. This greatly reduces the cost and eliminates the need for requantization, since the soft mutating off input data can be easily bypassed without being multiplied by a coefficient.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made without departing from the gist of the present invention.

〔Effect of the invention〕

Since the present invention is configured as described above, it is possible to prevent click sounds generated at the time of signal interruption, reproduction start, or switching in the digital data path in digital audio equipment. Moreover, since the multiplication circuit used in the digital filter IC can be used, the space can be saved and the cost can be greatly reduced, and requantization can be prevented when soft muting is turned off.

[Brief explanation of drawings]

FIG. 1 is a system diagram of the digital audio signal attenuation device of the present invention, FIG. 2 is an audio signal waveform diagram of the present invention obtained with the configuration of FIG. 1, and FIG. 3 explains the digital audio signal attenuation device of the present invention. FIG. 4 is a system diagram of a digital filter integrated circuit used in the present invention, and FIG. 5 is a conventional audio signal waveform diagram when data is interrupted or switched. (2) is an up/down counter, (3) is a multiplication circuit, (
4) is a control circuit, (5) is a switching means, OR is an OR gate circuit, (6) is a soft mute signal, (7) is a hold signal, (8) is an input digital audio signal,
(46) is a count clock.

Claims (1)

[Claims] The present invention includes a multiplication circuit and an up/down counter for generating coefficient signals in which the coefficients gradually increase or decrease, and the multiplication circuit doubles as the multiplication circuit of a digital filter. . A digital audio signal attenuation device, characterized in that the multiplication circuit multiplies the input digital audio signal by the coefficient signal of the up/down counter.