JPS634489A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent mis-readout due to charge shares by using a control signal switching internal access and external access to synchronize an address signal supplied externally asynchronously and selecting a complementary data line. CONSTITUTION:When the inverse of a busy signal BUSY is set to a low level to indicate memory access by an internal circuit, an output signal of an inverter circuit N10 goes to a high level to bring the output of NOR gates G4, G9 to a low level (logical 0). That is, the transmission of a timing signal formed based on the inverse of a clock signal DP from a microcomputer side is inhibited. Then a NOR gate circuit G11 fixed the inverse of an address A0 to a low level independently of an address signal from the microcomputer side. In case of the readout in the unit of 16 bits, malfunction due to the possibility caused by the charge shares through the simultaneous operation of column switches MOSFETs Q11, Q13 and Q12, Q14 is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and relates to a technique effective for use in a static RAM built in a speech recognition device using DP matching, for example.

[Conventional technology]

Speech recognition using the DP matching method is a method that normalizes and matches variations in the time axis of speech patterns.
It is widely used because it provides high recognition performance.

Even when the same person utters the same word normally, the speech speed varies.

As a result, the time axis of the audio pattern is expanded or contracted.

In order to normalize this expansion and contraction, the time axis of the negative pattern is varied in various ways to maximize approximation to the other pattern. In other words, the input pattern and the standard pattern with similar feature vectors are matched, and the sum of the distances between the feature vectors (cumulative distance) on the correspondence relationship (time normalization function) is calculated.
is recognized by finding the minimum among various correspondences.

Regarding the above speech recognition technology, for example, ■ "Fundamentals of speech information processing" published by Ohmsha on November 30, 1980, Shuzo Saito and Kazuo Nakata, pp. 182-215, and Journal of the Acoustical Society of Japan, Vol. 127, 1971, p. 9, p. 483. There are ~490 pages.

[Problem that the invention seeks to solve]

Data of a standard pattern close to the input pattern is temporarily stored in the built-in RAM. Then, the standard pattern is read out by an external microcomputer and the most similar standard pattern is selected. For this reason, the above RA
M is accessed by an external address signal asynchronous to the internal circuit. When reading out the RAM using a dynamic method, in other words, a precharge circuit is provided on the data line to which the memory cell is connected, and this precharge potential is used to generate a read signal by discharging through the selected memory cell. If the memory access is performed asynchronously as described above, the address may be switched by the external address signal while the RAM is being read by the internal signal.

When such address switching is performed, for example, unselected data lines to be maintained at a precharge level,
A problem arises in that charge sharing occurs between the data line and the data line that has been partially read, resulting in erroneous reading.

An object of the present invention is to provide a semiconductor integrated circuit device including a RAM that prevents malfunctions due to asynchronous access from the outside.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, for a static RAM in which a precharge circuit is provided on a complementary data line to which a memory cell is coupled, an address signal supplied asynchronously is synchronized with a control signal instructing external access to perform a complementary data line selection operation. Let it happen.

[For production]

According to the above-mentioned means, switching operation of the complementary data line can be prevented by an external address during reading, so that erroneous reading due to charge sharing can be prevented.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a static RAM built into a semiconductor integrated circuit device constituting a speech recognition device. Each circuit in the figure is formed on a semiconductor substrate such as, but not limited to, single crystal silicon using known CMO3 integrated circuit manufacturing techniques.

In the figure, the P-channel MO3FET is distinguished from the N-channel SFET by adding an arrow to its channel portion (substrate gate).

In this embodiment, although not particularly limited, a total of 16 memory cells MC are coupled to one word line WO or the like. The eight memory cells are divided into upper bits and lower bits. In the figure, a complementary data line DO9DO representing the lower bits and a complementary data line D8°D8 representing the upper bits are exemplarily shown.

The memory cell MC represented by the lower bit is a CMOS inverter circuit N whose input and output are cross-connected.
1 and N2, and a transmission gate for address selection provided between the common connection point of the input and output and the complementary data '4IADO, Do) MO3FETQ5. Consists of Q6. Above transmission game) MO3FETQ5. The gate of Q6 is coupled to word line WO. Similarly, the memory cell MC represented by the upper bit is connected to the CMOS inverter circuit N3.
゜N4 and transmission gate MO3FETQ7. Consists of Q8.

The complementary data lines Do, DO and D8. A P-channel precharge MO is connected between D8 and the power supply voltage Vcc.
3FETCI to Q4 are provided. These MO3
A precharge signal PA is supplied to the gates of FETCI to Q4.

Word lines WO to Wn are selected by a selection signal formed by an X decoder circuit OCR (not shown) and an output signal from NOR gate circuits GOO to GOn receiving a control signal PB.

This causes the control signal PB to be at a high level (logic “1”).
When , regardless of the output signal of the X decoder DCR,
When all the word lines are brought to a low level non-selected state, the complementary data lines Do, Do and D8 . D8 is provided with a write/read circuit for the next internal access.

The output terminals of clocked inverter circuits CNI and CN2 constituting the write circuit are coupled to each of the complementary data lines Do and Do. Moreover, the negative complementary data line Do is
Clocked inverter circuit CN that constitutes the readout circuit
3 input terminal. The output terminal of this clocked inverter circuit CN3 is coupled to a corresponding one of a lower bit data bus LBB consisting of 8 bits (not shown). This data bus LBB is coupled to the input terminal of the write clocked inverter circuit CN2. Further, the input signal of the clocked inverter circuit CN2 is inverted by the inverter circuit N5 and transmitted to the input terminal of the clocked inverter circuit CNI. The write clocked inverter circuits CNI and CN2 are put into operation by a write signal W generated by an internal control circuit. Further, the read clocked inverter circuit CN3 is brought into operation by a read signal R generated by an internal control circuit.

Complementary data line D8. representing the upper bits. D8 is also provided with a write circuit consisting of locked inverter circuits CN4, CN5 and an inverter circuit N6, and a read circuit consisting of a clocked inverter circuit CN6, similar to the above.

As a result, a write or read operation is performed from the internal circuit to the RAM in units of 16 bits.

In this embodiment, in order to perform memory access in units of 8 bits with an external microcomputer, complementary data lines DO and D8 . D8 is an N-channel type column switch MO3FETQI 1. Ql 2 and Ql 3.
They are commonly connected via Ql4. At this common connection point, there are P-channel precharge MO3FETs Q9 and Q10 that receive the same precharge signal PA as described above.
is provided. Also, at the common connection point, the locked inverter circuit CN7. A write circuit consisting of SN8 and an inverter circuit N8, and a read circuit consisting of a clocked inverter circuit CN9 are provided.

The clocked inverter circuits CNT and CN8 constituting the write circuit are brought into operation by a write signal MW supplied from the microcomputer side. The clocked inverter circuit CN9 constituting the read circuit is put into operation by a read signal MR from the microcomputer side.

The input terminal of the write circuit and the output terminal of the read circuit are connected to an external terminal MCD connected to a micro combinator (not shown).

In order to access the memory in units of 8 bits, the switches MO3FETQI 1 and Ql2 and Ql3 and Q
The gate of l4 is supplied with an address signal AO supplied from the microcomputer side and an output signal of an inverter circuit N7 that receives this address signal AO. As a result, if the address signal AO is at a high level, for example, the switches MO3FETQI1 and Ql2 are turned on, and the complementary data lines DO, DO(
Dl, D1~D? , D7 (not shown) are connected to the common connection point (the output terminal of the write circuit and the input terminal of the read circuit) consisting of the eight sets. In addition, the address signal AO
If is at low level, the output signal of inverter circuit N7 becomes high level and switch yfMo S F E TQ 1
1 and Ql2 are turned on. As a result, the complementary data line D8 . D8 (D9.D9~D15
．． Dl5...not shown) is a common connection point consisting of the above eight groups (output terminal of the write circuit and input terminal of the read circuit)
connected to.

The signal that should be output rises to a high level).
This causes a malfunction in the determination of the read signal using the logic threshold voltage of the clocked inverter circuit CN9.

Therefore, in this embodiment, the address signal AO is synchronized by a circuit as described later.

FIG. 2 shows a circuit diagram of an embodiment of the memory access circuit of the RAM.

The memory array M-ARY is composed of memory cells MC arranged in a matrix as shown in FIG. 1 above. The input/output circuit I10 is composed of the above write/read circuit and column selection circuit. The precharge circuit PC is composed of the precharge MOS FET as described above. Further, the X decoder circuit R includes the gate circuits GOO to GQn as described above.

The busy signal BUSY allows memory access from the outside when it is high level, and indicates the memory access by internal circuits when it is low level and the above address signal AO
is input asynchronously with the internal operation, for example, the word line WO is selected and the non-inverted data line data mD of the lower bit is input according to the storage information of the memory cell coupled to it.
When O is at a low level and inverted data '1aDo is at a high level, if the address signal AO is at a high level, the potential of the common connection point changes according to the data of the lower bit. In this state, the address signal AO is switched from high level to low level, and the switch MO3FETQI
1. Switch MO3FET QI instead of Ql 2 3.
When Ql 4 is turned on, complementary data lines D 8 . The signal of D8 is transmitted. At this time, when the stored information of the memory cell on the upper bit side is opposite to that of the lower bit, that is, when the non-inverted data mDB is at a high level and the inverted data line D8 is at a low level, the signal of the lower bit is Charge sharing occurs with the potential of the common connection point according to
The signal to be maintained at a high level is lowered to a low level (shown as a low level).

Signal DP is a clock signal supplied from the microcomputer side, and is supplied to inverter circuit N16. The output signal of this inverter circuit N16 is supplied to one input of a NOR gate circuit G6 and a NAND gate circuit G7 on the - side. Each of the above gate circuits G6
．． The output signal of the inverter circuit N16 is connected to the other input of the inverter circuit N17.G7. It is supplied via a delay circuit consisting of N18. A precharge signal based on the signal DP is generated from the output terminal of the NOR gate circuit G6, and a precharge signal is generated from the output terminal of the NAND gate circuit G7.
A control signal for the decoder is formed. As a result, as is clear from the timing diagram described later, the selection operation of the decoder circuit is inhibited and the word Set the line to low level and unselected state. Further, the word line selection operation is started after the precharge operation is completed. The reason why there is a certain time difference between the precharge operation and the word line selection operation is that during the precharge operation, the precharge level decreases due to the memory cell being selected, and the memory cell This prevents direct current from being consumed through the

Signal TP is a clock signal supplied from the internal circuit side, and two signals having the same time relationship as described above are formed by inverter circuits N12 to N14 similar to those described above, NOR gate circuit G1, and NAND gate circuit G2.

The reason why two timing generation circuits are provided in this manner is that the clock signal on the internal circuit side and the clock signal on the micro combinator side have different periods.

The signals formed by these two timing generation circuits are selectively transmitted to the above-mentioned bridge via switching gate circuits consisting of NOR gate circuits G3 to G5 and G8 to GIO, respectively, in response to a switching signal formed based on the signal BUSY. It is output as a charge signal PA and a signal PB.

The output signal of the NOR gate circuit G1 formed based on the clock signal TP from the internal circuit side is a NOR gate circuit controlled by the output signals of two inverter circuits NIO and Nil in a cascade configuration receiving the busy signal BUSY. It is supplied to the input of the NOR gate circuit G5 via G3. On the other hand, the output signal of the NOR gate circuit G6, which is formed based on the clock signal DP from the microcomputer side, is input to the NOR gate circuit G5 via the NOR gate circuit G4, which is controlled by the output signal of the inverter circuit NIO. Supplied. The output signal of this NOR gate circuit G5 is inverted by an inverter circuit N15 and supplied to the RAM precharge circuit PC as the precharge signal PA.

The output signal of the Nands gate circuit G2, which is formed based on the clock signal TP from the internal circuit side, is the same as the NOR gate circuit G which receives the same control signal as the NOR gate circuit G3.
8 to the input of the NOR gate circuit GIO.

On the other hand, the output signal of the Nant gate circuit G7, which is formed based on the clock signal DP from the microcomputer side, is transmitted to the NOR gate circuit G1 via the NOR gate circuit G9 which receives the same control signal as the NOR gate circuit G4.
0. A control signal PB supplied to the decoder DCH is formed from the output of this NOR gate circuit G10.

The multiplexer MPX switches between the internal address DPA and the external address MCA supplied from the microcomputer side in response to the busy signal BUSY, and accesses the external address MCA in units of 8 bits. The 1-bit signal is input to a NOR gate circuit Gll that performs synchronization with the internal circuit. The busy signal BUSY is supplied to the other input of the NOR gate circuit Gll through the inverter circuit 10.

The address signal AO is formed from the output terminal of this NOR gate circuit Gll.

For example, if the busy signal BUSY is set to low level and instructs the internal circuit to access the memory, the output signal of the inverter circuit NIO becomes high level, and the outputs of NOR gate circuits G4 and 09 are set to low level (logic "0"). That is, transmission of the timing signal formed based on the clock signal DP from the microcomputer side is prohibited. At the same time, the NOR gate circuit Gll also fixes the address AO to a low level regardless of the address signal from the microcomputer side. With this, 16
When reading in bit units, column switches MO3FETQI 1 and Q13 and Q12 and Q14
This prevents malfunctions that may occur due to charge sharing caused by simultaneous operation of the two. Further, the output signal of the inverter circuit Nil is at a low level (logic “0”).
”), the NOR gate circuits G3 and 08 essentially operate as inverter circuits and transmit timing signals formed based on the clock signal TP supplied from the internal circuit side. G5
A timing signal formed based on the clock signal TP is sent out from the output of GIO. That is, the precharge signal PA and the control signal PB are formed based on the clock signal TP from the internal circuit side.

Further, as shown in FIG. 3, for example, a busy signal BUs
When Y is changed from low level to high level to permit external memory access, the output signal of the inverter circuit Nil becomes high level, and the NOR gate circuits G3 and 0
8 is set to low level (logic "0"), that is, transmission of the timing signal formed based on the clock signal TP from the internal circuit side is prohibited. Further, the output signal of the inverter circuit NIO becomes low level (logic "0"), and the NOR gate circuits G4 and 09 essentially operate as an inverter circuit, based on the clock signal DP supplied from the microcomputer side. transmits timing signals formed by In this case, even if the asynchronously supplied clock signal is set to the signal level, it is invalidated as shown by diagonal lines in the figure. As a result, NOR gate circuit G5
A timing signal formed based on the clock signal DP is sent from the output of GIO. That is, the precharge signal PA and the control signal PB (the input side signals of the NOR gate circuit G10 in the figure are shown) are as follows.
It is formed based on the clock signal DP from the microcomputer side. In this case, as shown in the figure, the precharge signal PA becomes high level to complete the precharge operation, and then the signal PB becomes high level (PB is low level) after the delay time by the delay circuit. The word line selection operation is started. Further, after the signal PB first becomes low level (signal PB is high level) and puts the word line in a non-selected state, the precharge signal PA becomes low level and starts the precharging operation of the complementary data line. By providing such a time difference, during the precharge operation, no direct current is consumed between the precharge MOS FET and the memory cell, and the complementary data line is reliably maintained at a high level such as the power supply voltage Vcc. can be precharged.

The above memory access (precharge and address selection operations) is performed using the clock signal D on the microcomputer side.
This is done in synchronization with P. At the same time, the NOR gate circuit Gll transmits the address signal AO for column selection supplied from the micro combinator side in response to the high level of the busy signal BUsY. As a result, memory access and address signal AO change in synchronization, so malfunctions due to charge sharing due to switching of the column switch MO3FET can be prevented in the memory read operation in units of 8 bits as described above. .

The outline of the speech recognition operation by the speech recognition circuit (not shown) is as follows.

The input pattern is temporarily stored in the memory circuit.

The input pattern signal stored in this memory circuit is output as a digitized input pattern signal according to a fixed sampling period. Multiple standard patterns are
stored in a separate memory circuit. The address calculation section generates an address signal for referring to standard pattern data required by a distance calculation section, which will be described later, and reads out the standard patterns one by one.

The distance calculation section calculates the distance between the input pattern and the read standard pattern.Thus, a pattern with a close distance calculation is selected and stored in the RAM. By calculating distances between all standard patterns stored in the memory circuit and the input pattern, a plurality of standard patterns approximated to the input pattern are stored in the RAM.

The microcomputer selects a standard pattern with the minimum cumulative distance from among the plurality of standard patterns stored in the RAM and outputs it as a vl recognition result.

The effects obtained from the above embodiments are as follows. That is, (1) A control signal for switching between internal access and external access is used to synchronize address signals supplied asynchronously from the outside to perform a complementary data line selection operation. This makes it possible to prohibit the switching operation of the complementary data line due to switching of the address signal during internal access, thereby achieving the effect that erroneous reading due to charge sharing can be prevented.

(2) By performing the precharge operation and the word line selection operation by the decoder with a time difference, it is possible to prevent the generation of direct current through the precharge MOSFET and the memory cell. This has the effect of reducing power consumption and improving the read operation margin through reliable precharge operation.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the bit configuration for accessing the RAM can be modified in various ways.

Also, specific circuits of a timing generation circuit that forms a precharge signal and a memory selection control signal based on a clock signal, and a switching circuit that selectively outputs a precharge signal, etc. that is formed based on an external clock and an internal clock signal. The configuration can take various embodiments. Furthermore, the memory cell is a HiCMO3 type memory cell consisting of a pair of memory MO3FETs whose gates and drains are cross-connected, and a high resistance provided between the drains of these memory MO3FETs and a power supply voltage. Good too.

In the above explanation, the invention made by the present inventor has mainly been explained in the case where it is applied to a RAM built in a semiconductor integrated circuit device constituting a speech recognition device, which is the field of application in which the invention was made by the present inventor. Various semiconductors, including static RAM, in which memory access is performed by a signal formed by an internal circuit and an external signal supplied asynchronously as described above, and a precharge circuit is provided on a complementary data line. Widely used in integrated circuit devices (
Available.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a control signal for switching between internal access and external access is used to synchronize address signals supplied asynchronously from the outside to perform a complementary data line selection operation. This makes it possible to inhibit the complementary data line switching operation using the address signal for column switching during internal access, thereby preventing erroneous reading due to charge sharing.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a RAM showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the memory access circuit, and FIG. 3 is a circuit diagram showing an example of its operation. FIG. MC...Memory cell, DCR...X decoder, PC...
Precharge circuit, M-ARY...memory array, Il
o...Input/output circuit, MPX...Multiplexer

Claims (1)

[Claims] 1. Static type RA in which a precharge circuit is provided on a complementary data line to which input/output nodes of memory cells are coupled.
1. A semiconductor integrated circuit device comprising: M and a synchronization circuit that synchronizes an asynchronously supplied external address signal with a control signal instructing external access to perform a selection operation of the complementary data line. 2. The static type RAM has a pattern recognition circuit including a built-in distance calculation circuit that receives digitized input pattern and standard pattern data according to a fixed sampling period and calculates the distance between the two data, and an external microcomputer. The semiconductor integrated circuit device according to claim 1, wherein the access is performed by.