JPS6344256A - Buffer memory controlling system - Google Patents

Abstract

PURPOSE:To prevent a processing from being interrupted, by providing an address comparator, and a buffer memory, and obtaining data required at the next stage from the buffer, even when the data is being loaded on a cache memory. CONSTITUTION:The buffer memory 6 stores the data of an (n+1)-th address, and the address comparator 5 stores the address of the (n+1)-th address. A processor 1 reads out the data of an n-th address, and also, makes the buffer memory 6 read out the data of the (n+1)-th address, and stores the address of the (n+1)-th address in the address comparator 5, and after that, permits data loading on the cache memory 3. Even during the data loading on the cache memory 3, it is possible to obtain the data of the (n+1)-th address required at the next stage, from the buffer memory 6.

Description

[Detailed Description of the Invention] [Summary] In a device equipped with a cache memory between a processor and an input/output device, when desired data does not exist in the cache memory, data is loaded from the input/output device to the cache memory. During this data loading time, access to the processor's input/output device is blocked, so the data at the address next to the data read from the input/output device by the processor is stored in the buffer memory, which reduces processing efficiency. prevent.

[Industrial application field]

The present invention relates to a device equipped with a cache memory between a processor and an input/output device, and in particular, when there is no desired data in the cache memory and data is loaded from the input/output device to the cache memory, the processing efficiency of the processor is improved. This invention relates to a buffer memory control method that prevents deterioration.

In information processing equipment, a processor reads data from an input/output device, processes this data, and writes it to the input/output device to accomplish a job, but there is a need to improve the processing efficiency of information processing equipment, and this Therefore, cache memory is used to reduce the time it takes for a processor to access an input/output device.

By the way, cache memory usually stores data that is most likely to be used by a processor, but when the cache memory does not contain data that the processor needs, the processor accesses the memory and also stores data in the cache memory. Load.

At this time, it is necessary that the processing efficiency of the processor does not deteriorate due to the processing of the processor being made to wait.

[Conventional technology]

FIG. 2 is a block diagram illustrating memory access using a conventional cache memory.

The processor 1 sends an address to the tag circuit 2 to check whether the desired data exists.

If the desired data address exists in tag circuit 2,
The data at the corresponding address of 8 is read from the cache memory 3, but if the address of the desired data is not found, that is, if it is not hit, the processor 1 sends the address to the memory 4 and reads the data from the memory 4. At the same time, the same data is also loaded into the cache memory 3.

In this case, data loaded into the cache memory 3 is normally transferred as a data block having a plurality of consecutive addresses. Therefore, this loading requires time, and the memory 4 is occupied during this time by loading data from the cache memory 3.

For example, the processor 1 reads the data at address n from the memory 4 and also immediately reads the data at address n+1.
The memory 4 is accessed, but since the memory 4 is occupied as described above, access to the data at address n+1 of the memory 4 has to wait until the data is loaded into the cache memory 3.

[Problem that the invention seeks to solve]

As mentioned above, if the cache memory does not provide a hint, if the processor accesses the memory at consecutive addresses, the processor will have to wait until the data has been loaded from memory to the cache memory, reducing processing efficiency. There is a problem with doing so.

[Means for solving problems]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

FIG. 1 shows an arrangement in which an address comparison circuit 5 and a buffer memory 6 are added to FIG. 2.

Buffer memory 6 stores data at address n+1, and address comparison circuit 5 stores address at address fi+1.

When access to the memory 4 is blocked, the processor 1 refers to the address comparison circuit 5, and when the addresses match, that is, when the address is n+1, the processor 1 reads data from the buffer memory 6.

[Effect]

With the above configuration, the processor 1 reads the data at address n from the memory 4, outputs the data at address n+1 to the buffer memory 6 one after another, stores the address at address n+1 in the address comparison circuit 5, and then reads the data at address n+1 from the memory 4. By loading data into the cache memory 3, it is possible to obtain the next necessary data at address n+1 from the buffer memory 6 even while data is being loaded into the cache memory 3, thereby preventing interruption of processing. I can do it.

[Example] In FIG. 1, when the processor 1 is notified from the tag circuit 2 that the target address n does not exist and was not hit, the processor 1 sends the address of the n address to the memory 4 and stores the data. Read out. At this time, the data at address n+1 is read out to the buffer memory 6, and the address at address n+1 is stored in the address comparison circuit 5.

The processor 1 then instructs the tag circuit 2 to load the data of one data block from the memory 4 to addresses fi+1 and n+2 sequentially from address n to the cache memory 3.

After taking in the data at address n, processor 1 immediately accesses memory 4 to read data at address n+1, but this access is rejected because memory 4 is loading data into cache memory I73. Therefore, the processor 1 refers to the address of the address comparison circuit 5, and here n
Since there is an address at address +1, data from the buffer memory 6 is fetched.

Processor 1 transfers data at address n+1 to buffer memory 6
When the data is fetched from the cache memory 3, the data loading from the memory 4 to the cache memory 3 has been completed, so if the processor 1 subsequently needs data at address n+2, the tag circuit 2 will take the address - failure, so the data will be loaded from the cache memory 3. Data can be read.

Although this embodiment has been described by storing data at address n+1 in the buffer memory 6, it goes without saying that there may be a plurality of addresses.

〔Effect of the invention〕

As described above, the present invention can improve processing efficiency by preventing processor processing from having to wait in order to load data from the memory to the cache memory when the cache memory is not hit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram illustrating memory access using a conventional cache memory. In the figure, 1 is a processor, 2 is a tag circuit, 3 is a cache memory, 4 is a memory, 5 is an address comparison circuit, and 6 is a buffer memory. Ichisho O7+f'3λ7
Sono Zuhoki 1 2

Claims (1)

[Claims] A cache memory (3) that reduces the time it takes for a processor (1) to access an input/output device (4), and data desired by the processor (1) exists in the cache memory (3). When the processor (1) reads data from the input/output device (4), the device that loads the data from the input/output device (4) chains the address specified by the processor (1). a buffer memory (6) that stores the data of the chained address, and an address comparison circuit (6) that stores the chained address.
5), and when the processor (1) reads data from the input/output device (4) because the desired data does not exist in the cache memory (3), the address chained to the address specified by the processor (1) is provided. When continuously reading data from the buffer memory (6), the address stored in the address comparison circuit (5) is referred to, regardless of data loading from the input/output device (4) to the cache memory (3). A buffer memory control method characterized by reading data from ).