JPS6343515A - Failure detecting circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application This invention relates to a failure detection circuit attached to an SSR (solid state relay) or the like that controls a load circuit.

(b) Conventional technology In general, a three-phase SSR is used to connect a heater (
The 6th controller is used to connect and control loads such as
The circuit shown in FIG. 7 is used, and the circuit shown in FIG. 7 is used to control loads such as a three-phase power supply and a three-phase cotton wadding heater using a three-phase SSR. A conventional load control circuit using this type of SSR is not equipped with a failure detection circuit.

(c) Problems to be Solved by the Invention The main failure modes that may occur in a load control circuit using SSR and the phenomena caused by the failure modes are shown in the following table.

<Table 1> When such a failure occurs, current does not flow due to disconnection when the SSR is turned on, a heater cooling accident occurs in the case of a heater load, and the motor does not rotate in the case of a motor load. Additionally, if one phase of a three-phase load does not turn on, overcurrent will flow through the other phases, leading to wire breakage. Further, when the SSR is turned off, if a current flows due to a short circuit in an element or the like, an accident such as heating of the heater or rotation of the morph may occur. Of these accidents,
If the heater load rotates even though the heater is cooled and the motor load rotates even though the SSR is turned off, this is particularly dangerous as it may lead to a serious accident. However, since conventional circuits do not have a failure detection function, it is not possible to discover failures and prevent accidents from occurring.

In view of the above, an object of the present invention is to provide a failure detection circuit that can detect a failure in a relay circuit or a load circuit and take measures to safely operate the load circuit.

(d) Means and operation for solving the problem The failure detection circuit of the present invention is a current detection circuit (4a to 4
c, 5a to 5c), a relay on/off detection circuit (2) that detects the on/off state of the relay circuit (14), and a relay on/off detection circuit (2) that receives the output of the current detection circuit and the output of the relay on/off detection circuit as input signals. , a logic circuit (7) that outputs a fault signal when these input signals are in a predetermined logic state; a fault signal holding circuit (9) that holds the fault signal from this logic circuit; Output circuits (10, 11, 1) that perform processing to operate the circuit safely
2).

In this failure detection circuit, an on/off detection circuit detects when the relay circuit is on or off, and a current detection circuit detects whether there is a current in the load. Then, when the logic mode of the signals output from the on/off detection circuit and the current detection circuit of these relay circuits is a predetermined failure mode, the logic circuit outputs a failure signal. This fault signal is then held in a fault signal holding circuit.

In response to the fault signal being held, the output circuit may, for example, flash a light emitting element to provide an alarm to take measures to make the load circuit safe, or in response to the fault signal, the output circuit may activate a keep relay. Take measures to operate the load circuit safely.

(E) Examples The present invention will be explained in more detail with reference to Examples below.

FIG. 1 is a block diagram of a failure detection circuit showing one embodiment of the present invention. This failure detection circuit is used attached to the SSR.

This failure detection circuit includes a power supply circuit 1, S, which outputs a constant voltage.
Input circuit 2 that detects SR on signal or off signal
, a prohibition signal circuit 3 that outputs a signal for preventing malfunction, detects the presence or absence of current flowing in the three-phase load current lines 6a, 6b, and 6C through current transformers 5a, 5b, and 5C, and when the current exceeds a predetermined value, the current an amplifier circuit 4a that outputs a logic state signal of
4b, 4C3 A logic circuit 7 that determines a failure state from the logic states of the signals from the input circuit 2, prohibition signal circuit 3, and amplifier circuits 4a, 4b, and 4c and outputs a failure signal, and a signal in this logic circuit 7. A discharge signal circuit 8 outputs No. 3 for discharging the capacitors in the amplifier circuits 4a, 4b, and 4c, and a failure signal holding circuit 9 for reliably transmitting the failure signal to each output circuit. S in response to a fault signal
5SROFF circuit 10 that cuts (off) the input signal of SR, LED (light emitting diode) in response to a failure signal
The LED flashing circuit 11 flashes on and off to notify the operator of a failure, and the keep relay drive also drives a keep relay in response to a failure signal, and the relay output transmits a signal to the protective equipment to lower the load circuit to the safe side. circuit 12,
A reset circuit 13 is provided for restarting when the normal state returns from the failure state.

A more specific circuit connection diagram of the failure detection circuit in Figure 1 is shown below.
Figure 2 [Figure 2 (a), Figure 2 (b), Figure 2 (C+,
Figure 2(d)] shows this.

As shown in FIG. 2(a), the power supply circuit 1 includes 12 to 20
A DC input voltage of V is applied to terminal P1. The three-terminal regulator 21 provides a stable constant voltage of 3V (+Vcc) to the terminals P3 and P2 over a relatively wide range of input voltages.
The signal is then supplied to the subsequent circuit.

Note that the diode D is provided to protect against reverse connection, and the capacitor C8 is provided to prevent noise.

Input circuit 2 is a circuit for taking in the 5SR140 input signal as a signal into the failure detection circuit, and
The signal is captured by 2. The light emitting element L2 of the photocoupler PH2 is connected in series to the input circuit of the 5SR14, and lights up when the 5SR14 is turned on.

SSL with a built-in Schmitt circuit etc. in the input circuit? In this case, in order to effectively utilize the function, photocoupler PH
A resistor R4 is connected between the base 11 and emitter terminal of the phototransistor PT2 of No. 2 to reduce the sensitivity of the photocoupler PH2. As a result, the Schmitt circuit in the 5SR14 is turned on, and at the same time, a signal is output to the terminal P. Since the sensitivity of the photocoupler PH2 is lowered,
The current flowing through the resistor R1 becomes minute, and the circuit current can be reduced.

The 5SROFF circuit IO includes a photocoupler PH, transistors Trl, Tr2, and the like.

A failure signal is input to the base of the transistor Tr2 from the failure signal holding circuit 9 via the terminal P6 and the resistor R3.

The emitter of the transistor Trz is connected to the ground GND, and the collector is connected to the base of the transistor Tr and the output of the three-terminal regulator 21, that is, +VcC, via a resistor R2. Also, the resistance R,
, photocoupler PH, light emitting element 7, transistor Tr
The collector and emitter of l are connected in series to +Vc
c and ground GND. Further, the phototransistor PT of the photocoupler PH1 is connected in series to the input circuit of the 5SR14 and the light emitting element L2 of the photocoupler PH.

In the 5SROFF circuit 10, when a voltage is applied to the power supply circuit 1, the transistor Tr is turned on by the base current from the resistor R2, and a photocuff is generated.

A current flows through the light emitting element L1 of PH+, the light emitting element L1 lights up, and the phototransistor PT of the photocoupler PH turns on. Now, when a failure signal is input through terminal P, transistor 'l'rz is turned on and transistor Tr
The base of z becomes the same potential as the emitter, and the transistor T
r is turned off. Therefore, the light emitting element RI of the photocoupler PH is turned off, and the phototransistor PT is turned off.
The 5SR140 input signal is cut and the 5SR14 is turned off. Further, even if the input voltage is no longer applied to the power supply circuit 1 due to some accident in the failure detection state, the photocoupler PH remains off, and a fail-safe is established.

The prohibition signal circuit 3 is composed of a delay circuit consisting of a resistor R6 and a capacitor C2, and a comparator 22.
The on signal of 5SR14 output to terminal P is connected to resistor R8.
A reference voltage is applied to one input terminal of the comparator 22 via a terminal P.

Now, if the SSR ON signal of the input circuit 2 is the signal shown in FIG.
So 1. Since the signal is input manually to the comparator 22 with a delay of time, the output of the comparator 22 outputted to the terminal P8 becomes the signal shown in FIG. This is a signal that the time is near. This signal is input to the logic circuit 7 as a prohibition signal.

The logic circuit 7 does not detect a failure at times t3 and t2. This makes it possible to prevent malfunctions in the logic circuit 7 caused by chattering of the input signal of the 5SR 14 and variations in output due to differences in components and phases of each amplifier circuit. Note that since the comparator 22 employs an output open collector transistor, a resistor R7 is connected between +Vcc and the output terminal to obtain a necessary current.

In the amplifier circuit 4a, as shown in FIG. 2(b), the resistor R6
A series circuit of resistor R1 and resistor R1 connects 10 Vcc and ground G N
A voltage connected between the resistors R8 and R7 and divided by the resistors R8 and R7 is applied to one input terminal of the comparator 24 as a reference voltage. A Zener diode ZD and a resistor R11 are connected in parallel to the secondary winding of the current transformer 5a, and one end of this parallel circuit is connected to the input terminal of the OP amplifier 23. Also, a resistor RIG and a Zener diode ZD are connected in series between +Vcc and ground GND, and the midpoint of the connection is between a resistor R1+ and a Zener diode Z.
While connected to the other end of the parallel circuit of D2, it is also connected to one input end of the OP amplifier 23 via a resistor R12. O
A resistor R13 is connected between the output terminal of the OP amplifier 23 and one input terminal, and the output terminal of the OP amplifier 23 is connected to a diode D.
2. Connected to the input terminal of the comparator 24 via the resistor R14. The output end of the comparator 24 outputs a current detection signal from a terminal P. Further, this output terminal is connected to +Vcc via a resistor R111.

A capacitor C3 is connected between the input terminal of the comparator 24 and the ground GND, and a series circuit of a resistor RI6 and a transistor Tr3 is connected in parallel to the capacitor C3. Furthermore, a resistor RIS is connected between the collector of the transistor Tr3 and the ground GND. The transistor 'R3 is connected from the discharge signal circuit 8 to the terminal P12.
It is designed to turn on when a signal is input.

Now, when a load current flows through the load line that crosses the current transformer 5a, a current corresponding to this current flows through the secondary coil of the current transformer 5a, and a voltage corresponding to this current is obtained across the resistor R8. and is input to the OP amplifier 23. The OP amplifier 23 amplifies the input voltage in the same mode with a resistance ratio R1, , /R1□. The amplified voltage is transferred to the diode D! The signal is half-wave rectified by a resistor RI4 and a capacitor C1, and is smoothed by a resistor RIS and a capacitor C:l, and then input to a comparator 24. When the input voltage is higher than the reference voltage, the comparator 24 outputs a current detection signal from the terminal P in the form of a rectangular wave.

Note that the capacitor C3 with the resistor RI is set to a small time constant, but this is because the on-speed of the photocoupler PH of the input circuit 2 is slower than that of the amplifier circuit 4a, so it is necessary to prevent malfunction.

In addition, since the OP amplifier 23 is a single power supply, an offset voltage is required, and for this purpose, the reference voltage of the comparator 24 (= V
It is set at a voltage that does not exceed c c-Re/ (Rs + R9)).

In a normal state, when the 5SR14 is turned off, the transistor Tr'x is turned on for a time t2 in FIG. 5 by a signal from the discharge signal circuit 8. Therefore, capacitor C
The charges accumulated in the transistor Tr3 are discharged all at once through the resistor R1 and the transistor Tr3, and the output of the comparator 24 is turned off. As a result, even if the 5SR14 is used at high switching frequency, this circuit will function without malfunctioning.

If a failure occurs from the normally on state and the output from the current transformer 5a and the output from the OP amplifier 23 turn off, the transistor Tr3 remains in the off state, and in this case, the transistor Tr3 is discharged through the resistor RI5. Then, the terminal P9 becomes low (level).

The amplifier circuits 4b and 4C are configured in exactly the same way as the amplifier circuit 4a, so the explanation of their configuration and operation will be omitted.However, when current flows in the load line, the rectangular current detection is performed from the terminals PIG and P in the same way. A signal is output.

The logic circuit 7 is connected to the amplifier circuit 4 as shown in FIG. 2 (C1).
a, 4b, and 4c, that is, terminals P7, P,. , P
In addition to receiving the signal (current detection signal) from Il, the output of input circuit 2, that is, the signal from terminal PS (SSR
on signal), the output of the prohibition signal circuit 3, that is, the terminal PIl
Human power is receiving signals from people.

The terminals P, , P, , , pH are connected to the input terminals of the NAND circuit GI, and imparks N1, Nz, N, respectively.
It is connected to the input end of the NAND circuit G2 via x. The output of the NAND circuit G1 is connected to one end of the human power of the NAND circuit G:l, and the output of the NAND circuit G is connected to one end of the human power of the NAND circuit G4. The terminal P is connected to the other input end of the NAND circuit G, and is also connected to the other end of the input of the NAND circuit G4 via an inverter N4. Also, terminal P. is connected to yet another end of the input of the NAND circuit G3, and is also connected to yet another end of the NAND circuit G4 via an inverter N. The outputs of NAND circuits G3 and G4 are connected to the input terminal of NAND circuit G, and the output terminal of NAND circuit G5 (terminal P2
．． ), a failure detection signal is output.

Now, the presence or absence of load current, that is, the amplifier circuits 4a, 4b, 4
Table 2 shows all the combinations of the outputs of c and the logical states of the outputs (A, B) of the NAND circuits G, , G2.

<Table 2> Next, the outputs of NAND circuits G1 and G2 and terminals P3 and Pa0
Considering the combination of Al1, Table 3 shows the results.

(Left below) <Table 3> Therefore, the failure detection signal output from terminal PI5 is A B P5P [l + A B PSP8 + A
B PSPII + λBvsTs=APsPa (B +
B) + BPsPs (A + λ) = AP, P,
+ BP, PIl. In this logical formula, the former term corresponds to the output of the NAND circuit G3, and the latter term corresponds to the output of the NAND circuit G4, and both outputs pass through the NAND circuit G and are output from the terminal PIS in an OR manner.

The discharge signal circuit 8 is composed of a NAND circuit G and an inverter N6, and as shown in FIG. Output to PI2.

The failure signal holding circuit 9 includes a photocoupler PH, as shown in FIG. SCR
It is also connected to the ground GND via a resistor R24 and a capacitor C5. In addition, the cathode of the thyristor SCR is also connected to the ground GND.
It is connected to the.

A failure detection signal from terminal PI5 is input to the gate of Cyrisk SCR via resistor RI7 and diode D. A parallel circuit of a resistor R2° and a capacitor C4 is connected between the gate of the Cyrisk SCR and the ground GND. Diode D3, resistor R1,.

R2O, , RZ:l and capacitors C4 and C6 are provided for noise protection.

The collector of the phototransistor PT of the photocoupler PH is connected to +Vcc, the emitter is connected to the ground GND via the resistor R24, and the emitter is connected to the terminal P6.
After that, four hold outputs of the fault signal are output.

In this failure signal holding circuit 9, the logic circuit 7
When a failure signal is input through 5, the thyristor SCR is turned on, +Vcc, ) transistor T r 4, resistor R2
1. Current flows through the light emitting element L3 of the photocoupler P 1 (j, and the light emitting element L3 of the photocoupler PI!3 lights up. Therefore, the phototransistor P of the photocoupler PHff
The photodetection current flows through T3, and the terminal P.

A high (level) signal is output. Even if the failure signal input to the terminal PIS is turned off, the thyristor SCR maintains ○N, so the high signal output from the terminal P6 is maintained as it is. The reset circuit 13 operates,
When the transistor Tr is turned off, the light emitting element of the photocoupler PH3 turns off, and the signal output from the terminal P6 also becomes low (off).

The LED blinking circuit 11 has the output of the failure signal holding circuit 9 connected to the input terminal of the OP amplifier 25, a diode D4, and a resistor R2.
connected to be input via S, and the OP amplifier 25
The output terminal of is connected to one input terminal via a resistor R26, and this - input terminal is further connected to the ground GND via a capacitor C5. In addition, the input terminal of the OP amplifier 25 is connected to ground via the resistor 122□.
while being connected to its output terminal via a resistor R28.

A resistor R is connected between the output terminal of the OP amplifier 25 and the ground GND.
Light emitting element (LED) L with 29 inserted in series.

is connected.

In this LED blinking circuit 11, when the holding output of the failure signal is input, the output is repeatedly turned on and off at a predetermined period in the OP amplifier 25, that is, it performs an oscillation operation, and the light emitting element L4
blinks and lights up to visually notify the occurrence of 1λ.

The keep relay drive circuit 12 includes a keep relay 27 and a transistor for operating the keep relay 27.
'rs, and the output of the failure signal holding circuit 9 is applied to the base of the transistor Tr5 via a resistor R3, a diode Ds, a capacitor C, and a resistor Rtz.

When a failure signal is input, the transistor Trs, which is normally off, turns on, switching the keep relay 27 from a normally closed contact to a normally open a contact. The operation of this keep relay 27 activates the external equipment and brings the load circuit to the safe side. A specific example of this will be described later. In addition, to drive the relay, resistor R3 and R3□, capacitor C1, and transistor T
A differentiating circuit composed of r prevents unnecessary current from flowing. Diode D6 is transistor T
This is a resistor for protection of rs.

The reset/node circuit 13 includes a reset switch 28 and transistors Tr, Tr6, a resistor R2□ is connected between +■CC and the base of the transistor 7r4, and +
A reset switch 28 is connected between Vcc and a set terminal S of the keep relay 27. Transistor Tr6
The collector is connected to the connection point between the diode D and the capacitor C1, and the emitter is connected to the ground GND. Further, the set terminal S of the keep relay 27 is connected to the base of the transistor Tr4 via a resistor R3:I, and is also connected to the base of the transistor Tr via a resistor R34.

Normally, transistor Tr is on, transistor Tra
is off, but when the reset switch 28 is turned on, the base potentials of the transistors Try and Tr6 become high, the transistor Tr is turned off, and the transistor Tr6 is turned off.
turns on. When the transistor Tr is turned off, the thyristor SCR is turned off. As a result, the terminal P becomes low, the transistor Tr is turned off, and the transistor T
r.

is turned on, and 5SR14 is turned on. In addition, light emitting element L4
disappears, and keep relay 27 also returns. transistor T
When rb is turned on, the charge in capacitor C7 is discharged.

FIGS. 3 and 4 show an example of how the protective equipment of the nine load circuits is connected when the keep relay 27 is activated in the failure detection circuit.

FIG. 3 shows that when the keep relay 27 is switched from the B contact to the A contact due to failure detection, a signal is sent to the interface device 30 such as a PC or a relay, and the interface device 3
From 0, the load line converter (breaker) 31 is turned off, the patrol light 32 is turned on, or the fuser 33 is turned on.

FIG. 4 shows an example where it is sufficient to simply turn off the contactor of the load line as a protection.The keep relay 27 is normally kept in the a contact state, and the load line 3
5 is turned on, and when a failure is detected, the keep relay 27 is kept at contact B and the contactor 34 is turned off. In this example, the ink face device, which is a contactor protection circuit, is not required, and the reaction time (protection device activation time) is also faster.

(F) Effects of the Invention According to the present invention, failures are detected based on the on/off detection output of relay circuits such as SSRs and the logical state of whether or not load current is detected. First, it is possible to detect failures even when the system is off, so that if a failure occurs, it can be reliably discovered and accidents can be prevented from occurring. In addition, since the current flowing in the load line is judged as "flowing" or "not flowing", that is, logical values "1" and "0", there is no need for the user (operator) to make delicate settings such as the volume, making it easy to use. Not complicated.

Also, if a fuse is installed on the load line,
If a fuse blows due to a short circuit accident and current no longer flows to the load line, this can be detected, so it can also be used as a fuse rupture detection device.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of an SSR failure detection circuit, but does not show an embodiment of the present invention.
Figures (C1 and 2(d) are circuit diagrams showing specific connections of the same failure detection circuit, and Figures 3 and 4 are the keep relay drive circuit of the same embodiment circuit and the load circuit by external equipment. FIG. 5 is an explanatory diagram for explaining the protection of the circuit, and FIG. 6 is a waveform diagram for explaining the operation of the discharge signal circuit of the same embodiment circuit.
FIG. 7 is a circuit diagram showing an example of the use of a conventional general SSR. 2: Input circuit, 4a/4b-4c: Amplifier circuit, 7: Logic circuit, 9: Failure signal holding circuit, 10: 5SROFF
Circuit, 11: LED blinking circuit, 12: Keep relay drive circuit.

Claims (4)

[Claims] (1) A current detection circuit that detects the current in the load circuit and outputs a logic state signal indicating the presence or absence of current, a relay on/off detection circuit that detects the on/off state of the relay circuit, and the output of the current detection circuit. and a logic circuit that receives the output of the relay on/off detection circuit as an input signal and outputs a fault signal when these input signals are in a predetermined logic state; and a fault signal holding circuit that holds the fault signal from this logic circuit; A failure detection circuit consisting of an output circuit that performs processing to safely operate a load circuit in response to a failure signal. (2) The failure detection circuit according to claim 1, wherein the output circuit is a circuit that turns off the relay circuit. (3) The failure detection circuit according to claim 1, wherein the output circuit is a light emitting element drive circuit and blinks the light emitting element in response to the failure signal. (4) The failure detection circuit according to claim 1, wherein the output circuit is a keep relay drive circuit.