JPS6342422B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device including an insulated gate field effect transistor.

Conventionally, insulated gate field effect transistors, for example, so-called metal-insulator-semiconductor structures,
As shown in Figure 1a, the most effective protection device for preventing dielectric breakdown of the MISFET gate is to connect the gate input to FET Q ₂ , which should be gate protected, to the drain of depletion type FET Q ₁ . Connect D ₁ to input A, gate G ₁ and source
This is realized on a semiconductor substrate 11 of one conductivity type having an oxide film 10 on the surface, as shown in FIG. _1b , and is protected here. The gate insulating film GI ₁ of the FET Q ₁ is formed thicker than the gate insulating film GI ₂ of the FET Q ₂ to be used. The technology shown in Figure 1 was published in Japanese Unexamined Patent Application Publication No. 1973-
This is proposed in Publication No. 54778.

In this way, if an abnormal voltage is applied to the drain D ₁ side of FET Q ₁ , the back gate of this FET Q ₁ will be pulled, and if a voltage above a certain level is applied to input A, FET Q ₁ will finally be cut off. become. However, when a waveform with a very sharp rise is input, this input waveform punches through between the source S ₁ and drain D ₁ of FET Q ₁ and passes through FET Q _2.
The gate insulating film GI ₂ will be destroyed. Also, as a configuration that takes into account the above-mentioned punch-through, see Figure 2a.
Input A and depletion transistor as shown in
There is a circuit in which a resistor R is inserted between the drain of _Q3 . This circuit is realized as shown in Figure 2b,
We considered increasing the resistance R by lengthening the drain _D3 region of FET _Q3 . Here, depletion type FET Q ₃ gate sag membrane GI ₃ is FET
It is formed to have approximately the same thickness as the gate insulating film GI ₄ of Q ₄ . In this case, depression
The input waveform will be applied between the drain and gate of FET Q ₃ , but the only element to protect the gate of FET Q ₃ is the resistor R connected in series with the input, so the gate protection effect is not that great. is not obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having an improved gate protection function for protecting internal gate circuits from abnormal voltages at input terminals.

The present invention is characterized in that the gate of the first insulated gate field effect transistor to be protected provided on the semiconductor substrate operates in a depletion mode and is cut off when the input voltage exceeds a predetermined value; A gate electrode and a source or drain electrode of a second insulated gate field effect transistor having a gate insulating film thicker than the gate insulating film of the gate field effect transistor are connected in common, and the second insulated gate field effect transistor provided on the semiconductor substrate is selectively increasing the substrate impurity concentration only under the channel of the second insulated gate field effect transistor, extending the drain or source diffusion layer of the second insulated gate field effect transistor to form a resistor there; The semiconductor device is connected to an input terminal via the resistor, and the resistor prevents punch-through of the second insulated gate field effect transistor due to a sudden change in the input waveform.

Next, the technology related to the present invention will be explained with reference to FIGS. 4a and 4b. As shown in Figure 4a, the resistance R
and a depletion type FET whose gate and source are connected in common and whose drain is connected to one end of the resistor R.
_Q5 , and a diode D between this contact and the board, and input A is applied to the other end of the resistor R.
FET Q ₆ receives gate input from the source of FET Q ₅ . Here, the gate insulating film of FET _Q5 is made thicker than the gate insulating film of FET _Q6 . FIG. 4b shows a case where this semiconductor device is realized on an N-type semiconductor substrate 11.

It can be seen that the gate insulating film GI ₅ of FET Q ₅ is thicker than the gate insulating film GI ₆ of Q ₆ . According to this configuration, input A is connected to FET Q ₅ via resistor R.
This area D ₅ because it is connected to the drain D ₅ of
A sudden change in the input waveform is absorbed by the resistance component and the capacitance between the substrate and the breakdown of junction D on the drain side of _Q5 , and punch-through of FET _Q5 is prevented.

FIG. 3 shows the relationship between V _T and back gate voltage V _BG of FET Q ₁ in FIG. 1 and FET Q ₃ in FIG. 2. The FET used here is P-type MIS
FET Q ₁ is gate insulating film GI ₁ 3500Å FET
The data is when the gate insulating film GI ₃ of Q ₃ is 1000 Å. It can be seen from this graph that the thicker the gate insulating film is, the more rapidly the gate is cut off when the back gate voltage is applied. This is also clear from the equation below.

Here, Co=EoxEo/tox (tox=gate thickness, V _BG = back gate voltage) Therefore, V _T =V _T (BG=0) −Ktox√｜2 _F ｜+ _BG …(2) Here, K is proportional Constant It can be seen from the above equation that the thicker the gate film, the steeper the slope of the graph becomes.

In this way, thick gate insulating film such as FET Q ₃
FETs have a fairly high cut-off voltage and
As with FET Q ₁ , the thinner the gate insulating film is, the lower the cut-off voltage is and the more rapid the change.Also, input A is connected to the internal gate circuit via FET Q ₅ , which has the characteristic of abruptly cutting off when back gate voltage is applied. , by setting the cutoff point of FET Q ₅ below the dielectric strength voltage of the gate insulating film.
When the source potential of FET Q ₅ becomes abnormally high, it is immediately cut off and the internal gate circuit is isolated from the input terminal to protect it.

Next, an embodiment of the present invention will be described with reference to FIG.
This embodiment has the same circuit configuration as shown in _FIG . It has been made darker by In other words, by increasing the value of the term Nsub in equation (1), the cutoff characteristics are improved and a more complete input protection effect is obtained.

As described in detail above, according to the present invention, there is an MIS FET that normally operates in depletion mode and is cut off when the input voltage exceeds a predetermined level before the internal gate circuit to be protected;
Since there is an input terminal across the resistive element from the drain side of the FET, the gate circuit to be protected is always protected from abnormal input. Furthermore, it goes without saying that the present invention is not limited to P-channel FETs, but can be similarly applied to N-channel FETs.

[Brief explanation of the drawing]

Figures 1a and 1b show conventional semiconductor devices;
Figure a shows the circuit, and Figure 1b shows its cross-sectional structure. FIG. 2a is a circuit diagram showing a semiconductor device having another conceivable input protection means, and FIG. 2b is a diagram showing its cross-sectional structure. Figure 3 is a diagram showing the relationship between V _T and back gate voltage of MIS FETs with different gate film thicknesses. FIG. 4a is a circuit diagram showing a semiconductor device related to the present invention, and FIG. 4b is a sectional view of the semiconductor device. FIG. 5 is a sectional view showing an embodiment of the present invention. In the figure, Q ₁ and Q ₅ are depletion type MIS FETs with thick gate films, and Q ₃ is a depletion type MIS FET with a gate film that is the same as the internal gate circuit.
MIS FET, Q ₂ , Q ₄ , Q ₆ are internal gate circuit transistors, D is a diode, and R is a resistor.

Claims (1)

[Claims] 1 The gate of the first insulated gate field effect transistor to be protected provided on the semiconductor substrate operates in depletion mode and is cut off when the input voltage exceeds a predetermined value, and the first insulated gate field effect transistor The gate electrode and the source or drain electrode of a second insulated gate field effect transistor having a gate insulating film thicker than the thickness of the gate insulating film of the second insulated gate field effect transistor provided on the semiconductor substrate are connected in common. selectively increasing the substrate impurity concentration only under the channel of the field effect transistor, extending the drain or source diffusion layer of the second insulated gate field effect transistor to form a resistor there; A semiconductor device connected to an input terminal, wherein the resistor prevents punch-through of the second insulated gate field effect transistor due to a sudden change in an input waveform.