JPS6341951A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve convenience in use by making it possible to select function as a watchdog timer is to be given to a timer circuit or not only when a power source is made on. CONSTITUTION:A timer overflow signal TOF outputted from a timer circuit 8 is outputted to an OR gate 3 through an AND gate 8 and becomes an initial set signal IRS only when a high level watchdog enable signal WENE is outputted from a flip-flop 7, that is, when a high level watchdog function selection signal WDSE is generated and given to an AND gate 6 while a power on flag POF is set ('1') and a power on flag signal POF, output of a power on flag generating circuit 5, is high level. In other words, a timer circuit 9 functions as a watchdog timer only when the flip-flop 7 is in a set state. Selection as to whether the watchdog function is to be used or not is made possible only just after a power source is made on. In case the watchdog fuction is not used, the timer circuit can be used for other purpose without any restriction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer equipped with a watchdog function, that is, a function for escaping from a program runaway state or an infinite loop.

[Prior art]

In microcomputer systems, users often create and use programs themselves. When using such a program created by the user himself/herself, the program is likely to run out of control due to the presence of a bug, or an infinite loop may occur due to inappropriate loop release conditions. Therefore, if the entire program or the processing of each block of the program is not completed within a predetermined time, it is assumed that the program has gone out of control or an infinite loop has occurred, and a signal is output to initialize the entire system. Microcomputers equipped with a watchdog function that generates a non-maskable interrupt signal that causes a jump to a predetermined step or a jump to a predetermined step are becoming popular.

[Problem that the invention seeks to solve]

By the way, a conventional microcomputer having a watchdog function is equipped with a timer circuit dedicated to this function, that is, a watchdog timer.

This watchdog timer is set at the start of execution of the entire program or each block into which the program is divided as appropriate, and is reset at the end of execution. In this case, an initial reset signal or a non-maskable interrupt signal was generated, which was used to stop the program from running out of control and escape from the infinite loop. Therefore, if the watchdog function is not used, the watchdog timer is wasted, which is uneconomical.

As a measure to avoid such waste, it is possible to configure the evening/timer circuit so that it can be switched by software to multiple uses, including the function as a watchdog timer, for example.

However, if a configuration is adopted in which the timer circuit can be switched from the watchdog timer to another use by such a program, there is a possibility that the program runs out of control and the timer circuit is switched from the watchdog timer to another use. Therefore, when using the watchdog function,
If the program goes out of control and the timer circuit used as a watchdog timer is used for other purposes, the watchdog function becomes completely meaningless.

As another method, for example, once the timer circuit is set to be used as a one-stop timer, it may be configured such that it cannot be switched to other uses by a program.

However, such a configuration in which special regulations are provided for the operation of the timer circuit makes the timer circuit less convenient to use, and also tends to cause various problems during programming and debugging.

The present invention has been made in view of the above circumstances, and is intended to prevent a timer circuit used as a watchdog timer from ceasing to function as a watchdog timer when a program runs out of control, and to prevent a timer circuit used as a watchdog timer from failing to function as a watchdog timer when a program runs out of control. The purpose of the present invention is to provide a microcomputer whose timer circuit can be used freely for other purposes if the timer circuit is not used.

[Means for solving problems]

In the present invention, an initial reset signal that resets the entire device to its initial state is set by a power-on clear circuit that generates when the power is turned on, and an initial reset signal that is generated by the power-on clear circuit, and is set by the time the program starts executing. a circuit for outputting a watchdog selection signal only while the power-on flag is in the set state; A circuit that outputs a watchdog enable signal that destroys the timer circuit as a watchdog timer that generates an overflow signal when a program processing time is longer than a predetermined time by receiving a watchdog selection signal from the circuit. It is characterized by having the following.

[Effect]

In the microcomputer of the present invention, it is possible to select whether or not to use the watchdog function only immediately after power is turned on, and when the watchdog function is not used, the timer circuit can be used for other purposes without any restrictions. It is.

[Example] Hereinafter, the present invention will be described in detail based on drawings showing examples thereof.

FIG. 1 is a block diagram showing the configuration of essential parts of a microcomputer according to the present invention.

In the figure, 1 is an M8 source line, to which a power supply voltage Vcc is applied.

Reference numeral 2 denotes a manually operated and automatically reset type initial reset whose one end is connected to the power supply line 1, and the other end is connected to the first input terminal of the OR gate 3. Therefore, when the initial reset switch 2 is turned on, a pulse signal of the power supply voltage VCC is outputted via the OR gate 3 as the initial reset signal IR3.

In the figure, reference numeral 4 denotes a power-on clear circuit, which outputs a power-on clear signal POC of no return to the second input terminal of the OR gate 3 when the main switch of the device of the present invention is turned on. Note that the power-on clear signal POC given to this OR gate 3 is the initial reset signal IR.
5 from the OR gate 3. Further, this power-on clear signal POC is applied to the set terminals S and R-S of the power-on flag generating circuit 5, which is an R-S flip-flop.
It is applied to the reset terminal R of the flip-flop 7.

The power-on flag generating circuit 5 is an R-S flip-flop as described above, and its set terminal S receives the power-on clear signal POC, which is the output of the power-on clear circuit 4, and its reset terminal R receives the POF reset signal. , the output terminal Q is connected to the first input terminal of the AND gate 6 and the power-on flag signal output gate 10.

Therefore, when the power-on clearing qpoc is output from the power-on clear circuit 4, the power-on flag generating circuit 5 is set (in other words, the power-on flag PO
(F is set), the power-on flag signal 5POF, which is the output of its output terminal Q, changes to a high level. In addition, once it is read that the power-on flag POF is set (“do”) in the initial routine at the start of program execution, the POF reset signal RP goes high.
OF is generated and applied to the reset terminal R of the power-on flag generating circuit 5. As a result, the power-on flag generating circuit 5 is reset, and the power-on flag signal 5POF output from its output terminal Q changes to a low level.

The AND gate 6 has one input terminal supplied with the power-on flag signal 5POF, which is the output of the power-on flag generation circuit 5, as described above, and the other input terminal supplied with the watchdog function selection signal WDSE. , the output terminal is connected to the set terminal S of the flip-flop 7.

Therefore, the AND gate 6 selects the high-level watchdog function only while the high-level power-on flag signal 5POF is applied, in other words, only while the power-on flag POF is set (“1”). Signal-D
SE is output to the set terminal S of the flip-flop 7.

As mentioned above, the flip-flop 7 has its set terminal S
is supplied with the watchdog function selection signal WDSE through the AND gate 6, the power-on clear signal poc which is the output of the power-on clear circuit 4 is supplied to the reset terminal R, and the output terminal Q is supplied with one of the AND gates 8. connected to the input terminal.

Therefore, the watchdog function selection signal -〇S is at a high level only while the power-on flag signal 5POF output from the power-on flag generating circuit 5 is at a high level.
When E is input, a high level signal (watchdog function selection signal -○SF) is applied from the AND gate 6 to the set terminal S of the clip-flop 7, and the flip-flop 7 is set.

As a result, the high level watchdog enable signal WENE is output from the output terminal Q of the flip-flop 7.

The output of the clip-flop 7, that is, the watchdog enable signal -ENE, is applied to one input terminal of the NO gate 8 as described above, but the output of the flip-flop 7 is set to a high level at the warp set terminal R. When the signal POC is given, specifically, only when the power-on clear signal POC is output from the power-on clear circuit 4, the flip-flop 7 remains in the set state while the power is continuously turned on. will continue.

Reference numeral 9 in the figure is a timer circuit, and it is possible to set a time value by a setting circuit (not shown), and when the time measurement of the set time value is completed, a high level timer overflow signal TOF is sent to the above-mentioned AND It is output to the other input terminal of gate 8. The output of the AND gate 8 is connected to the third input terminal of the aforementioned OR gate 3.

Therefore, the timer overflow signal TOF output from the timer circuit 8 does not set the hit power-on flag POF when the high-level watchdog enable signal -ENE is output from the flip-flop 7.
AND only when a high-level watchdog function selection signal WDSE is generated and applied to the AND gate 6 while the power-on flag signal POF, which is the output of the power-on flag generating circuit 5, is at a high level. It is output to the OR gate 3 via the gate 8 and becomes the initial reset signal IR5. In other words, the timer circuit 9 functions as a watchdog timer only when the flip-flop 7 is in the set state.

Note that the gate 10 is a gate for outputting the power-on flag signal 5POF to the lotus 11.

The operation of the microcomputer of the present invention having the above configuration will be described below with reference to the timing charts of FIGS. 2 and 3.

When the watchdog function is selected, it operates according to the timing chart shown in FIG.

First, when the power is turned on (al power-on clear circuit 4 outputs a high-level power-on clear signal POC fbl, this is output as an initial reset signal IR3 through OR gate 3 fcl, and a power-on flag is generated. Since the power-on flag signal 5POF is applied to the seventh node terminal S of the circuit 5 and sets the power-on flag generating circuit 5, the power-on flag signal 5POF changes to high level (d), and the flip-flop 7 is also initially reset. While the flag signal 5POF maintains the high level, the high level watchdog function selection signal -[
) SE is applied, tel, AND gate 6 output changes to high level, flip-flop 7 is set, high level watchdog enable signal WEN^ is outputted, and inputted to one input terminal of AND gate 8. Ru ifl.

Then, for example, when the program starts executing and in its initial routine, the power-on flag signal 5PO is activated.
F is at a high level, that is, the power-on flag PO
When the set state of F is read, the POF reset signal R
POF is generated and applied to the reset +-a terminal R of the power-on flag generation circuit 5 (fg), thereby resetting the power-on flag generation circuit 5, that is, the power-on flag POF is reset (to "0"). However, since the flip-flop 7 maintains the safe state, the high-level watchdog enable signal -ENA is continuously output from its output terminal Q (f).
, whereby the timer circuit 9 functions as a watchdog timer.

By the way, when the execution of the program is started, the timer circuit 9 is set to a predetermined time and starts counting time. and,
The timer circuit 9 is reset when the entire program or each block obtained by appropriately dividing the program ends.

However, if a program runaway or an infinite loop occurs during program execution, the predetermined time measurement will be completed without this reset being performed. T.O.
fh) which outputs F to the other input terminal of AND gate 8.
. At this time, as described above, one input terminal of the AND gate 8 is supplied with a high-level watch tong enable signal -E.
Since NA is applied, the output of AND gate 8 changes to high level and is applied to the third input terminal of OR gate 3. As a result, the OR gate 3 outputs a high level initial reset IR3 (tel from which No. 3 is output).

Note that, of course, when the initial reset switch 2 is turned on, the initial reset signal IR3 is also output from the OR gate 3 to fi+ (C).

On the other hand, if the watchdog function is not selected, the third
It operates according to the timing chart shown in the figure. That is, when the watchdog function is not selected, the high-level watchdog function selection signal -0SE is not generated, so the flip-flop 7 is not set, and therefore the high-level watchdog enable signal -EN is not generated.
A is also not output (f). Therefore, if a situation occurs in which a high level signal is output from the timer circuit 9, the timer overflow signal T is sent to the NO gate 8.
Even if it is given as OF, the AND gate 8 output maintains a low level, so the initial reset signal IR3 is not output from the OR gate 3 (c+
.

In the above embodiment, when the timer circuit 9 as a watchdog timer outputs an overflow signal, the initial reset signal IRS is generated.
Of course, a configuration may also be used in which an interrupt signal is output to cause the execution of the program to jump to a predetermined step.

〔effect〕

As described above, in the present invention, it is possible to select whether or not to give the #R setting as a watchdog timer to the timer circuit only when the power is turned on. Therefore, when the watchdog function is selected, even if the program The timer circuit reliably maintains its function as a watchdog timer even in the event of a runaway, and if the watchdog function is not selected, programming or debugging is possible without having to consider the timer circuit's function as a watchdog timer. etc., thereby realizing a microcomputer with a watchdog function that is extremely easy to use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of essential parts of a microcomputer according to the present invention, and FIGS. 2 and 3 are timing charts for explaining its operation. 2... Initial reset switch 4... Power-on clear circuit 5... Power-on flag generation circuit 6... AND gate 7... Flip-flop 9... Timer circuit

Claims (1)

[Scope of Claims] 1. A power-on clear circuit that generates an initial reset signal that resets the entire device to its initial state when the power is turned on; and a power-on clear circuit that is set by the initial reset signal generated by the power-on clear circuit to start program execution. A circuit for outputting a watchdog selection signal only while the power-on flag is in a set state; , a circuit that outputs a watchdog enable signal that causes the timer circuit to function as a watchdog timer that generates an overflow signal when a program processing time is longer than a predetermined time when a watchdog selection signal is applied from the circuit; A microcomputer characterized by being equipped with.