JPS6341210B2 - - Google Patents
Info
- Publication number
- JPS6341210B2 JPS6341210B2 JP57075165A JP7516582A JPS6341210B2 JP S6341210 B2 JPS6341210 B2 JP S6341210B2 JP 57075165 A JP57075165 A JP 57075165A JP 7516582 A JP7516582 A JP 7516582A JP S6341210 B2 JPS6341210 B2 JP S6341210B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- amorphous silicon
- layer
- temperature
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000000758 substrate Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 34
- 239000013078 crystal Substances 0.000 claims description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 16
- 239000007790 solid phase Substances 0.000 claims description 12
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 8
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002425 crystallisation Methods 0.000 claims description 2
- 230000008025 crystallization Effects 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 238000000137 annealing Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000001947 vapour-phase growth Methods 0.000 description 7
- 229910052786 argon Inorganic materials 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- -1 for example Chemical compound 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は単結晶半導体基板上あるいはその表面
の一部に絶縁物層を形成した単結晶半導体基板上
に気相成長法を用いて非晶質半導体層を形成した
エピタキシヤル成長させることにより単結晶化す
る半導体装置の製造方法に関するものである。Detailed Description of the Invention The present invention relates to an epitaxy method in which an amorphous semiconductor layer is formed using a vapor phase growth method on a single crystal semiconductor substrate or a single crystal semiconductor substrate on which an insulating layer is formed on a part of the surface of the single crystal semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device which is made into a single crystal by double crystal growth.
従来、気相成長法を用いて単結晶半導体基板上
に非晶質半導体シリコン層を形成し、エピタキシ
ヤル成長させることにより単結晶化した半導体装
置の製造方法としては、高温処理を用いたいくつ
かの方法が提案されていた。 Conventionally, there are several methods for manufacturing semiconductor devices that use high-temperature processing, in which an amorphous semiconductor silicon layer is formed on a single-crystal semiconductor substrate using a vapor phase growth method, and then made into a single crystal by epitaxial growth. method was proposed.
その１つは、高温固相成長法である。この従来
法は、単結晶シリコン基板あるいはその表面の一
部に絶縁物層を形成した単結晶シリコン基板を
650℃以下の温度に加熱した後、シランガスを熱
分解して基板上に非晶質シリコン層を形成し、こ
れを1100℃以上の高温に加熱することによつて固
相成長させ単結晶化する方法である。この従来法
においては、非晶質シリコン層堆積前に単結晶シ
リコン基板表面の自然酸化膜を除去していないた
め、熱処理の初期段階で非晶質シリコン層が固相
エピタキシヤル成長せずに多結晶化してしまい、
1100℃以上の高温でも固相成長速度が遅く、また
単結晶化した部分の結晶性も悪くなるという欠点
があつた。また高温加熱のため絶縁物層上の非晶
質シリコン層が多結晶化してしまい、絶縁物層上
の非晶質シリコン層はほとんど固相エピタキシヤ
ル成長しないという欠点もあつた。 One of them is high temperature solid phase growth. This conventional method uses a single crystal silicon substrate or a single crystal silicon substrate with an insulating layer formed on a part of its surface.
After heating to a temperature of 650℃ or less, silane gas is thermally decomposed to form an amorphous silicon layer on the substrate, which is then heated to a high temperature of 1100℃ or higher to grow in solid phase and become a single crystal. It's a method. In this conventional method, the natural oxide film on the surface of the single-crystal silicon substrate is not removed before depositing the amorphous silicon layer, so the amorphous silicon layer does not undergo solid-phase epitaxial growth in the early stage of heat treatment. It crystallizes,
The disadvantage was that the solid phase growth rate was slow even at high temperatures of 1100°C or higher, and the crystallinity of the single crystallized portion was also poor. Another drawback was that the amorphous silicon layer on the insulating layer became polycrystalline due to high-temperature heating, and the amorphous silicon layer on the insulating layer hardly grew solid-phase epitaxially.
これらの欠点を除去するために、溶融成長法も
用いられていた。これは上記方法と同様に形成し
た単結晶シリコン基板あるいはその表面の一部に
絶縁物層を形成した単結晶シリコン基板上の非晶
質シリコン層にレーザービーム又は電子ビームを
照射することにより融点以上の高温に加熱し、溶
融した非晶質シリコンが固化する際に液相エピタ
キシヤル成長させ単結晶化する方法である。この
方法によれば、単結晶基板および絶縁物層上に比
較的良質の単結晶層が得られるが、溶融時に表面
形状が乱れるという欠点があつた。 Melt growth methods have also been used to eliminate these drawbacks. This is achieved by irradiating a laser beam or an electron beam onto a single crystal silicon substrate formed in the same way as the above method or an amorphous silicon layer on a single crystal silicon substrate with an insulating layer formed on a part of its surface. In this method, the molten amorphous silicon is heated to a high temperature, and when the molten amorphous silicon solidifies, liquid phase epitaxial growth is performed to form a single crystal. According to this method, a relatively good quality single crystal layer can be obtained on the single crystal substrate and the insulating layer, but it has the disadvantage that the surface shape is disturbed during melting.
このように従来法では、気相成長法により形成
した非晶質半導体層から結晶性の良く表面形状の
乱れのない単結晶層を形成した半導体装置を製造
することが困難であつた。 As described above, with the conventional method, it has been difficult to manufacture a semiconductor device in which a single crystal layer with good crystallinity and no disturbance in surface shape is formed from an amorphous semiconductor layer formed by vapor phase growth.
本発明はこれらの欠点を除去するため、単結晶
半導体基板または一部表面に絶縁物層を形成した
単結晶半導体基板の露出している表面を清浄な状
態にした後、気相成長法により非晶質半導体層を
形成し、アニールによつて固相エピタキシヤル成
長させることを特徴とするもので、その目的は結
晶性がすぐれ表面形状の乱れのない単結晶半導体
層を単結晶半導体基板または絶縁物層上に形成す
ることにある。 In order to eliminate these drawbacks, the present invention cleans the exposed surface of a single-crystal semiconductor substrate or a single-crystal semiconductor substrate with an insulating layer formed on a portion of the surface, and then decomposes it by vapor phase growth. It is characterized by forming a crystalline semiconductor layer and growing it solid-phase epitaxially by annealing.The purpose is to grow a single-crystal semiconductor layer with excellent crystallinity and no disturbance in surface shape onto a single-crystal semiconductor substrate or an insulator. The purpose is to form on the material layer.
前記の目的を達成するため、本発明は水素雰囲
気中での高温熱処理により単結晶半導体基板表面
の自然酸化膜を除去する工程と、次に、堆積せん
とする非晶質シリコン層が結晶化しない温度に達
するまで塩化水素を導入して前記単結晶半導体基
板表面の清浄表面を保つ工程と、次に、非晶質シ
リコン層を結晶化しない温度で堆積する工程と、
前記非晶質シリコン層を固相エピタキシヤル成長
させる工程を含むことを特徴とする半導体装置の
製造方法を発明の要旨とする。 In order to achieve the above object, the present invention includes a step of removing a natural oxide film on the surface of a single crystal semiconductor substrate by high-temperature heat treatment in a hydrogen atmosphere, and then removing the amorphous silicon layer to be deposited to prevent crystallization. A step of introducing hydrogen chloride to maintain a clean surface of the single crystal semiconductor substrate until reaching a temperature, and then a step of depositing an amorphous silicon layer at a temperature that does not crystallize it.
The gist of the invention is a method for manufacturing a semiconductor device, which includes a step of solid-phase epitaxial growth of the amorphous silicon layer.
次に本発明の実施例を添附図面について説明す
る。なお実施例は一つの例示であつて、本発明の
精神を逸脱しない範囲内で、種々の変更あるいは
改良を行いうることは云うまでもない。 Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.
第１図は本発明の実施例を示す。図において、
１は単結晶シリコン基板、２は絶縁物層、３ａは
非晶質シリコン層、３ｂ，３ｃは単結晶シリコン
層である。まず単結晶半導体基板として第１図Ａ
に示すような単結晶シリコン基板１を用いる。次
に第１図Ｂに示すような絶縁物層（例えば酸化シ
リコン、窒化シリコン）２を単結晶シリコン基板
１の一部表面に形成する。次に非晶質半導体とし
て非晶質シリコン３ａを清浄な基板表面上に堆積
する。まず前記基板を非晶質シリコン堆積用反応
炉に入れ、高純度の水素雰囲気中で基板を1100℃
に加熱し、シリコン表面の自然酸化膜を除去す
る。 FIG. 1 shows an embodiment of the invention. In the figure,
1 is a single crystal silicon substrate, 2 is an insulating layer, 3a is an amorphous silicon layer, and 3b and 3c are single crystal silicon layers. First, as a single crystal semiconductor substrate, as shown in FIG.
A single crystal silicon substrate 1 as shown in FIG. 1 is used. Next, an insulating layer 2 (for example, silicon oxide, silicon nitride) as shown in FIG. 1B is formed on a portion of the surface of the single crystal silicon substrate 1. Next, amorphous silicon 3a is deposited as an amorphous semiconductor on the clean substrate surface. First, the substrate was placed in a reactor for amorphous silicon deposition, and the substrate was heated to 1100°C in a high-purity hydrogen atmosphere.
to remove the natural oxide film on the silicon surface.
シリコン表面の自然酸化膜を除去した後、良質
な非晶質シリコンが堆積可能な600℃以下の温度
までシリコン基板を冷却する（600℃以上では単
結晶半導体となつてしまう）。その際にシリコン
表面が雰囲気中の不純物によつて再び汚染されな
いため、本発明では第２図のような塩化水素によ
るシリコンのエツチング効果を用いる。 After removing the natural oxide film on the silicon surface, the silicon substrate is cooled to a temperature below 600°C at which high-quality amorphous silicon can be deposited (at temperatures above 600°C, it becomes a single crystal semiconductor). At this time, the silicon surface is not contaminated again by impurities in the atmosphere, so in the present invention, the silicon etching effect by hydrogen chloride as shown in FIG. 2 is used.
第２図は、横軸に試料温度をとり、縦軸に各種
ガスによるエツチング速度をプロツトしたもので
ある。４はアルゴン希釈塩化水素0.5％、５はア
ルゴン希釈塩化水素0.1％、６は水素ガスによる
シリコンのエツチング速度を表す。以上のエツチ
ング速度は、当該の温度におけるエツチングに先
立つて水素雰囲気中で1100℃以上に加熱し、自然
酸化膜を除去した上で求めた値である。これに対
して７は自然酸化膜を除去しない場合のアルゴン
希釈塩化水素0.1％によるエツチング速度であり、
その値は自然酸化膜を除去した場合に比べ著しく
減少している。第２図からわかるように水素雰囲
気で加熱し、自然酸化膜を除去した後、塩化水素
を含む雰囲気中たとえばアルゴン希釈塩化水素
0.1％雰囲気中で冷却すれば600℃以下の温度でも
清浄なシリコン表面を形成できる。 FIG. 2 plots the sample temperature on the horizontal axis and the etching rate with various gases on the vertical axis. 4 represents argon diluted hydrogen chloride 0.5%, 5 represents argon diluted hydrogen chloride 0.1%, and 6 represents the etching rate of silicon with hydrogen gas. The above etching rates were determined after heating to 1100° C. or higher in a hydrogen atmosphere to remove the natural oxide film prior to etching at the relevant temperature. On the other hand, 7 is the etching rate with 0.1% hydrogen chloride diluted with argon when the native oxide film is not removed.
The value is significantly reduced compared to the case where the native oxide film is removed. As can be seen from Figure 2, after heating in a hydrogen atmosphere to remove the natural oxide film, in an atmosphere containing hydrogen chloride, for example, hydrogen chloride diluted with argon.
By cooling in a 0.1% atmosphere, a clean silicon surface can be formed even at temperatures below 600°C.
その後第１図Ｃのように600℃以下の温度たと
えば550℃で非晶質シリコン層３を気相成長させ
る。気相成長はたとえばアルゴン希釈シランの熱
分解により非晶質シリコンを成長させる。600℃
以下で気相成長を行なうことにより、膜中に微結
晶を含まない良質な非晶質シリコン膜をシリコン
基板上に及び絶縁物層上に形成できる。これによ
り固相エピタキシヤル成長後の結晶性を良好なも
のにすることができる。その後適当な温度例えば
600℃で非晶質シリコン層３ａをアニールし固相
エピタキシヤル成長させ第１図Ｄに示すように単
結晶シリコン層３ｂにする。アニールを低温で行
なえば、基板１と単結晶シリコン層３ｂの間に不
純物濃度分布を形成する場合急峻な分布を形成す
ることができる。不純物濃度分布はあらかじめ基
板に不純物を含ませたり、気相成長時に非晶質シ
リコンに不純物を含ませることにより形成でき
る。 Thereafter, as shown in FIG. 1C, an amorphous silicon layer 3 is grown in a vapor phase at a temperature below 600 DEG C., for example, 550 DEG C. In vapor phase growth, for example, amorphous silicon is grown by thermal decomposition of silane diluted with argon. 600℃
By performing vapor phase growth below, a high-quality amorphous silicon film containing no microcrystals can be formed on the silicon substrate and on the insulating layer. This makes it possible to improve the crystallinity after solid phase epitaxial growth. Then set the appropriate temperature e.g.
The amorphous silicon layer 3a is annealed at 600° C. and solid-phase epitaxially grown to form a single crystal silicon layer 3b as shown in FIG. 1D. If annealing is performed at a low temperature, a steep impurity concentration distribution can be formed between the substrate 1 and the single crystal silicon layer 3b. The impurity concentration distribution can be formed by including impurities in the substrate in advance or by including impurities in amorphous silicon during vapor phase growth.
第３図は本発明の他の実施例を示すもので、第
１実施例における絶縁物層を形成せずに行う場合
を示すもので、第３図Ａ，Ｂ，Ｃの工程は第１図
Ｂ，Ｃ，Ｄの各工程と同じように行われるもので
ある。 FIG. 3 shows another embodiment of the present invention, in which the steps in the first embodiment are carried out without forming an insulating layer, and the steps in FIGS. 3A, B, and C are similar to those in FIG. 1. This step is carried out in the same manner as steps B, C, and D.
本発明については、単結晶シリコン基板および
絶縁物層上の単結晶シリコン層の反射電子線回折
像によつて結晶性を調べたところこの回折像は菊
池パターンと呼ばれる回折像を含んでおり結晶性
が良好であることが認められた。 Regarding the present invention, the crystallinity was investigated using reflected electron beam diffraction images of the single crystal silicon substrate and the single crystal silicon layer on the insulator layer. was found to be good.
なお、本発明において形成した清浄なシリコン
基板表面上の非晶質シリコン層の場合アニール時
にレーザービーム、電子ビーム、高エネルギー粒
子ビーム及び赤外線アニール等を用いた融点以下
の高温加熱を行なつても非晶質シリコン層が多結
晶化する以前に固相エピタキシヤル成長するため
これらのアニール法も適用可能であり、アニール
時間を短縮することができる。 In addition, in the case of the amorphous silicon layer formed on the surface of a clean silicon substrate formed in the present invention, even if high-temperature heating below the melting point is performed using a laser beam, electron beam, high-energy particle beam, infrared annealing, etc. during annealing. Since solid-phase epitaxial growth occurs before the amorphous silicon layer becomes polycrystalline, these annealing methods can also be applied, and the annealing time can be shortened.
その後単結晶半導体層３ｂの一部を除去又は絶
縁物化することにより第１図Ｅに示したように単
結晶シリコン層３ｃを基板１と完全に絶縁分離す
ることができる。 Thereafter, by removing a portion of the single crystal semiconductor layer 3b or converting it into an insulator, the single crystal silicon layer 3c can be completely isolated from the substrate 1 as shown in FIG. 1E.
以上説明したように、本発明を用いれば単結晶
半導体層を単結晶半導体基板上に低温で、あるい
はビーム・アニールによれば非常に短時間で形成
できるので、不純物の拡散による分布のダレのな
い急峻な不純物濃度分布を単結晶半導体基板と単
結晶半導体層の間に形成することができる利点が
ある。また本発明を用いれば絶縁物層上に固相エ
ピタキシヤル成長により単結晶半導体層を形成で
きるので、
(イ) 単結晶半導体層を単結晶半導体基板と完全に
絶縁分離できる。 As explained above, by using the present invention, a single-crystal semiconductor layer can be formed on a single-crystal semiconductor substrate at a low temperature or in a very short time by beam annealing, so there is no sag in the distribution due to impurity diffusion. There is an advantage that a steep impurity concentration distribution can be formed between the single crystal semiconductor substrate and the single crystal semiconductor layer. Furthermore, according to the present invention, a single crystal semiconductor layer can be formed on an insulating layer by solid-phase epitaxial growth, so (a) the single crystal semiconductor layer can be completely insulated and separated from the single crystal semiconductor substrate.
(ロ) 単結晶がすぐれかつ表面形状の乱れのない単
結晶半導体層が形成できる。(b) A single crystal semiconductor layer with excellent single crystal structure and no disturbance in surface shape can be formed.
等の利点がある。There are advantages such as
第１図Ａ〜Ｅは本発明による半導体装置の製造
方法の概略、第２図は各種ガスによるシリコンの
エツチング速度、第３図Ａ〜Ｃは本発明の他の実
施例を示す。
１……単結晶シリコン基板、２……絶縁物層、
３ａ……非晶質シリコン層、３ｂ，３ｃ……単結
晶シリコン層。
1A to 1E schematically show a method for manufacturing a semiconductor device according to the present invention, FIG. 2 shows the etching rate of silicon using various gases, and FIGS. 3A to 3C show another embodiment of the present invention. 1... Single crystal silicon substrate, 2... Insulator layer,
3a...Amorphous silicon layer, 3b, 3c...Single crystal silicon layer.
Claims (1)
導体基板表面の自然酸化膜を除去する工程と、次
に、堆積せんとする非晶質シリコン層が結晶化し
ない温度に達するまで塩化水素を導入して前記単
結晶半導体基板表面の清浄表面を保つ工程と、次
に、非晶質シリコン層を結晶化しない温度で堆積
する工程と、前記非晶質シリコン層を固相エピタ
キシヤル成長させる工程を含むことを特徴とする
半導体装置の製造方法。1. A step of removing the native oxide film on the surface of the single crystal semiconductor substrate by high-temperature heat treatment in a hydrogen atmosphere, and then introducing hydrogen chloride until the temperature reaches a temperature at which the amorphous silicon layer to be deposited does not crystallize. The method includes a step of maintaining a clean surface of the single crystal semiconductor substrate, a step of depositing an amorphous silicon layer at a temperature that does not cause crystallization, and a step of growing the amorphous silicon layer by solid phase epitaxial growth. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57075165A JPS58192320A (en) | 1982-05-07 | 1982-05-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57075165A JPS58192320A (en) | 1982-05-07 | 1982-05-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58192320A JPS58192320A (en) | 1983-11-09 |
| JPS6341210B2 true JPS6341210B2 (en) | 1988-08-16 |
Family
ID=13568311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57075165A Granted JPS58192320A (en) | 1982-05-07 | 1982-05-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58192320A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2689985B2 (en) * | 1988-05-30 | 1997-12-10 | 富士通株式会社 | Semiconductor device manufacturing method and manufacturing apparatus |
| CN1879204B (en) * | 2003-12-03 | 2010-07-14 | S.O.I.Tec绝缘体上硅技术公司 | Process for improving the surface roughness of a wafer |
-
1982
- 1982-05-07 JP JP57075165A patent/JPS58192320A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58192320A (en) | 1983-11-09 |
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