JPS6340360A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a channel stopper reducing the pattern space by a method wherein adjoining two transistors out of multiple driving MOS transistors are overlapped each other on a channel region in the direction making a right angle with the current flowing direction. CONSTITUTION:Within a semiconductor device with a multiple layer gate electrode structure comprising a NOR circuit, a load MOS transistor 11, a control electrode 14 of TrQ12 and another control electrode 15 of TrQ13 i.e. at least two adjoining transistors out of multiple driving MOS Trs are overlapped on a channel region in the direction making a right angle with the current flowing direction. Through these procedures, a channel stopper can be eliminated to reduce the pattern space.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to pattern arrangement of a semiconductor NOR circuit having a multilayer gate electrode structure.

(Prior Art) Conventionally, as a technology in such a field, for example, the literature title [Introduction to VLSI System JP, 19-20 Baifukan;
Co-authored by C. Mead and L. Conway, translated and supervised by Takuo Kanno and Hiroyuki Sakaki.

The configuration will be explained below using figures.

FIG. 2 is a block diagram of such a conventional semiconductor device, and FIG. 2(a) is its equivalent circuit diagram, which has a NOR circuit configuration. No. 21m(b) is a plan view thereof, showing a planar layout pattern. Figure 2(c) is Figure 2(b)
FIG. 2 is a schematic cross-sectional view taken along line CC of

This NOR circuit consists of load MO5l - transistor QI, first
drive MO5) control electrode Qz of the transistor; and second drive MOS) control electrode Q of the transistor. The pattern arrangement is as shown in FIG. 2(b): the drain diffusion layer 1 of the transistor Q, the gate electrode 2 of the transistor Q1, and the transistor Q.

Source and transistor Qt, common drain 3 of Q3
, gate electrode 4 of transistor Q2, transistor Q.

The gate electrode 4 and the gate electrode 6 are arranged in parallel. Also, transistors Q2 and Q.

As shown in FIG. 2(c), between the gate electrode 4 of the transistor Q2 on the silicon substrate 10 and the transistor. The gate electrodes 6 of No. 3 are separated by a channel stopper 8 and an insulator 9.

(Problems to be Solved by the Invention) As described above, in the conventional device, the area of the channel stopper (including the isolation insulator 9) 8 portion is required, and in particular, as the density of LSI increases, In the current situation where fine pattern circuits are required, reducing the area thereof has been an issue.

An object of the present invention is to provide a semiconductor device having a multilayer gate electrode structure constituting a NOR circuit that can eliminate the above-mentioned channel stopper (including the isolation insulator) and reduce the pattern area.

(Means for Solving the Problems) In order to solve the above problems, the present invention solves the problems described above. lOS
) In a semiconductor device having a multilayer gate electrode structure that includes a transistor and a plurality of drive MOS transistors and constitutes an N011 circuit, the control electrodes of at least two adjacent transistors among the plurality of drive MOS transistors are arranged in the direction in which current flows. The structure is such that there is an overlap over the channel region in the direction perpendicular to the channel region.

(Function) According to the present invention, in a semiconductor device having a multilayer gate electrode structure constituting an N012 circuit, a plurality of drive MO5)
Since the lI control electrodes of at least two adjacent transistors among the transistors overlap on the channel region in the direction perpendicular to the direction of current flow, the channel separation region of the two driving MOS transistors, that is, By eliminating the channel stopper and the insulator, the circuit pattern area can be reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor device having a multilayer gate electrode structure constituting a NOR circuit according to the present invention, and FIG.
) is its equivalent circuit diagram, FIG. 1(b) is its top view, and
FIG. 1(c) is a sectional view taken along the line c--c of FIG. 1(b).

In the figure, 11 is the drain diffusion layer of the load MOS transistor Ql+, 12 is the gate electrode of the transistor Ql+, and 13 is the gate electrode of the transistor Ql+.
is the source diffusion layer (output) of the transistor Ql+, 14 is the first drive MO5) transistor, □ is the control electrode, 15
16 is a common source diffusion layer of transistors Q+z+Q++, 17 is a silicon substrate, and 18 is an isolation oxide film.

In this embodiment, as shown in FIG. 1(c), between the transistors QIZ and Qll, there is a channel stopper (separating insulator) which is a partitioning region, as shown in FIG. 2(c) described above. Since it does not have 8 (including 9), the area can be reduced accordingly.

This point will be explained in detail in comparison with the conventional example.

In the conventional method, as shown in FIG. 3, the actual gate electrode width Weff is reduced due to lateral diffusion ΔW in which the channel stopper layer penetrates under the gate electrode.
becomes narrower. The amount is twice ΔW per gate electrode. In contrast, according to the present invention, as shown in FIG. 4, the second control electrode 24 overlaps the first control electrode 23. This has the advantage that the stopper layer and the insulator can be removed, the lateral diffusion of chaffle bombs is reduced by 1 times ΔW, and the substantial gate electrode width can be increased.

This means that the narrow channel effect when using a fine pattern can be alleviated when the gate electrode width is the same, and there is an advantage that a fine pattern can be created.

Next, the operation of this semiconductor device will be explained with reference to FIG.

FIG. 5 is an explanatory diagram of the operation of the semiconductor device of the present invention, and FIG.
FIG. 5(a) is a schematic cross-sectional view thereof, and FIGS. 5(b) to 5(e) show potential states within the silicon substrate corresponding to FIG. 5(a). In addition, in FIG. 5(a), for convenience of explanation,
The load MO5l-transistor [Figure I] and the drive MOS transistor (IN+ + INz) Figure Ciii] are shown separately, and 31 is the base pole of the load transistor,
32 is the control electrode of the first drive transistor, 33 is the second drive transistor.
The control electrode of the drive transistor is shown.

Here, in FIG. 5(b), both IN and IN are in the OFF state, and in FIG. 5(c), IN is in the ON state,
IN.

is OFF state, IN in Fig. 5(d), is OFF state
.

IN is in the ON state, and in FIG. 5(e), IN, , IN are both in the ON state. Note that the transistor in this example is N
The voltage applied to the type channel is +■ to VDD, O■ to the GNI) terminal, and V is applied to the gate of the load MOS transistor Ql+, so that it is always in a conductive state.

In Fig. 5(b), since both INI and INg are opF, the potential under the gates of INI and INg is lower than GN[Level], and the output terminal is
It is out of conduction with the GND terminal. As a result, a voltage of (VDD V - ΔVT ) is generated at the output terminal. Here, VT is the gate threshold voltage of the MOS transistor, and ΔvT is the voltage change due to the back bias effect of the MOS transistor.

In FIG. 5(c), INI is ON, INt is OFF, and a channel is formed below INI. INt is in a non-conductive potential state with GND.

As a result, the output terminal has the ON state of the load MOS transistor.
A voltage determined by the resistance voltage division ratio between the resistor and the ON resistance of the transistor IN is output.

In FIG. 5(d), since INI is OFF and INz is ON, the area under IN is non-conductive, and a channel is formed under IN. As a result, the output terminal has the ON resistance of the load MOS transistor and the ON resistance of the transistor IN.
A voltage determined by the resistance voltage division ratio of the resistors is output.

In Figure 5(e), IN, , and INK are all ON, so INK.

A channel is formed under both IN and IN. The output voltage at this time is determined by the resistance voltage division ratio of the ON resistance of the load MOS transistor and the ON resistance of the INI and INK transistors connected in parallel.

As described above, even if a transistor is configured with gate electrodes overlapping each other, no operational problems occur because the potential state under the gate is dominated by the potential of the gate.

The overlapping portion of the gate is dominated by the gate potential on the side closer to the silicon substrate, and the influence of the voltage of the upper overlapping electrode has no effect on the silicon substrate because the electric field terminates at the lower electrode.

The amount of gate coverage of the present invention can be varied in various ways, as shown in FIG.

For example, as shown in FIG. 6(a), the first gate 41 and the second gate 42 slightly overlap, and as shown in FIG. 6(b), the first gate 41 and the second gate 42 overlap slightly. The amount of overlap may be arbitrary as long as the second gate 43 does not cross over the gate 41.

Further, the present invention can be constructed without being controlled by the electrode material of the multilayer gate.

Here, an example of a two-layer polycrystalline silicon gate and a polycrystalline silicon gate and an aluminum gate will be described.

FIG. 7 is an explanatory diagram of the step of forming a two-layer polycrystalline silicon gate by electric scraping.

First, as shown in FIG. 7(a), a silicon substrate 5
A first gate oxide film 51 is formed on 0.

Next, as shown in FIG. 7(b), a first polycrystalline silicon gate electrode 52 is formed.

Next, as shown in FIG. 7(c), the gate electrode 52
A second gate oxide film 53 is formed thereon.

Next, as shown in FIG. 7(d), the gate electrode 52
A second polycrystalline silicon gate electrode 54 is formed so as to overlap. In this case, a second gate oxide film 53 exists between the gate electrode 52 and the gate electrode 54, insulating the first and second gate electrodes.

Finally, source/drain diffusion layers 55 are formed.

FIG. 8 is an explanatory view of the process of forming a gate electrode using polycrystalline silicon for the first gate and aluminum film for the second gate.

First, as shown in FIG. 8(a), a silicon substrate 6
A first gate oxide film 61 is formed on 0.

Next, as shown in FIG. 8(b), a first polycrystalline silicon gate electrode 62 is formed.

Next, as shown in FIG. 8(c), source/drain diffusion Jii63 is formed.

Next, as shown in FIG. 8(d), a second gate oxide film 64 is formed. Then, as shown in FIG. 8(e), an aluminum gate electrode 65 is formed.

In this way, the difference in the manufacturing process from the two-layer polycrystalline silicon gate electrode shown in FIG.
The point is that the gate oxide film for the aluminum gate is formed after drain diffusion.

As described above in detail, the present invention can be constructed by appropriately selecting and using gate electrode materials.

In addition, although the above description has been made regarding a NOR gate powered by two people, the present invention is also applicable to a NOR gate powered by three or more people.

An example of a pattern configuration in the case of three-man power will be explained while comparing it with a conventional one of this type.

FIG. 9 is a block diagram of a conventional three-man powered NOR gate.

That is, FIG. 9(a) is a plan view thereof, showing a planar layout pattern. Figure 9(b) is Figure 9(a)
FIG. 2 is a sectional view taken along line bb. In the figure, +lto is the load MOS transistor, To+ is the first drive MO5) transistor, C1zz is the second drive MO5 transistor, f
lzi is the third driving MOS transistor, 71 is the drain diffusion layer of the transistor Q2°, 72 is the gate electrode of the transistor Q2°, and 73 is the transistor [lz
o source and transistor Q2. .

Q! □The common drain of 1 port and 2 units, and 74 are transistors QZI + Q! ! + +lz: common source of + and transistor Q! The gate electrodes of l + Qtt + Q23 are arranged in parallel. Further, 76 and 78 are channel stoppers, and 77° and 79 are insulators.

On the other hand, FIG. 10 is a block diagram of a three-man powered NOR gate according to the present invention. That is, FIG. 10(a) is a plan view thereof and shows a planar layout pattern, and FIG. 10(b) is a sectional view taken along the line bb--b of FIG. 10(a). In the figure, Q3゜ is a load MOS transistor, Q31 is a first drive MOS) transistor, and Q is a second drive MOS transistor.
O5) transistor; Q33 is the third drive MOS transistor; 81 is the transistor Q; the drain diffusion layer of
82 is a transistor Q. 83 is a transistor Q. source and transistor Q31 + 0
32 + 022 common drain, 84 is the common source of the transistor (h+ + 031 + Qss).

As is clear from these figures, in the conventional type, the channel stoppers 76 and 78 and the insulator 77 are
, 79 (see FIG. 9(b)), which requires space, whereas in the embodiment of the present invention,
As shown in FIG. 10, INI.

IN, , IN2 can be arranged compactly, and the electrodes of INI and lNff are made of the first polycrystalline silicon gate, and the electrode of IN, which has an overlap between these electrodes, is made of the second polycrystalline silicon gate. Consists of gates. Further, here, the electrode wiring is arranged in such a manner that IN crawls over IN.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, the following effects can be achieved.

(1) In the NOR circuit, it is possible to eliminate unnecessary channel stoppers, that is, channel stoppers and insulators for separating parallel connection portions of drive MOS transistors, and it is possible to reduce the size of the LSI pattern.

(2) Furthermore, since there is no unnecessary channel stopper, it is possible to prevent the actual gate width from being shortened due to lateral diffusion of the channel stopper, and it is possible to easily manufacture fine patterns.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a semiconductor device having a multilayer gate electrode structure constituting a NOR circuit according to the present invention, Fig. 2 is a block diagram of a conventional semiconductor device, and Fig. 3 is a diagram explaining problems of the conventional semiconductor device. , FIG. 4 is an explanatory diagram of the advantages of the semiconductor device of the present invention, FIG. 5 is an explanatory diagram of the operation of the semiconductor device of the present invention, FIG. 6 is an explanatory diagram of the overlapping state of the semiconductor device of the present invention, and FIG. Figure 8 is a process diagram for forming a layered polycrystalline silicon gate electrode; Figure 8 is a diagram showing a process diagram for forming an electrode using polycrystalline silicon for the first gate electrode and A2 for the second gate electrode; Figure 9 is a diagram showing the configuration of a conventional three-man-powered NOR gate; FIG. 10 shows another embodiment of the present invention.
It is a block diagram of an OR gate. Ql+...Load MO3 transistor, 11...Drain diffusion layer of transistor I, 12...Transistor Q. gate electrode, 13... source diffusion layer (output) of transistor Ql+, Q12... first drive MOS)
Transistor, 14... Control electrode of transistor Lz,
15... Control electrode of transistor Q12, 16...
Transistor Q1□. Qlff common source diffusion layer, 17... silicon substrate.

Claims (1)

[Claims] In a semiconductor device including a load MOS transistor and a plurality of drive MOS transistors and having a multilayer gate electrode structure constituting a NOR circuit, current flows through control electrodes of at least two adjacent transistors among the plurality of drive MOS transistors. A semiconductor device characterized by having an overlap over a channel region in a direction perpendicular to the direction.