JPS6338953B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method of controlling a voltage source inverter. Although the output voltage waveform of a voltage source inverter inevitably includes harmonic components due to the configuration of the inverter, it is preferable to reduce these harmonic components as much as possible. One way to improve the output waveform by controlling the inverter itself is to perform so-called pulse width modulation, which modulates the pulse width of multiple rectangular pulses obtained by performing multiple commutations during a half cycle. (hereinafter referred to as PWM) method is common. To give an overview of this PWM method,
It is as follows. FIG. 1 shows an example of a general three-phase voltage source inverter composed of six sets of transistor switching elements T ₁₁ -T ₁₃ and T ₂₁ -T ₂₃ . In the figure, Ed is a DC power supply, D ₁₁ to D ₁₃ , D ₂₁
~ _D23 is a surge absorption diode. In other words, in sinusoidal modulation using the conventional PWM method, switching elements T ₁₁ to _{T 13} on the positive side and negative switching elements provided in the arms of each phase are connected so that the output voltage waveform at the output terminal of each phase becomes a sine wave voltage. The switching elements T ₂₁ to T ₂₃ on the side are operated. For example, considering the U-phase, the U-phase terminal voltage is determined when switching element _T11 is conductive (hereinafter simply ON).
That's what it means. ) T ₂₁ is non-conducting (hereinafter simply referred to as OFF).
When , it becomes +1/2Ed, and when T ₁₁ is OFF and T ₂₁ is ON, it becomes -1/2Ed. By changing this ON-OFF ratio (ie, pulse width), the output voltage is modulated into a sine wave. Determines ON/OFF of this switching element
There are various methods to obtain a PWM signal, but a common method is to obtain it by comparing the voltage reference of each phase with a carrier wave. In this method, the output voltage is controlled by keeping the carrier wave peak value constant and changing the voltage reference peak value to change the ON/OFF duty ratio of the switching element. Hereinafter, the ratio of (peak value of reference wave)/(peak value of carrier wave) will be referred to as voltage control rate. Now, the disadvantage of the modulation control using the PWM method mentioned above is that when the voltage control rate α = 1, the maximum voltage peak value is

[Formula] remains, and it is not possible to output up to the maximum voltage peak value Ed, which is the DC power supply voltage, and therefore the conversion efficiency is poor. Here, an example of a modulation control method using the conventional PWM method is shown in FIGS. 2a, b, and c. For the U phase, by applying the gate signal shown in figure b to switching element T ₁₁ and the gate signal shown in figure T ₂₁ c, the voltage of the U phase becomes as shown in figure a, and its average waveform is shown by the dotted line. A sine wave of d can be obtained. The V and W phases are similarly modulated with a phase difference of 120 degrees, resulting in a sinusoidally modulated three-phase AC voltage. In other words, the voltages of each of the three phases Vu, Vv,
Vw is expressed as Vu=1/2Edsinωt Vv=1/2Edsin(ωt−120°) Vw=1/2Edsin(ωt+120°). ω is the angular velocity of the output frequency. Therefore, the phase-to-phase voltages Vu-v, Vv-w, Vw
-u is It is expressed as As can be seen from equations (1), (2), and (3) above, the maximum voltage peak value is

[Formula] can only be obtained. Furthermore, according to the conventional PWM method, it is necessary to provide a modulation circuit for each phase, which requires control over a 360-degree period (or alternate use of 180-degree periods), making the control circuit extremely complex. There are drawbacks such as: SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for controlling a voltage source inverter with a simple configuration and high conversion efficiency, which can obtain the same voltage peak value as the power supply voltage when the voltage control rate α=1. The present invention will be described in detail below based on illustrated embodiments. FIGS. 3a, 3b, and 3c are voltage waveform diagrams of the inverter controlled by the control method according to the present invention. In Figure 3a and b, the U-phase voltage Vu is shown by a solid line, the V-phase voltage Vv is shown by a dashed-dotted line, and the W-phase voltage
Vw is shown as a dashed line. In the control method according to the present invention, (i) control intervals are set at intervals of 30 electrical degrees of the output voltage frequency of the inverter. This control interval is indicated by t ₁ -t ₁₂ in FIGS. 3a and 3b. (ii) In each 30-degree period (each t ₁ to t ₁₂ ) of the control period, the potential (e.g., Vv) of any one phase (e.g., V phase) of the three-phase UVW of the inverter is By keeping the switching element (for example, T ₂₂ ) on the side) conductive for a period of 30 degrees, it is fixed at the positive potential or negative potential of the DC power supply (at t ₁ in FIG. 3a, it is fixed at the negative potential). In addition,
In the figure, the fixed potential is shown by a thick line. (iii) The fixed phase mentioned above is sequentially switched to the next phase every 30 degree period. For example, t ₁ (V
phase) → t ₂ (W phase) → t ₃ (U phase), and so on. (iv) Furthermore, the potential of the fixed phase is alternately switched between positive potential and negative potential every 60° period. For example, in the 30 degree period t ₁ , the V phase is fixed at a negative potential, and in the 30 degree period t ₁₂ adjacent to t ₁ , the U phase is fixed at a negative potential, so the negative potential is fixed at 60 degrees. It is a degree period. then t ₂ 30
During the degree period, the W phase is fixed at a positive potential, and at _t3 , the U phase is fixed at a positive potential.Therefore, the negative potential is reversed to a positive potential, and the positive potential is fixed for a period of 60 degrees. (v) Two phases other than the phase fixed in each control period t ₁ to t ₁₂ (for example, if the V phase is fixed, UW
The switching elements of the two phases are subjected to pulse width modulation control so that the potentials of the two phases generate a predetermined interphase voltage with respect to the potential of the fixed phase.
This will be discussed later. A more specific explanation is as follows. That is, FIG. 3a is a voltage waveform diagram of each phase when the voltage control rate α=1, and in period _t1 in the figure, the V-phase voltage Vv is held fixed at the negative potential of the DC power supply. On the other hand, the U-phase voltage Vu is expressed as Vu=αEdsinθ=Edsinθ with respect to the negative potential of the DC power supply. However, θ is set to 0 at the beginning of the _t1 period. It is controlled so that a potential difference of . W phase voltage
Vw is controlled so that a potential difference of Vw = αEdsin (θ + 60°) = Edsin (θ + 60°) is generated with respect to the negative potential (-1/2 Ed) of the DC power supply. Therefore, the UV phase voltage Vu-v is controlled to be Vu-v=Edsinθ with the V-phase voltage Vv as a reference, and the V-W phase voltage Vv-w is Vv-w=-Edsin(θ+60°)= Controlled by Edsin (θ−120°). Further, the W-U phase voltage Vw-u is Vw-u=Edsin(θ+60°)−Edsinθ=Edsin(θ+120°). During the control period _t2 , the W-phase voltage Vw is fixed to the positive potential of the DC power supply, and the U-phase voltage Vu is set to the positive potential of the DC power supply as follows: Vu=-αEdsin(θ+120°) =-Edsin(θ+120°) controlled to generate a potential difference. V phase voltage
Vv is controlled to generate a potential difference of Vv = -αEdsin (θ + 120°) = -Edsin (θ + 120°) with respect to the positive potential of the DC power supply. Therefore, the W-U phase voltage Vw-u is controlled to be Vw-u = Edsin (θ + 120°), and the V-W phase voltage Vv-w is controlled to be Vv-w = Edsin (θ-120°). . Further, the UV interphase voltage is controlled to be Vu−v=−Edsin(θ+120°) −{−Ed(θ+60°)}=Edsinθ. In the same way, UV is applied every control period t ₃ , t ₄ ...
Any one of the W phases is sequentially and alternately fixed to the positive or negative potential of the DC power supply, while the other two phases are controlled to generate the above-mentioned predetermined phase-to-phase voltage with respect to the fixed phase. . Further, the potential of the fixed phase is controlled by being alternately switched between the positive potential and the negative potential of the DC power supply every 60 degrees. Note that when focusing on each phase-to-phase voltage, the UV phase-to-phase voltage Vu-v for each control period is always given by Edsinθ,
V-W phase voltage Vv-w is always Edsin (θ-120°)
The W-U phase voltage Vw-u is always Edsin(θ+
120°). Figure 3b shows the modulation state of each phase potential when the voltage control rate α = 0.4, and it can be clearly seen that the phase-to-phase voltage is generated based on the positive or negative potential of the DC power supply as described above. . FIG. 3c shows the UV interphase voltage in the case of FIGS. 3a and 3b, that is, the voltage control rate α=1 and α=0.4. With the control method described above, the peak value of the phase-to-phase voltage is equal to the DC voltage Ed at a voltage control rate α=1.
The voltage value can be equal to . Similarly, a sine wave voltage with a peak value Ed can be obtained for the V-W inter-phase voltage and the W-U inter-phase voltage with a phase difference of 120 degrees. Next, a control device for implementing the control method according to the present invention will be explained. FIG. 4 is a block diagram showing a generating circuit for generating a PWM waveform in the control method according to the present invention. In response to the output signal from this PWM waveform generating circuit, the switching elements T ₁₁ to _{T 13} of each phase of the inverter are connected. A control circuit for controlling the gates T ₂₁ to _{T 23} is shown in FIG. and,
PWM waveform generation circuit (Figure 4) and control circuit (Figure 5)
The operation waveform diagram of each part in FIG. 6 is shown in FIG. In FIG. 4, 1 indicates an output frequency command device. This output frequency command device 1 outputs a voltage signal corresponding to the frequency of the output voltage to be output from the inverter. 2 indicates a voltage frequency converter (hereinafter referred to as a V/F converter). This V/F converter converts the voltage signal given by the output frequency command device 1 into a frequency signal and outputs a pulse signal of the corresponding frequency. 3 indicates an N-bit counter. This counter counts the output pulse signal of the V/F converter 2 and outputs the count value. Here,
The most significant bit of the output count value a is set to N bits, and the lower bits are sequentially (N-1) and (N-
2), Bit... Therefore, the output signal is a(N),
Let them be expressed as a(N-1) and a(N-2). 4 indicates a hexadecimal ring counter. The ring counter 4 receives the (N-2)th bit output signal a(N-2) of the counter 3, and outputs output signals b to g to the control circuit (FIG. 5). Output signals of counter 3 a(N), a(N-1), a(N-2)
The relationship between and the output signals b to g of the counter 4 is shown in FIG. 5 indicates a switching circuit. This switching circuit 5 is composed of an exclusive OR logic circuit,
The Nth bit output signals a(N) and (N
-1) Perform exclusive OR with the bit-th output signal a(N-1) and output the switching signal h. This switching signal h and N-th bit output signals a(N) and (N
-1) The relationship with the bit output signal a(N-1) is shown in FIG. 6 indicates an up/down switching circuit. This up/down switching circuit 6 receives a lower bit signal a(N-2) from the (N-1) bits of the counter 3.
...a(N−n) is input. The up/down switching circuit 6 is composed of (N-2) exclusive OR logic circuits. (N-1) of counter 3 is commonly used as one input signal of each logic circuit.
The output signal a(N-1) of the bit bit is given, and the output signal a(N-2) of the (N-2)th bit and below is given as the other input signal. Therefore,
The output signal i of the up-down switching circuit 6 is counted up during the period when the (N-1)th bit output signal a (N-1) of the counter 3 is at logic "0".
The period of logic "1" is counted down. This output signal i specifies the address of a read-only memory (hereinafter referred to as ROM) 7, which will be described later. In the ROM 7, a sine function of electrical angle (Y×30/2 ^N-2 −1+60) degrees, ie, sin(Y×30/2 ^N-2 −1+60) degrees, is written at address Y. Since the address Y of the ROM 7 is specified by the output signal i of the up/down switching circuit 6, it repeatedly increases and decreases between Y=0 and Y=(2 ^N-2 -1). That is, from 0 to (2 ^N-2 −
It increases to 1), decreases to 0 when it reaches (2 ^N-2 -1), increases again, and so on. Therefore, the ROM 7 outputs the output signal j while repeating the increase and decrease of the function from sin60° to sin90°. The form of this output signal j is as shown in FIG. In the ROM 8, a sine function of electrical angle (Y×30/2 ^N-2 −1) degrees, ie, sin(Y×30/2 ^N-2 −1) degrees, is written at address Y. ROM8 has address Y from 0 to
When increasing or decreasing between (2 ^N-2 -1), the output signal k is repeatedly output while increasing or decreasing the function value from sin0° to sin30°. 9 and 10 indicate pulse width modulation circuits (hereinafter referred to as PWM circuits). Note that there are various known pulse width modulation methods, and any method may be used here, so a specific circuit is not illustrated. The PWM circuit 9 pulse-modulates the output signal j [=sin(Y×30/2 ^N-2 −1+60)°] from the ROM 7 according to a voltage control rate signal α given from another source. Therefore, the output signal l of the PWM circuit 9 is output as a signal obtained by pulse modulating α×sin(Y×30/2 ^N-2 −1×60)°. similarly
The PWM circuit 10 pulse-modulates the output signal k [=sin(Y+30/2 ^N-2 -1)°] from the ROM 8 in accordance with the voltage control rate α given from another source. Therefore, the output signal m of the PWM circuit 10 is output as a signal obtained by pulse modulating α×sin(Y×30/2 ^N-2 −1)°. Reference numerals 11 and 12 each indicate a switching circuit.
Both switching circuits 11 and 12 are constructed from exclusive OR logic circuits. In the switching circuit 11
The output signal l of the PWM circuit 9 and the output signal h of the switching circuit 5 are input to the switching circuit 12.
The output signal m of 0 and the output signal h of the switching circuit 5 are input. Therefore, when the output signal h of the switching circuit 5 is "0", the PWM circuits 9 and 10 output the output signal h as it is, and when it is "1", they invert it and output it. The average value waveform of the output signal of the switching circuit 11 is as shown in FIG.
The average value waveform of the output signal p is as shown in FIG. 6r. The actual pulse width modulated output waveforms of the switching circuits 11 and 12 are shown in FIG. 6, p. In FIG. 5, 13, 14, and 15 each indicate a control circuit, which is composed of an AND circuit and an OR circuit. These control circuits 13-1
5 is an output voltage command signal of each phase of the inverter, that is, a switching element T ₁₁ of each phase, based on the input logic conditions of the output signals b to g of the ring counter 4 and the output signals h, o, and p of the switching circuits 5, 11, and 12.
Gate control signal G _1u of ~T ₁₃ and T ₂₁ ~T ₂₃ ,
Output G _1v , G _1w and G _2u , G _2v , G _2w . The gate control signals G _2u , G _2v , G _2w are sent to the knot circuits 16, 1
7 and 18, the signals are inverted to the opposite logic to G _1u , G _1v , and G _1w . Hereinafter, the operation of creating the output voltage command in the control circuits 13, 14, and 15 will be described for the U phase. As shown in FIG. 6, in the control circuit ₁₃ , the output signals h, _o , o, p is selected in the following manner. (Control period) (Output signal) t ₁ , t ₂ → p t ₃ → h t ₄ , t ₅ → o t ₆ → h t ₇ , t ₈ → p t ₉ → h t ₁₀ , t ₁₁ → o t ₁₂ →h As a result, the PWM waveform obtained for the U phase becomes the waveform shown by U in FIG. In addition, at this time, the same p signal in the period t ₁ and t ₇ , the same p signal in the period t ₂ and t ₈ , the same h signal in the period t ₃ and t ₉ , and so on for 6 periods. The same signals are selected in mutually distant periods. Therefore, one period is
Although divided into 12 periods, all 12 periods can be individually selected using the output signals b to g of the hexadecimal ring counter 4. In this way, the control circuit 13 controls the control period t ₁ or t ₇
The output signal f of the ring counter 4 and the output signal P of the switching circuit 12 are ANDed at t ₂ or t ₈
By taking the logical product of g and p at ...t ₆ or t ₁₂ , and calculating the sum of all of these output signals by the switching circuit, Continuous for one period as shown
PWM waveform can be obtained. The average value waveform of this waveform U is as shown in FIG. 6 U', and this average value waveform U' is the waveform obtained based on the control method of the present invention previously shown in FIG. Although the U-phase has been described above, the V-phase and W-phase can also be operated with a phase difference of 120 degrees by the control circuits 14 and 15, and similar waveforms can be obtained. The inverter output voltage command signal thus obtained is given as a gate control signal to the switching elements T ₁₁ to T ₁₃ and T ₂₁ to _{T 23} of each phase of the inverter, as described above. Gate control signal G _1u ,
G _1v and G _1w are applied to switching elements T ₁₁ to _{T 13} via a base drive circuit (not shown).
On the other hand, the switching elements T ₂₁ to _{T 23} have G _1u , G _1v ,
Gate control signals G _2u , G _2v , and G _2w obtained by inverting G 1w via knot circuits 16, 17, and ₁₈ are applied via a base drive circuit (not shown). These gate control signals G _1u ~ G _3w , G _2u ~ _{G 3w}
The average value of the phase-to-phase voltage of the inverter is controlled to be a sine wave. For example, when looking at the UV phase-to-phase voltage, the PWM waveform is as shown in Figure 6 UV,
The average value waveform can be a sine wave as shown by the broken line. As described above, according to the control method of the present invention, the pulse width modulation circuit can have a simple configuration since only two sets are required, and the pulse width modulation circuit can have the largest possible value based on the given DC power supply. It is possible to obtain a sine wave voltage of 1, and therefore it is possible to provide an inverter with a simple configuration and high conversion efficiency. In addition, in the conventional control method of sinusoidally modulating each phase voltage, depending on the PWM control method, the modulation of each phase may interfere with each other, causing waveform disturbances in the phase-to-phase voltage. be. Therefore,
If such a disturbance occurs when the phase of the interphase voltage is small, there is a risk that the phase error will become extremely large. However, according to the control method of the present invention, for example, when the phase-to-phase voltage is sinθ, θ is 0 to 30 degrees,
During periods of 150 to 210 degrees and 330 to 360 degrees, the phase voltage of each phase is held fixed at either the positive potential or the negative potential of the DC power supply, and the phase-to-phase voltage is adjusted by pulse width modulating the other phase potential. Because it generates
This has an excellent effect in that no disturbance of the phase-to-phase voltage occurs during a period in which the phase-to-phase voltage is small.

[Brief explanation of the drawing]

Figure 1 is a main circuit diagram of a general voltage source inverter, and Figure 2 shows an example of sine wave modulation using conventional PWM control, where a is a U-phase voltage waveform diagram, b,
c is a gate control signal waveform diagram of the switching element;
Figure 3 shows the output voltage waveform according to the control method of the present invention, where a is a waveform diagram when the voltage control rate α=1, b is a waveform diagram when α=0.4, and c is the UV phase voltage Figure 4 is a PWM waveform generation circuit used in the control method of the present invention, Figure 5 is a diagram of the average value waveform of
Figure 6 shows a control circuit that receives the output signal of the waveform generation circuit and generates gate control signals for each phase of the inverter.
This is a time chart for explaining the operation of the PWM waveform generation circuit and control circuit. Ed...DC power supply voltage, _T11 to _T13 ; _T21 to _T23 ...Switching element, _t1 to _t12 ...Control period, _Vu , _Vv ,
V _w ...Each phase voltage, 1...Output frequency command, 2...
V/F converter, 3...N bit counter, 4...
Hexadecimal ring counter, 5... switching circuit, 6... up/down switching circuit, 7... ROM, 8... ROM,
9...PWM circuit, 10...PWM circuit, 11...switching circuit, 12...switching circuit, 13...control circuit, 14...
Control circuit, 15... Control circuit, 16, 17, 18...
Not circuit.

Claims (1)

[Scope of Claims] 1. In a voltage source inverter that obtains three-phase AC voltage from a DC power source, (a) a control period is set every 30 electrical degrees of the output voltage of the inverter, and (b) the above-mentioned During each 30-degree period of the control period, the potential of any one of the three phases of the inverter is fixed to the positive potential or negative potential of the DC power supply by conducting the switching element of one arm of this phase, and (c ) This fixed phase is sequentially switched to the next phase every 30 degree period, (d) and the potential of the fixed phase is alternately switched between positive and negative every 60 degree period, (e) A voltage source inverter characterized in that the two-phase switching elements perform pulse width modulation control so that the potentials of the two phases generate a predetermined interphase voltage with respect to the potential of the fixed phase. Control method.