JP2593081B2 - Inverter device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC / AC converter, that is, an inverter, and more particularly, to an inverter capable of relatively easily obtaining a desired AC waveform.

[Conventional technology]

Japanese Patent Application Laid-Open No. 62-207196 discloses a method in which the presence / absence voltage vector and the zero voltage vector are written in a memory in a predetermined order, and are sequentially read by an address counter.

[Problems to be solved by the invention]

By the way, in the method of controlling a plurality of switching elements of a three-phase inverter collectively as disclosed in the above application, the speed of the magnetic flux vector based on the inverter output is 30 degrees, 90 degrees with respect to the first phase of the three-phase output voltage. , 150 degrees, 210 degrees, 27
It gets faster at 0 degrees and 330 degrees, slows down in the middle of these,
A sine wave with good approximation could not be obtained.

Therefore, an object of the present invention is to provide an inverter device that can easily obtain a sine wave with good approximation.

[Means for Solving the Problems] The present invention for achieving the above object will be described with reference to the reference numerals in the drawings showing the embodiments. The input DC voltage is intermittently switched to a pulse width modulation state by a plurality of switching elements. And a plurality of switching elements so that an approximate sine-wave three-phase AC voltage can be obtained from the three-phase inverse conversion circuit 5. Voltage vector data and zero voltage vector data for collectively controlling the three-phase inverse conversion circuit 5
And the waveform data indicating the three-phase full-wave rectified waveform of the sine-wave three-phase AC voltage corresponding to the target output voltage is written so as to correspond to the section from 0 to 360 degrees of the AC voltage waveform. First, second and third memories M1, M2, M3
And an address counter 10 for reading out each of the valued voltage vector data, the zero voltage vector data, and the waveform data from the first, second, and third memories M1, M2, M3 in a predetermined order. , The address counter 10
Oscillator 21 that generates clock pulses for
A triangular wave generation circuit 19 having a repetition frequency sufficiently higher than the frequency of the AC voltage to generate data indicating a triangular wave; the triangular wave generation circuit 19 and the third memory M3
A modulating means 18 for modulating the triangular wave so that the maximum amplitude value of the triangular wave corresponds to the three-phase full-wave rectified waveform, and a desired frequency of the output AC voltage of the three-phase inverse conversion circuit 5 Frequency command signal providing means 23 for providing a frequency command signal indicating the
And a comparator 22 connected to the frequency command signal applying means 23 and configured to generate a comparison output between the modulated triangular wave and the frequency command signal, and a comparator 22 connected to the clock oscillator 21. One input terminal, a second input terminal connected to the comparator 22, and an output terminal connected to the address counter 10, and the modulated three-phase wave does not cross the frequency command signal. A clock pulse from the clock oscillator 21 to the address counter 10 in response to the output of the comparator 22 indicating that the modulated triangular wave is crossing the frequency command signal. A gate circuit 20 formed to block the transmission of the clock pulse to the address counter 10 in response to the output of the comparator 22 and the first circuit.
And outputting the valued voltage vector data of the first memory M1 when the modulated triangular wave is not crossing the frequency command signal and connected to the second memories M1 and M2, Select gate means 11, formed so as to output the zero voltage vector data of the second memory M2 when crossing the frequency command signal,
12, 13, 15 and the switching elements A1, A2, B1, B2, C1, C2 of the three-phase inversion circuit 5 are turned on based on the data selected by the selection gate means 11, 12, 13, 15. The present invention relates to an inverter device including a drive circuit 8 for off-drive.

[Operation and Effect of the Invention] According to the present invention, the triangular wave is modulated by the data indicating the three-phase full-wave rectified waveform read from the third memory M3. As a result, 30 degrees, 90 degrees, 150 degrees, 210 degrees,
The maximum amplitude of the triangular wave increases at 270 degrees, 330 degrees, and the vicinity thereof, and the maximum amplitude of the triangular wave decreases at an intermediate portion between them. As a result, the blocking time of the clock pulse input to the address counter 10 is 30, 90, 150, 210, 27
At 0 degrees, 330 degrees and in the vicinity, these intermediate parts (0
, 60, 120, 180, 240, and 300 degrees), and the number of clock pulses input to the address counter 10 per unit time is reduced. Therefore, in these regions, the number of address switching per unit time is reduced, and as a result, the speed of the magnetic flux vector becomes substantially constant on the circumference, and a sine wave output voltage with good approximation can be obtained.

〔Example〕

Next, a frequency converter according to an embodiment of the present invention will be described. Three-phase AC power lines 1, 2, 3 connected to commercial power
The three-phase full-wave rectifier circuit 4 and the diode D ₁ to D ₆ and Buritsuji connection is connected. No filter for removing ripples is connected to the output stage of the full-wave rectifier circuit 4, and the reverse conversion circuit 3, that is, a reactor 6 of about 1 to 2 mH for removing high-frequency noise due to switching of the inverter circuit, is smoothed. Capacitor 7 is connected.

The PWM controllable three-phase inverter 5 is a device in which switching elements A ₁ , A ₂ , B ₁ , B ₂ , C ₁ , and C ₂ composed of transistors are connected in a bridge, and a diode D is connected in parallel to each switching element. The six switching elements A _{1 to} C ₂ are:
On / off operation is performed in response to a control signal supplied from the drive circuit 8. Note that the upper three switching elements A ₁ , B ₁ , and C _{1 of} the inverter 5 and the lower three switching elements
Since A ₂ , B ₂ , and C ₂ operate in opposite directions, specifying one of the controls specifies the control of the entire inverter. Here, the inverter control state is specified by the first, second, and third signals A, B, and C read from a ROM (read only memory) 9, and the signals A, B, and C are set to a high level, that is, logic "1". When ", the switching elements A ₁ , B ₁ , C ₁ are on,
The switching elements A ₁ , B ₁ ,
C ₁ is turned off.

ROM9 is written the PWM when to quenching pattern first memory M ₁ is written (unit vector data) in advance for PWM-controlling inverter 5, the second writing the zero vector and the memory M _2, the speed adjustment data Third memory M ₃
And Each of the memories M _{1 to} M ₃ is, for example, 512 to 0 to 511.
Each has an address, each addressed by the value of a 9-bit binary output line of counter 10. First memory M ₁
The eigenvalues vector and not output at the same time the second memory M ₂ zero vector are output alternatively. In order to make this alternative control, the output lines of the first 3 of the memory M ₁ bit is first AND gate 11 and OR gate 12 and the driving circuit through the 8
Is connected to the second three bits output lines of the memory M ₂ is the second AND gate 13 and OR gate 12 and the driving circuit 8 via the
The first AND gate 11 is controlled by the output of the comparator 22, and the second AND gate 13 is controlled by the output of the NOT circuit 15 connected to the output of the comparator 22. In addition,
In FIG. 1, the first and second memories M ₁ and M ₂ are shown for convenience of illustration.
, The output lines of the first and second AND gates 11 and 13, and the output line of the OR gate 12 are shown by one line, which are three signals A indicating a voltage vector, It consists of three (3 bit) signal lines for transmitting B and C. First and second memories as will become apparent from the description below.
The principle of the control of the switching-element A ₁ -C ₂ inverse transform circuit 5 based on the eigenvalues vectors and zero vector of M _1, M ₂ is JP
It is the same as that disclosed in JP-A-62-207196.

The drive circuit 8 includes three NOT circuits. Input signals A, B, and C are supplied to respective bases of the switching elements A ₁ , B ₁ , and C ₁ , and signals A, B, and C are inverted by the NOT circuits. Is supplied to the bases of the switching elements A ₂ , B ₂ , and C ₂ .

The input terminal of the address counter 10 is connected to a 4 MHz clock oscillator 21 via an AND gate 20. The AND gate 20 controls the passage of the clock signal. The other input terminal of the AND gate 20 is connected to the comparator 22.

The non-inverting input terminal of the comparator 22 is a frequency command signal line 23.
The inverting input terminal is connected to a triangular wave generation circuit 19 via a modulation circuit 18. The triangular wave generation circuit 19 generates a triangular wave at a frequency (for example, 20 kHz) sufficiently higher than the output AC voltage of the inverse conversion circuit 5. The modulation circuit 18 is also connected to the third memory M3, and converts the three-phase full rectified waveform of the sine-wave three-phase AC voltage shown in FIG. 5A as speed adjustment data obtained from the third memory M3. The amplitude modulation of the triangular wave is performed by the data shown. Note that the output of the comparator 22 is also used to select the output of the first and second memories M1 and M2. Next, the operation principle and each part will be described in more detail.

〔Operating principle〕

Sum of each phase voltage, V _a in a three-phase voltage type inverter connected to a DC power supply that supplies a completely smoothed DC voltage
These instantaneous values if you choose the neutral point voltage is defined as the space vector _{V = 2/3 (V a} + V b · e -j2π / 3 + V c · e -j4π / 3) to + V _b + V _c = 0 It can be represented by an instantaneous space vector. There are a total of eight types of instantaneous space voltage vectors of the output depending on the switching state of the inverter. Two of them V
₀ (000) and V ₇ (111) are zero voltage vectors because the output is short-circuited. In order to obtain a sine-wave symmetrical three-phase alternating current at the output, the vector obtained by time-integrating the voltage vector, that is, the trajectory of the magnetic flux vector must also be a circle. Even if the vector moves at a constant speed, the locus of the magnetic flux vector rotating at a speed proportional to the DC voltage is shown in FIG. Is fast at 30 degrees and slow at 0 degrees, and a complete sine wave cannot be obtained. The portion where the speed of the magnetic flux vector becomes faster is 30 degrees, 90 degrees, 150 degrees, 210 degrees in FIG.
The portions at 270 degrees and 330 degrees are the intermediate portions between which the speed is reduced. Therefore, this speed distribution becomes like a three-phase full-wave rectified waveform of the three-phase inverter output. Therefore,
In Figure 1 the third memory M _3, data a 5 bit corresponding to the three-phase full-wave rectified waveform of an output voltage of the inverse transform circuit 5 shown in FIG. 5 (A) is written. In order to rotate the magnetic flux vector at a constant speed, the speed at which the voltage vector advances may be modulated so as to follow the reciprocal of the three-phase full-wave rectified waveform in FIG. 5 (A). In this voltage vector velocity modulation, a multiplying DA converter (M · D / A) is used for the modulation circuit 18 in FIG. The signal is modulated as indicated by the triangular wave signal b, input to the comparator 22, and compared with the frequency command signal c shown in FIG. 5B to form a comparison output shown in FIG. 5C. , And to the AND gate 20 to pass the clock signal as shown in FIG. 5D only during the period when the comparison output in FIG. You. In short, the number of input clock pulses per unit time length of the address counter 10 is reduced in the vicinity of 30 degrees where the rotation of the magnetic flux vector is accelerated in FIG. 4, and increased in the vicinity of 0 degrees. Thereby, the speed of the magnetic flux vector becomes constant on the circumference. In addition,
When the zero vector of the second memory M ₂ is selected, motion trajectory of FIG. 4 is stopped, the time constant of the load to move the slave connexion center direction, speed adjustment is performed.

[Contents of ROM]

Data is written in the memories M ₁ , M ₂ and M ₃ of the ROM 9 as shown in principle in FIG. That is, each memory M _{1 of the} ROM 9
~M _3, for example addresses 0 to 511 respectively have, in the first address 0-3 memory M ₁ for example, a voltage vector V _6, V _2,
3-bit data (A, B, C) of V ₆ and V ₂ are written in order, and a zero vector is stored in addresses 0 to 3 of the second memory M _2.
Data _{V 7, V 0, V 7} , V 0 is written in this order, the third data a corresponding 5-bit full-wave rectified waveform of the three-phase output of the memory M ₃ inverse conversion circuit 5 sequentially Has been written. The remaining addresses 4 to 511 are also written with vector data according to the same principle as the addresses 0 to 3. The vector data of each address shown in FIG. 2 shows the principle and differs from the actual data. Now, indicating the actual voltage vector data of the first address of the memory M ₁ 0-84 (corresponding to 0 ° to 60 ° _{interval), V 6, V 6,} V 6, V 6, V 2, V 2 , V ₂ , V ₂ , V ₂ , V ₂ , V ₆ , V ₆ ,
_{V 6, V 6, V 2} , V 2, V 2, V 2, V 2, V 2, V 6, V 6, V 6, V 6,
V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ ,
V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ ,
V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ , V ₂ ,
_{V 2, V 3, V 3} , V 3, V 3, V 2, V 2, V 2, V 2, V 2, V 2, V 3,
_{V 3, V 3, V 3} , V 2, V 2, V 2, V 2, V 2, V 2, V 3, V 3, V 3, V 3
become.

[Voltage vector]

Figure 3 shows the six voltage vectors V ₁ ~V _6, and two zero vectors V _0, V _7. The switching states that the switching elements A ₁ , B ₁ , and C ₁ can take are (000), (001), and (01).
0), (011), (100), (101), (110), and (111), which are represented by V ₀ , V ₁ , V ₂ , V ₃ , V ₄ , V ₅ , V ₆ ,
To be represented by V _7. In the apparatus of this embodiment is written to the voltage vector V ₀ ~V ₇ is the memory M ₁ of the first and second 2, M _2, which is the output control data (A, B, C) as a. Combining eight vectors V ₀ ~V _7, it is possible to obtain a sinusoidal output voltage and rotating magnetic field vector.

[Vector selection]

Figure 4 shows a selection of the voltage vector to obtain a rotating magnetic field vector phi _1. In order to make the trajectory of the tip (end point) of the rotating magnetic field vector φ ₁ close to a circle, it is required to be 330 ° to 3 °.
Sixth and second vectors V ₆ and V ₂ in the 0 ° section, 30 ° to 90 °
Vector V ₂ of the second and third in the section, V _3, 90 ° to 150 DEG in ° interval third and first vector V _3, V _1, 0.99 ° to 210 first and fifth vector V in ° intervals _1, V _5, 210 ° _~270 in ° intervals fifth and fourth vector _{V 5, V 4, 270 °} ~330 selecting fourth and vector V _4, V ₆ of the 6 ° intervals. V and V ₆ as eigenvalues vector in the fourth diagram of 330 ° to 30 ° interval shown in principle
₂ and are selected, and zero vector V ₇ is selected when stopping the vector rotation.

Output bits of the comparator 22 is at a low level, the second memory M ₂ is selected, the output of the comparator 22 is at the time of high level is selected first memory M ₁ is. While the output of the comparator 22 is at a high level, the clock pulse passes through the AND gate 20 and becomes an input pulse of the address counter 10. This allows
The value of n of the counter 10 bits (9 bits) is increased by up-operation, the first address of the memory M ₁ are sequentially designated. However, when the output of the comparator 22 goes low, the clock input of the address counter 10 is inhibited, and the address counter retains the address specification at this time. For example,
When the vector V ₆ of the memory M ₁ at the address 2 is read out as shown in FIG. 2, the memory M ₂ is selected, the zero vector V ₇ at the same address 2 (111) is selected. Zero vector V ₇ continues to occur between the output of the comparator 22 is low, again counter comparator output Te Modotsu the high level 10
When the clock pulse is input to the first memory M and the output of the counter 10 is incremented by _one , the voltage vector V ₂ (010) at the address 3 of the first memory M1 is selected. Zero vector is V
A vector which is composed of two types, ₀ (000) and V ₇ (111), and requires less switching of the switch elements A _{1 to} C ₂ is selected. When the counter 10 finishes generating the binary numbers corresponding to the decimal numbers 0 to 511, the entire voltage vector data of 0 to 360 degrees is read, and the three-phase approximate sine wave voltage is generated from the inverse conversion circuit 5, For example, a three-phase AC motor connected to the lines 26, 27, 28 generates a rotating magnetic field vector close to a circular locus.

[Experimental results] The switching pattern, that is, the value vector, the zero vector, and the ripple data are written into the ROM 9 every 360/2048 degrees.
A load of R = 10Ω and L = 10 mH is connected to the output lines 26, 27, and 28, and the inverse conversion circuit 5 is an input to the input power supply lines 1, 2, and 3 when the approximate sine wave is output by simple PWM drive. Current waveform, DC voltage waveform of DC lines 24 and 25, output line
The output current waveforms of 26, 27 and 28 were as shown in FIG.

(Modification)

The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.

(A) as a switching-element A ₁ -C ₂ may be used FET.

(B) The output of the triangular wave generating circuit in the circuit system of Japanese Patent Application No. 61-47875 may be modulated according to the angle of the inverter output waveform. That is, the absolute value of the comparison output between the output of the speed detector of the AC motor connected to the output lines 26, 27, and 28 of the inverse conversion circuit 5 and the reference value is input to the frequency command signal line 23 of FIG. You may do so. In addition,
A proportional integration circuit is inserted in the comparison output line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a frequency converter according to an embodiment of the present invention, FIG. 2 is a diagram showing a part of the contents of the ROM of FIG. 1 in principle, FIG. 3 is a diagram showing voltage vectors, FIG. 4 is a diagram showing a rotating magnetic field vector, FIG. 5 is a waveform diagram showing the state of each unit in FIG. 1, and FIG. 6 is a waveform diagram of each unit in FIG. 1, 2, 3 ... power line, 4 ... rectifier circuit, 5 ... reverse conversion circuit, 7 ... bypass capacitor, 9 ... ROM, 14 ...
1st comparator, 16... Divider, 17... Voltage command signal line, 22... 2nd comparator, 25.

Claims (1)

(57) [Claims] An inverting three-phase conversion circuit for converting an input DC voltage into a pulse width modulated state by a plurality of switching elements to convert the input DC voltage into an approximate sine wave three-phase AC voltage.
Value voltage vector data and zero voltage vector data for collectively controlling the plurality of switching elements so that an approximate sine wave three-phase AC voltage can be obtained from the three-phase inversion circuit (5). The waveform data representing the three-phase full-wave rectified waveform of the sine-wave three-phase AC voltage corresponding to the target output voltage of the three-phase inversion circuit (5) is obtained from the 0-degree waveform of the AC voltage.
First, second, and third memories (M1, M2, M3), each of which is written so as to correspond to a 360-degree section, and the first, second, and third memories (M1, M2, M3) an address counter (10) for reading out the value voltage vector data, zero voltage vector data and the waveform data in a predetermined order, respectively, and a clock oscillator for generating a clock pulse for the address counter (10) (21) a triangular wave generating circuit (1) having a repetition frequency sufficiently higher than the frequency of the AC voltage and generating data indicating a triangular wave;
9) for connecting the triangular wave generating circuit (19) and the third memory (M3) to modulate the triangular wave so that the maximum amplitude value of the triangular wave corresponds to the three-phase full-wave rectified waveform. A modulating means (18); a frequency command signal applying means (23) for applying a frequency command signal indicating a desired frequency of an output AC voltage of the three-phase inversion circuit (5) by a DC level; ) And the frequency command signal providing means (2
3) a first comparator connected to the clock oscillator (21); and a comparator (22) formed to generate a comparison output between the modulated triangular wave and the frequency command signal. An input terminal, a second input terminal connected to the comparator (22), and an output terminal connected to the address counter (10), and the modulated triangular wave does not cross the frequency command signal. Transmitting the clock pulse of the clock oscillator (21) to the address counter (10) in response to the output of the comparator (22) indicating that the modulated triangular wave crosses the frequency command signal. A gate circuit (20) formed to block transmission of the clock pulse to the address counter (10) in response to an output of the comparator (22), 1st and 1st 2 memories (M1, M
2) and when the modulated triangular wave does not cross the frequency command signal, the first memory (M
1) outputting the valued voltage vector data, and outputting the zero voltage vector data of the second memory (M2) when the modulated triangular wave crosses the frequency command signal. Select gate means (11, 12, 1
3, 15) and the switching elements (A1, A2, B1, B2, C1) of the three-phase inversion circuit (5) based on the data selected by the selection gate means (11, 12, 13, 15). And a drive circuit (8) for driving ON / OFF of C2).