JPH0191669A - Inverter device - Google Patents

Abstract

PURPOSE:To miniaturize a device and to make sine wave with better approxima tion efficiency by controlling the number of clock pulses to be inputted to an address counter in proportion to angles. CONSTITUTION:A frequency converter is such that a three phase full-wave rectifier circuit 4 is connected to three phase AC power lines 1-3, and a reactor 6 and a condenser 7 for removing high frequency noises caused by a power inverter circuit (inverter circuit) 5 are connected to the output step. The said inverter circuit 5 is driven by a control signal at a driving circuit 8. ROM 9 is provided and is provided with the first memory M1 in which a PWM switch pattern for making a PWM control of the inverter circuit 5 is written in advance, the second memory M2 in which zero vector is written and the third memory M3 in which velocity control data are written. In addition, the first and the second comparators 14 and 22, an address counter 10 and others are provided, and the number of clock pulses to be inputted to the counter 10 are controlled in proportion to angles. According to the constitution, an inverter output voltage waveform is controlled to make an approximate sine waves.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DC-AC converter device, that is, an inverter device, and more particularly to an inverter device that can relatively easily obtain a desired AC waveform. .

[Conventional technology]

A system in which the presence/absence voltage vector and the zero voltage vector are written in a predetermined order in a memory and sequentially read out by an address counter is disclosed in Japanese Patent Application No. 47875/1983.

[Problem that the invention seeks to solve]

However, the above-mentioned application does not describe a more specific method for vector readout control.

Therefore, an object of the present invention is to provide an inverter device that can easily obtain a sine wave or a desired waveform with good approximation.

[Failure to solve the problem]

To achieve the above object, the present invention includes an inverse conversion circuit that converts an input DC voltage into an AC voltage by intermittent pulse width modulation using a plurality of switching elements, and obtains an approximate sine wave voltage from the inverse conversion circuit. a memory in which valued and zero voltage vector data for collectively controlling the plurality of switching elements is written, an address counter for reading voltage vector data from the memory, and an address counter for reading voltage vector data from the memory; The present invention relates to an inverter device comprising: a clock oscillator for the clock oscillator; and means for changing the supply time width of the output clock pulse of the clock oscillator to the address counter in accordance with the angle of the inverter output waveform.

[For production]

By controlling the number of clock pulses input to the address counter according to the angle according to the above invention, the speed at which valuable voltage vectors and zero voltage vectors are read from the memory is controlled, and the inverter output voltage waveform is controlled, e.g. A desired waveform such as an approximate sine wave can be obtained.

〔Example〕

Next, a frequency conversion device according to an embodiment of the present invention will be explained. A three-phase full-wave rectifier circuit 4 in which diodes D1 to D6 are bridge-connected is connected to three-phase AC power lines 1, 2.3 connected to a commercial power source.

A filter for removing beam pull is not connected to the output stage of the full-wave rectifier circuit 4, and a glue handle 6 of about 1 to 2 mH is connected to the output stage of the full-wave rectifier circuit 4 to remove high-frequency noise caused by switching of the inverter circuit. A high frequency noise bypass capacitor 7 of about 5 μF is connected.

The PWM controllable three-phase inverter 5 includes switching elements A1. A2. B1.132° C1 and C2 are bridge-connected, and a diode D is connected in parallel to each switching element. The six switching elements A1 to C2 are turned on/f7 in response to a control signal supplied from the drive circuit 8.

Nao, six switching elements A on the upper side of inverter 5
1. B,, C1 and the lower three switching elements A
2. Since Bz-('2) operate inversely to each other.

- If 10,000 controls are specified, the control of the entire inverter is specified. Here, ROM (read only memory) 9
The first . Second. and the sixth signal A, 3
3. The overnight control state is determined from CIF-, and the switching elements A1. B1. CI runs, low bell i.e. logic
When the switching element AI is 0.

B1. Assume that el is off.

ROM 9 is a PW for PWM control of the inverter 5.
The first memo 17 M, in which the M switching pattern C unit vector data) is written in advance, the second memory M2, in which the zero vector is written, and the third memo 17 Mz, in which the speed adjustment data is written. have

The command memories M1 to M3 each have, for example, 512 addresses from O to 511, and are each addressed by the value of the 9-bit binary column of the counter 10.

The valuable vector of the first memory M1 and the zero vector of the second cr) memory Li□ are not output simultaneously, but are output alternatively. To perform this alternative control, the 5-bit output line of the first memory M+ is connected to the first AND gate 1.
1 and the OR gate 12 and connected to the drive circuit 8,
The 3-bit output line of the second memory M2 is connected to the second AN
The first AND gate 11 is connected to the drive circuit 8 via the D gate 13 and the OR gate 12, and the first AND gate 11 is connected to the first comparator 14.
The second AND gate 13 is controlled by the output of a NOT circuit 15 connected to the output of the first comparator 14. In addition, in Figure 1, for convenience of illustration,
First and second notes! J Ml, Mz output line.

First and second AND gates 11. The output line of '13 and the output line of OR gate 12 are shown as one line, but these are six signals A indicating the voltage vector,
, B, and C. It consists of three (6-pit) signal lines that transmit signals. As will become clear from the description below, the first and second memories M
1. The principle of controlling the switching elements A1 to C2 of the inverse conversion circuit 5 based on the value vector and zero vector of M2 is as follows.
This is the same as that disclosed in Japanese Patent No. 61-47875.

The drive circuit 8 includes five NOT circuits, and receives an input signal A.
, B, C are switching elements A1, B1 . Supplied to each base of CI, signals A and B in the NOT circuit.

A signal obtained by inverting C is sent to switching element A2. B2.
Supply each base of C2.

The first comparator 14 generates a binary output indicating whether to select a significant vector in the first memory Ml or a zero vector in the second memory M2, and this non-inverting input terminal is connected to the first comparator 14. It is connected to the voltage command signal line 17 via the pull compensation divider 16.

The inverting input terminal is connected to the input terminal 20 via the speed compensation modulation circuit 18.
It is connected to a kHz triangular wave generation circuit 19.

The input terminal of the address counter 10 is connected to a 4 MHz clock oscillator 21 via an AND gate 20. The AND gate 20 controls the passage of the a check signal, and this second input terminal is connected to the second comparator 22.
It is connected to the.

The non-inverting input terminal of the second comparator 22 is connected to the frequency command signal line 23, and the inverting input terminal is connected to the triangular wave generation circuit 19 via the modulation circuit 18. Next, the operating principle and each part will be explained in more detail.2 [Operating principle] Direct current that supplies a completely smoothed DC voltage 1! In a three-phase voltage type inverter connected to the
a+Vb+V. If we choose the neutral point voltage to be = 0, these instantaneous values become the space vector V = 2/3 (Va+Vb-e-j2''/3+Vo-
It can be expressed as an instantaneous space vector defined as e-""3). Depending on the switching state of the inverter.

There are a total of eight types of output instantaneous wall voltage vectors. Of these, Chino 2 (000) and V7 (T 11 ) are zero voltage vectors because their outputs are short-circuited. In order to obtain a sinusoidally symmetric three-phase AC output, the locus of the time-integrated voltage vector, that is, the magnetic flux vector, must also be circular! The inverter switches are selected so that the pressure vector follows a circle. Furthermore, even if the vector advances at a speed of one foot, the number of switching is greater at 00 degrees in Figure 4 than at 30 degrees, so the locus of the magnetic flux vector rotating at a speed proportional to the DC voltage is as shown in Figure 4. It is fast at 30 degrees and slow at 0 degrees, making it impossible to obtain a perfect sine wave. The parts where the velocity of the magnetic flux vector increases are 60 degrees, 90 degrees, 150 degrees, 210 degrees, 270 degrees, and 6 in Figure 4.
It is the 60 degree portion, and the portion where the speed is slow is in the middle of these portions. Therefore, this speed distribution becomes like a three-phase full-wave rectified U-shape of a three-phase inverter output. Therefore, in FIG. 1, 5-bit data a corresponding to the three-phase full-wave rectified waveform of the output voltage of the inverse conversion circuit 5 shown in FIG. 5(A) is written in the third memory M3Vc. In order to rotate the magnetic flux vector at a constant speed, the speed at which the voltage vector advances can be modulated to follow the reciprocal of the three-phase full-wave rectified waveform shown in Figure 5. The velocity modulation of this voltage vector is performed by using a multiplication DA converter (MD/A) in the modulation circuit 18 in FIG. By modulating the triangular signal (qb), inputting it to the second comparator 22, and comparing it with the frequency command signal C shown in FIG. , this is given to AND gate 20.

This is achieved by passing the clock signal only during the period when the comparison output shown in FIG. 5 is at a high level, as shown in FIG. In short, the fourth
In the vicinity of 60 degrees, where the rotation of the magnetic flux vector in the figure becomes faster, the number of input clock pulses per unit time length of 100 address counters is increased, and in the vicinity of 0 degrees, it is decreased. This makes the velocity of the magnetic flux vector constant around the circumference.

Note that when the zero vector of the second memory M2 is selected, the movement of the trajectory shown in FIG. 4 is stopped, and the movement is moved toward the center according to the time constant of the load, and speed adjustment is performed.

The above explanation has been about the case where a large capacity capacitor is provided at the input stage of the inverse conversion circuit 5 and a DC voltage with small ripple is inputted. On the other hand, if you input a DC voltage with ripple, ! The magnetic flux vector locus does not become a circle because the pressure vector moves quickly at the maximum value of the beam pull and moves slowly at the minimum value.

Therefore, in FIG. 1, the input DC line 24 of the inverse conversion circuit 5
A ripple detection line 25 is provided in the divider 16.
It is connected to the. The divider 16 divides the DC voltage command signal E+ applied from the line 17 by the ripple detection voltage e1 and outputs El/e+=d. The ripple-compensated voltage command signal d has a waveform shown in FIG. 5, 037, and is input to the first comparator 14. Note that the ripple detection voltage el includes a ripple when the three-phase voltages of the input power supply lines 1, 2, and 3 are full-wave rectified. In the first comparator 14, as shown in FIG.
The triangular wave signal shown in FIG. 31 is compared with the ripple-compensated voltage command signal d to generate a comparison output shown in FIG. The gate 11 becomes conductive and the valuable vector of the first memory Ml is output, and the second AND gate 13 becomes the si state in response to the low level of the waveform of Q (see FIG. 5). The zero vector of M2 is output.The time length for outputting the zero vector from the second memory M is proportional to El/el, and the output time of the zero vector becomes longer during the period when the ripple is large.

The speed of the voltage vector is corrected so that the voltage vector advances at a constant speed regardless of the input waveform ripple. Therefore, even if the input line 24 is not provided with a large smoothing electrolytic capacitor and only the bypass capacitor 7 for removing high frequency switching noise is provided, the output line 26°27.28 of the inverse conversion circuit 5 will have an approximate sine wave. voltage can be obtained.

Contents of CROM〕 ROM 9 Each l mo! J Ml, M2. Ms
VCnCnFigure 2 Data is written in accordance with the principle. That is, each of the memories M1 to M3 of the ROM 9 has, for example, addresses 0 to 511, respectively, and the addresses Q to 3 of the first memory M1 have, for example, voltage spectra AV6. Vg,
Ve.

6-bit data (A, B, C) of Vg are written in order, and zero vector V7. VO, V7-VO data are written in order, and 5-bit data a corresponding to the full-wave rectified waveform of the three-phase output of the inverse conversion circuit 5 is written in the sixth memory M3 in order. ing. Vector data is also written to the remaining addresses 4 to 511 using the same principle as addresses 0 to 6. This is because the vector data of each address in FIG. 2 shows the principle.

This differs from the actual data. Now, let us show the actual voltage vector data of addresses 0 to 84 (corresponding to the 0° to 60° interval) of the first memory Ml.

Vg, Vg, Vg, Vg-Vz, Vg, Vg,
V,, Vg, Vg.

Vs, Vs, v6. v6. Vg, Vg, v
2. Vg, Vg, Vg-vs, v6. v6,
Vg, Vz, v2. Vz, Vz, Vz, V
g.

Vg, Vg, Vg, Vg, Vz, Vg, Vg
, Vg, Vx, Vg-Vg, Vg, v,,
Vg, Vg, Vg, Vg, Vg, Vg, Vg
.

v2. Vg, Vg, Vg, Vg, vz, V
g-v,, Vg, Vg-Vz-Vs, Vs, Vs
, V-s, Vg, Vg, Vg, Vg, Vg
-Vg-V3- v3. V3, ■1, Vz-Vg,
Vg, Vg, Vg, v,, V3. V3. Vs,
Naru to V3.

[Voltage Vector Figure 3 shows six voltage vectors V1 to V6 and two zero vectors V, , V,. Switching element A1.
The possible switching states of Bl and CI are (0
00), (001), (010), (011).

(100), (101), (110), (111) +
7) -8 Tuteal (') T, Ch woV. ,V+
, Vz, V3°V4. Let v, , Vs, and N'y be expressed. In the device of this embodiment,! Pressure vector V. ~v7 is written into the first and second memories M, , M2, and this is output as control data (A, B, C). 8 vectors V. ~V7 can be combined to obtain a sinusoidal output voltage and a rotating magnetic field vector.

[Vector selection]

FIG. 4 shows the selection of the voltage vector to obtain the rotating magnetic field vector φ1. In order to make the locus of the tip (end point) of the rotating magnetic field vector φl approach a circle, it is necessary to
The sixth and second vectors Vr,, Vg, in a 30° interval
The second and third vectors V in the 30° to 90° interval,
V3. The third and first vectors V3, V in the 90° to 150° interval, the first and fifth vectors V in the 150° to 210° interval, V5. The fifth vector in the 210° to 270° interval
and the fourth vector V5, V4, and the fourth and sixth vectors V4. in the 270° to 360° interval. Select V6. In the 360° to 30° section of FIG. 4 shown in principle, v6 and Vg are selected as valuable vectors, and zero vector V7 is selected when vector rotation is stopped.

When the output bit of the first comparator 14 is at a low level, the second memory M2 is selected, and when the output of the first comparator 14 is at a high level, the first memory M is selected. Second
During the period when the output of the comparator 22 is at a high level, the clock pulse passes through the AND gate 2o and is input to the address counter 1o.
input pulse. As a result, the value of n bits (9 bits) of the counter 10 is increased by the up operation, and the addresses of the first memory M1 are sequentially designated. However, the second
When the output of the comparator 22 becomes low level, the tally input of the address counter 10 is inhibited, and the address counter retains the current address designation. For example, if memory 812 is selected while vector V6 of memory M1 is being read at address 2 as shown in FIG. 2, zero vector V7 (111) at the same address 2 is selected. The zero vector V7 is already generated while the output of the first comparator 14 is at a low level, and when the comparison output returns to a high level, the clock pulse signal is again input to the counter 10, and the output of the counter 10 is incremented by one stage. , 1st
The voltage vector V2 (010
) is selected. Zero vector aVo(000) and V,
(111), the switch element AI-
A vector is selected that requires less switching of e2. 2 where counter 10 corresponds to decimal 1i00 to 511
After generating the base numbers, all voltage vector data from 0 to 360 degrees is read out, and the inverse conversion circuit 5 generates three-phase approximate sine wave voltages.

For example, a three-phase alternating current motor connected to lines 26, 27, 28 has a rotating magnetic field vector with a nearly circular trajectory.

[Experimental Results] ROM 9 contains 3 (switching patterns, ie, valuable vectors and zero vectors, every 50/2048 degrees).

Ripple data -it! Including, R=10.0. L=10
A mH load was connected to the output lines 26, 27, and 28, a 470 μF smoothing electrolytic capacitor was connected in place of the capacitor 70 in Figure 1, and the 2 inverse conversion circuit 5 was driven using simple PWM to output an approximate sine wave. Input power line 1, 2.3 in case
Input current waveform at .

DC voltage waveform of DC lines 24 and 25, output line 26
．． The output current waveforms of 27 and 28 were as shown in FIG. In addition, the input current waveform and DC voltage at the same position as in Figure 6 when a 5μF bypass capacitor 7 is connected without connecting a smoothing capacitor to the DC line 24 and the ripple detection line 25 and modulation circuit 18 are omitted. When the waveform and output current waveform were measured, they were as shown in Fig. 6 ω). When the input terminal, current waveform, DC voltage waveform, and output current waveform at the same position as in FIG. 6(4) were measured using the method according to the present embodiment shown in FIG. 1, the results were as shown in FIG. 6(C). As is clear from the comparison between the output current waveform in Figure 6 and the output current waveform in Figure 6, the circuit in Figure 1 produces an output that is qualitatively the same as when a smoothing capacitor is provided. Obtainable. Furthermore, it is possible to improve the input current waveform and input power factor. Moreover, not only can the smoothing capacitor be omitted, but the charging resistor and the switch that shorts it out can also be omitted.

The device can be made smaller.

[Modified example]

The present invention is not limited to the above-described embodiments, but can be modified, for example, as follows.

(a) Switching element A+ = FE as C2
T may also be used.

(b) The voltage command signal E1 may be output as an error between the output voltage and the reference value.

(C) The frequency command signal C may be controlled based on the output.

(d) Instead of the divider 160, a subtraction circuit may be used to form the ripple-compensated voltage command signal d.

(e) It can also be applied to the case where the capacitor 7 is a large-capacity electrolytic capacitor and a smooth −r+4 DC voltage is supplied to the inverse conversion circuit 5.

(f) The output of the triangular wave generating circuit in the circuit system of Japanese Patent Application No. 61-47875 may be modulated according to the angle of the inverter output waveform. That is, the output line 2 of the inverse conversion circuit 5 is connected to the frequency command signal line 23 in FIG.
The absolute value of the comparison output between the output of the speed detector of the AC motor connected to 6.27.28 and a reference value may be input. Note that a proportional-integral circuit is inserted in the comparison output line.

(g) Comparator 14 in FIG. 1 may be omitted and the output of comparator 22 may be input to AND gate 11.13.

〔Effect of the invention〕

As is clear from the above (according to the present invention), it becomes possible to easily control the output waveform of the inverse conversion circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a frequency converter according to an embodiment of the present invention, FIG. 2 is a diagram showing a part of the contents of the ROM in FIG. 1 in principle, and FIG. 3 is a diagram showing voltage vectors. FIG. 4 is a diagram showing the rotating magnetic field vector, FIG. 5 is a waveform diagram showing the state of each part in FIG. 1, and FIG. 6 is a waveform diagram of each part in FIG. 1 and a comparative example. 1.2.3... Power line, 4... Rectifier circuit, 5...
Inverse transformation [i15. 7... Bypass capacitor, 9
...ROM. 14...first comparator, 16...divider, 17...
-Voltage command signal line, 22...second comparator, 25
...Ripple detection line.

Claims (1)

[Scope of Claims] [1] An inverse conversion circuit that converts an input DC voltage into an AC voltage by intermittent pulse width modulation using a plurality of switching elements, and an approximate sine wave voltage from the inverse conversion circuit. a memory in which value and zero voltage vector data are written for collectively controlling the plurality of switching elements so as to obtain the voltage vector data; an address counter for reading voltage vector data from the memory; and the address counter An inverter device comprising: a clock oscillator for the clock oscillator; and means for changing a supply time width of an output clock pulse of the clock oscillator to the address counter according to an angle of an inverter output waveform.