JPS6338716B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention provides electronic devices such as computers,
The present invention relates to a method for visually displaying characters such as letters, symbols, numbers, etc., and more specifically, relates to a method for displaying characters that are larger than display digits. In the prior art, when the number of characters to be displayed is greater than the number of display digits, the characters are divided into a plurality of parts according to the number of display digits and are sequentially displayed in a plurality of times. In such prior art, no consideration is given to the meaning and ease of grasping the contents when visually read. Other prior art, for example, JP-A-52-
As shown in 79640, when the number of characters to be displayed is greater than the number of display digits, each character is sequentially shifted and displayed. Even in such prior art, it is extremely difficult to understand the meanings of multiple characters. In the present invention, the number of digits is larger than that which can be displayed on the display unit.
It is an object of the present invention to provide a display method that makes it easy to read the contents of a plurality of characters when displaying a plurality of characters. Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a front view of an electronic dictionary that displays information using the display method of the present invention. By inputting and operating a word or the like for which the user wants to know the meaning from the key input section K, the answer is displayed on the display section DSP. FIG. 2 is a block circuit diagram of the electronic dictionary shown in FIG. A key input section K, a display section DSP, a display control circuit DSC, and an external memory unit MU are connected to the central processing unit CPU.
Key strobe output terminal W of central processing unit CPU
By outputting key strobe signals from keys 1 to W8, a signal representing the operated key is applied from key input section K to key input terminals K1 to K4. The display unit DSP is a dot matrix type liquid crystal display with multiple digits, for example, 12 digits in this embodiment. Each display digit is provided with a segment electrode and a common counter electrode facing the segment electrode.
DSP is the output terminal H1 to H of the central processing unit CPU.
7 receives the counter electrode signal for selecting the counter electrode from the output terminals S1 to S of the display control circuit DSC.
Display is performed by receiving segment signals selecting segment electrodes from 126. The signals from the memory address output terminals BM1 and BL1 in the central processing unit CPU are sent to the memory digit address input terminals of the display control circuit DSC and the external memory unit MU, as described later.
The signals are input to BL2, BL3 and memory file address input terminals BM2, BM3, respectively. In Figure 2, these terminals are
The lines connecting BM1 to BM3 and BL1 to BL3 are shown as a single white line. central processing unit
Display/erase control signal output terminal DIS1 in CPU
The display/erase control signal DIS from the display control circuit DSC is applied to the display/erase control signal input terminal DIS2 of the display control circuit DSC as described later. This display/erase signal DIS
is a signal for controlling display or erasure on the display unit DSP. In the central processing unit CPU, display control circuit DSC, and external memory unit MU, data input/output terminals indicated by the same reference numeral DIO for simplicity are connected to each other. The central processing unit CPU, display control circuit DSC and external memory unit MU use the same reference sign RW for simplicity.
They are mutually connected to the read/write signal terminals indicated by . Bit cells F1 and F2 at specific positions of the output buffer register F provided in the central processing unit CPU
The signal from the display control circuit DSC chip selection signal input terminal CE1 and the external memory unit
Each chip selection signal is input to the MU chip selection signal input terminal CE2, and output buffer register F (see Figure 4).
The operation of either the display control circuit DSC or the external memory unit MU is selected depending on the contents of the bit cells F1 and F2 at a particular position. The external memory unit MU consists of random access memory. The display control circuit DSC has a display data storage unit DRM consisting of a random access memory. The above-mentioned display control circuit DSC is specifically shown in FIG. In this display control circuit DSC, the display data storage unit DRM includes an address decoder DC6.
is connected. This decoder DC6 is the memory digit address output terminal of the central processing unit CPU.
BL1 and memory file address output terminal BM1
The information obtained from these input terminals BL2 and
It is decoded from BM2 via address buffer AB. The read/write control circuit RWC receives a read/write signal obtained from the read/write terminal RW, and reads/writes information in the display data storage unit DRM via the data input/output terminal DIO. The display data storage unit DRM is the display unit DSP.
It has a display storage unit DM that stores 12 digits of content that can be displayed all at once. The stored contents of the display storage unit DM are given to the segment driver SED. The display elements of each digit in the display section DSP are activated by signals from output terminals S1 to S126. When the display/erase control signal DIS from the input terminal DIS2 is logic "1" (hereinafter simply referred to as 1), the segment driver SED outputs a so-called ON waveform, causes the display unit DSP to display, and displays /When the erase control signal DIS is logic "0" (hereinafter simply expressed as 0), a so-called OFF waveform is output, and the display operation of the display unit DSP is stopped. FIG. 4 is a concrete block circuit diagram of the central processing unit CPU. The specific logic circuit configuration of the central processing unit CPU will be described below. Note that this central processing unit is a general-purpose unit, and therefore some of its functions are used in the present embodiment, and also includes functions and connection terminals that are not used in the present embodiment. RAM is a random access memory, and input/output is performed in units of 4 bits, and desired digit contents can be input/output by specifying the digit address and file address. BL is memory
RAM digit address counter, BL1 is its output terminal, DC1 is memory RAM digit address decoder, BM is memory RAM file address counter, BM1 is its output terminal,
DC2 is a file address decoder for the memory RAM, AD1 is an adder, which operates as a subtracter when a control command is given, and as an adder when no control command is given. Hereinafter, control commands are similarly represented by enclosing numbers. AD2 is an adder, G1 is a numerical value 1 in one input of adder/subtractor AD1
Or, it is a gate for giving either operand IA, and when control command (H) is given, it is 1, (h)
When , the operand IA is output. Here, "at the time of (h)" represents the time when the control command (h) is given,
This simplified expression will be used below. SB is a countdown circuit for the memory digit address counter BL. G2 is the input gate of the memory digit address counter BL;
When it is IA, it outputs the operand IB, and when it is , it outputs the output of the countdown circuit SB. G3 is a gate for supplying either the numerical value 1 or the operand IA to one input of the adder/subtractor AD2;
Outputs the number 1 when , and outputs the operand IA when . EO is memory file address counter
This circuit provides exclusive OR of the contents of BM and the contents of accumulator ACC to gate G4. The gate G4 is a memory file address counter BM.
The input gate outputs the output of adder AD2 when , the operand IA, the contents of accumulator ACC when , and the contents of EO when . G5 is a file selection gate of the memory RAM. DC3 is a decoder for operand IA, which decodes operand IA and inputs a signal specifying a desired bit of the memory RAM to gate G6. G6 is memory
This is an input gate for RAM, and when a control command is given, it inputs a binary 1 to the desired bit of the memory RAM specified by the operand decoder DC3, and when , it inputs the desired bit of the memory RAM specified by the operand decoder DC3. It has a built-in circuit that inputs a binary 0 to the accumulator.
Output the contents of ACC. N1 and N2 are flags for display control. G46 is an input gate for N1 and N2, and turns on when 〓〓. RWA is a read/write signal generation circuit, RW is its output terminal,
Read when , and write when .
ROM is read-only memory, PL is program
The counter specifies the desired step of the read-only memory ROM. DC4 is read-only memory
The step access decoder of the ROM, G7, is the output gate of the read-only memory ROM.
When J (abbreviated as FF) is set, transmission of the ROM output to the instruction decoder DC5 is cut off. DC5 is an instruction decoder that decodes the instruction code from the memory ROM.The instruction code in the memory ROM is divided into an operation code part IO and operand parts IA and IB. Control instructions corresponding to ~
〓〓 will occur. The instruction decoder DC5 also includes a circuit that determines that the instruction code from the memory ROM is an operation code accompanied by an operand, and outputs the operand IA or IB as is. AD3 is an adder that adds the value 1 to the contents of the program counter PL and causes it to count up. G8 is the input gate of the program counter PL, which outputs the operand IA when , and outputs the program stack register when .
Communicate the contents of SP. , 〓 and 〓〓 for gate G39, the output of adder AD3 is not transmitted. , 〓, 〓〓 The above transmits the AD2 output and automatically adds 1 to the contents of the program counter PL. FC is flag FF, G9 is flag FF. At the input gate of FC, the binary number is 1,
When , the purpose is to input binary 0 to each flag FFFC. G10 is a key signal generation gate, and when the flag FFFC is in the reset state (0), it is a memory digital address decoder.
The desired output of DC1 is output as is, and the flag is
When FF FC is in the set state (1), a circuit is built in that sets the outputs of I1 to In all at once, regardless of the DC1 output. CG is clock generator, DV
is a frequency dividing circuit, H is a display counter, BP is a counter electrode signal generation circuit for the liquid crystal display, and H1 to H7 are counter electrode signal output terminals. ACC is an accumulator consisting of 4 bits, X is a temporary (temporary storage) register consisting of 4 bits, and G1
1 is the input gate of the temporary register X, which transmits the contents of the accumulator ACC when 〓〓, and transmits the contents of the stack register SX when 〓〓.
AD4 is an adder, which is used to perform binary addition of the contents of the accumulator ACC and other data. 2
During advance addition, if a carry occurs in the addition of the fourth bit, the carry signal from the highest order bit, that is, the fourth bit, that is, the fourth bit carry C4 is set to 1. C is a carry FF, G12 is an input gate of the carry FF C, and when a control command is generated, if the fourth bit carry C4 is 1, 1 is input to the carry FF C, and if the fourth bit carry C4 is 0, Kyari FF
It has a built-in circuit that inputs 0 to C, and when
When 1 is input to FF C, 0 is input to the carry FF C. G13 is a carry FF C input gate for causing the adder AD4 to perform binary addition including the carry, and transmits the output of the carry FF C to the adder AD4 at the time of 〓〓. G14 is an adder
The input gate of AD4 transmits the output of the memory RAM when 〓〓, and the operand IA when 〓〓. F
is an output buffer register consisting of 4 bits,
G15 is an input gate of the output buffer register F, which transmits the contents of the accumulator ACC and inputs it to the output buffer register F at the time of . SD is an output decoder that decodes the contents of the output buffer register F and outputs the display body segment signal SS.
This is for converting from 1 to SSn. W is an output buffer register, and SHC is a shift circuit for the output buffer register W that operates to shift all bit contents of the output buffer register W by 1 bit to the right at once. G16 is the input gate of the output buffer register W, and the first gate of the output buffer register W when .
This is to input 0 to the first bit of the output buffer register W when 1 is input to the bit, and 0 is input to the first bit of the output buffer register W. It is assumed that the circuit SHC operates and the input is made after shifting. NP is the output control flag FF, G17 is the input gate of the output control flag FF NP, input 1 when it is 〓〓, and input 0 when it is 〓〓. G18 is an output control gate of the output buffer register W, and is used to output the outputs of each bit of the output buffer register W at the same time only when the flag FFNP is set to 1. The output signal of this output buffer register W can be used as a keystrope signal. IV1 to IV4 are inverter circuits, and G19 is an input gate of the switch FFJ, which is used to transmit the state of the input KN1 to the switch FFJ at the time of 〓〓. however,
Since it is passed through inverter IV1, when KN1=0, the output of the jumper FFJ is 1 (hereinafter referred to as jumper FFJ).
The fact that the output of J is 1 is abbreviated as J=1). G20 is the input gate of Jatsuji FF J,
At the time of 〓〓, the state of input KN2 is transmitted to the switch FFJ. However, since it is passed through the inverter IV2, J=1 when KN2=0. G21 is the input gate of jersey FF J, and input KF when 〓〓.
This is for transmitting the state of 1 to J. However, since it is passed through the inverter IV3, J=1 when KF1=0. G22 is an input gate of the switch FFJ, and is used to transmit the state of the input KF2 to J at the time of 〓〓. However, inverter IV
4, so J=1 when KF2.
G23 is an input gate of the switch FFJ and transmits the state of the input AK to J at the time of 〓〓. A.K.
When J=1, J=1. G24 is Jatsuji FF J
This input gate is used to transmit the state of the input TAB to the switch FFJ at the time of 〓〓.
When TAB=1, J=1. G28 is a joke
This is a gate for setting FFJ, and is used to input 1 to the switch FFJ at the time of 〓〓. V1 is a comparison circuit and a memory digit address counter.
Compare the contents of BL with predetermined data,
If they match, an output of 1 is generated, and the circuit operates when 〓 or 〓 is generated. Data to be compared is output from gate G26. G26
is the comparison value input gate to the comparison circuit V1, and the comparison value
n1 corresponds to a specific address value on the higher side that is often used for memory RAM control. The comparison value input gate G26 outputs n1 to use as a comparison value when ≦, and outputs n2 to use as a comparison value when ≦. G27 is the input gate of the jumper FFJ, and when the content of the carry FFCR is 1 when 〓〓, 1 is input to the jumper FFJ. DC6 is operand IA
The decoder decodes the operand IA and stores it in memory.
It is used to determine whether the content of a desired bit in RAM is 1 or not. G28 judges the bit contents specified by the operand decoder DC6 of the memory RAM.
This is the gate that transmits to FF J, and operates when 〓〓.
Make sure that J=1 when the specified bit of RAM is 1. V2 is a comparison circuit that judges whether the contents of the accumulator ACC and the contents of the operand IA are equal, and generates an output of 1 when they are equal.
It works when . V3 is a comparison circuit that compares the contents of the memory digit address counter BL and the operand.
It checks whether the contents of IA are equal and generates output 1 when they are equal, and operates when 〓〓.
V4 is a comparison circuit that judges whether the contents of the accumulator ACC and the contents of the memory RAM are equal, and generates an output of 1 when they are equal. G29 is a transmission gate of the fourth bit carrier C4 to the jumper FFJ, and transmits C4 to the jumper FFJ when 〓〓. When C4=1, J=1. FA is flag flip-flop, G31 is flag FF FA
The input gate outputs 1 when 〓, and 0 when 〓〓. G32 is an input gate for the flag FFJ, which sets FFJ when the flag FFFA is 1. FB is flag FF, G33 is flag FF
The input gate of FB outputs 1 when 〓〓, and 0 when 〓. G34 is an input gate of the flag FFJ, which transmits the contents of the flag FFFB to FFJ, and operates when ≦. G44 is a joke
This is the input gate of FF J, which transmits the contents of input α, and is operated by 〓〓. When α=1, J=1. G35 is the input gate of Jatsuji FF J,
It transmits the contents of input β and operates by. When β=1, J=1. G45 is the output gate of the accumulator ACC, which displays the contents of the accumulator ACC when 〓〓.
Transmit data to DRM data input/output terminal DIO. G
36 is the input gate of the accumulator ACC,
When , the output of adder AD4 is transmitted, and when 〓〓, the contents of accumulator ACC are inverted and transmitted by inverter IV5. The input gate G36 transmits the contents of the memory RAM when 〓〓, transmits the contents of the operand IA when , and inputs K1 to K4 when .
When ≦, the contents of the stack register SA are transmitted, and when ≦, the data from the display data storage unit DRM is transmitted from DIO.
IV5 is an inverter circuit, and SA is a stack register whose output is led out of the system. The output of SX is led out of the system using a stack register. G37 is an input gate of the stack register SA, which transmits the contents of the accumulator ACC when ≓. G38 is the input gate of the stack register SX, which transmits the contents of the temporary register X when ≓. SP is the program stack register,
G39 is an input gate of the program stack register SP, which is used to input the contents of the program counter PL plus 1 by the adder AD3 into the program stack register when ≓. Next, the table below shows an example of the instruction code stored in the memory ROM of the central processing unit CPU, its instruction name, operation content, and control commands generated based on the instruction code. In the table, A: Instruction code;
B: instruction name, C: content, D: control command for the central processing unit CPU. Some control instructions include an operand code following an instruction code.

【table】

【table】

【table】

[Table] Explanation of control command contents 1 SKIP Do not execute the next program step command.
Only the program counter PL is incremented, essentially skipping. 2 AD Performs binary addition of the contents of the storage unit ACC and the contents of the memory RAM, and adds the addition result to the storage unit.
Enter in ACC. 3 ADC accumulator ACC, memory RAM, carry
Add the contents of FF C in binary and input the addition result to the accumulator ACC. 4 ADCSK Accumulator ACC, memory RAM, carry
The contents of FF C are subjected to binary addition, and the addition result is input to the accumulator ACC.If the fourth bit carry C4 occurs as a result of this addition, the next program step is skipped. 5 Contents of ADI accumulator ACC and operands
Binary addition of IA and addition result to accumulator
In addition to inputting to ACC, the fourth
If bit carry C4 occurs, the next program step is skipped. 6 Set the DC operand IA to 1010 (decimal number 10),
As with the ADI instruction, by adding the contents of the accumulator ACC and this operand IA in binary, the contents of the accumulator ACC are essentially added.
Add the decimal number 10 and put the result in the accumulator
Enter in ACC. 7 Set SC carry FF C. (In other words, input 1 to the carry FF C.) 8 RC Reset the carry FF C. (In other words, input 0 to the carry FFC.) 9 SM Decodes the contents of the operand IA and sets the desired bit in the memory specified by the operand. (In other words, input 1.) 10 RM Decodes the contents of operand IA and resets the desired bit in the memory specified by the operand. (In other words, input 0.) 11 COMA Invert the contents of each bit of the accumulator ACC, take the 15's complement, and input it to the accumulator ACC. 12 Introduce operand IA to LDI accumulator ACC. 13 L Inputs the contents of the memory RAM into the accumulator ACC and inputs the operand IA into the file address counter BM. 14 LI Loads the contents of the memory RAM into the accumulator ACC and inputs the operand IA into the memory file address counter BM. Furthermore, the memory digit address counter BL is increased. However, the content of BL is a predetermined value n1
If it is equal to , skip the next program step. 15 LD Inputs the contents of the memory RAM into the accumulator ACC and inputs the operand IA into the memory file address counter BM. Furthermore, the memory digit address counter BL is decreased. However, when the content of the counter BL is equal to the predetermined value n2, the next program step is skipped. 16 X Exchanges the contents of memory RAM and the contents of accumulator ACC, and inputs operand IA to memory file address counter BM. 17 X1 Exchanges the contents of memory RAM and the contents of accumulator ACC, and inputs operand IA to memory file address counter BM.
Furthermore, memory digit address counter BL
to increase. However, when the content of this counter BL is equal to the predetermined value n1, the next program step is skipped. 18 XD Exchange the contents of memory RAM and the contents of accumulator ACC, and input operand IA to memory file address counter BM.
Furthermore, memory digit address counter BL
bring down. However, when the content of the counter BL is equal to the predetermined value n2, the next program step is skipped. 19 LBLI Input to operand IA and memory digit address counter BL. 20 LB Operand IA is input to memory file address counter BM, and operand IB is input to memory file address counter BL. 21 ABLI Performs binary addition of the contents of memory digit address counter BL and operand IA, and stores the addition result in memory digit address counter BL. However, when the contents of the counter BL are equal to the predetermined value n1, the next program is skipped. 22 ABMI Performs binary addition of the contents of memory file address counter BM and operand IA, and stores the addition result in counter BM. 23 T Input operand IA to program step counter PL. 24 SKC Carry FF If C is 1, skip the next program step. 25 SKM Deciphers the contents of operand IA, and if the desired bit in the memory specified by the operand is 1, skips the next program step. 26 SKBI Compares the contents of the memory digit address counter BL and the operand IA, and if they are equal, skips the next program step. 27 SKAI Accumulator ACC contents and operands
Compare IA and if equal, skip next program step. 28 SKAM Accumulator ACC contents and memory RAM
The contents of the program are compared, and if they are equal, the next program step is skipped. 29 SKN1 When input KN1 is 0, skip the next program step. 30 SKN2 When input KN2 is 0, skip the next program step. 31 SKF1 When input KF1 is 0, skip the next program step. 32 SKF2 When input KF2 is 0, skip the next program step. 33 SKAK When input AK is 1, skips the next program step. 34 SKTAB When input TAB is 1, skips the next program step. 35 SKFA Flag FF When FA is 1, skips the next program step. 36 SKFB Flag FF When FB is 1, skips the next program step. 37 WIS Shifts the contents of the output buffer register W by 1 bit to the right and inputs 1 to the first bit (most significant bit). 38 WIR Shifts the contents of the output buffer register W by 1 bit to the right and inputs 0 to the first bit (most significant bit). 39 NPS Output buffer register W output control
Set FF NP. (In other words, input 1.) 40 NPR Output buffer register W output control
Reset FF NP. (In other words, input 0.) 41 ATF Transfers the contents of accumulator ACC to output buffer register F. 42 LXA Load the contents of accumulator ACC into temporary register X. 43 XAX Exchanges the contents of accumulator ACC with the contents of temporary register X. 44 SFA Flag FF Sets FA. (i.e. 1
Enter. ) 45 RFA Flag FF Reset FA. (In other words, enter 0.) 46 SFB Flag FF Sets FB. (i.e. 1
Enter. ) 47 RFB Flag FF Reset FB. (In other words, input 0.) 48 SFC Set the input test flag FF FC.
(In other words, input 1.) 49 RFC Input test flag FF Reset FC. (In other words, input 0.) 50 SFD Set the input test flag FF FD.
(In other words, input 1.) 51 RFD Input test flag FF Reset FD. 52 SFE Sets input test flag FF FE.
(In other words, input 1.) 53 RFE Resets the input test flag FF FE. (In other words, input 0.) 54 SKA When input α is 1, skip the next program step. 55 SKB When input β is 1, skips the next program step. 56 KTA Accumulate the contents of inputs K1 to K4.
Introduced to ACC. 57 STPO Loads the contents of accumulator ACC into stack register SA and the contents of temporary register X into stack register SX. 58 EXPO Exchanges the contents of accumulator ACC and stack register SA, and exchanges the contents of temporary register X and stack register SX. 59 TML Transfers the contents of program counter PL plus 1 to program stack register SP. Furthermore, operand IA is introduced into the program counter PL. 60 RIT Transfers the contents of program stack register SP to program counter PL. 61 LNI Transfer operand IAIB to display control flag. 62 READ Introduces data input from the outside to the terminal DIO to the accumulator ACC. 63 STOR Outputs the contents of accumulator ACC to terminal DIO. 64 EX Exchanges the contents of the memory RAM and the contents of the accumulator, and puts the exclusive OR of the operand IA and the contents of the memory file address counter BM into the counter BM. 65 DECB Counts down the contents of memory digit address counter BL. However, when the contents of the counter BL are equal to a predetermined value n2, the next instruction is skipped. Next, Table 2 shows the relationship between the operation codes and operands stored in the read-only memory ROM in the central processing unit CPU.

【table】 〓

Claims (1)

[Scope of Claims] 1. A plurality of display characters, which are larger than the total number of display digits of the display unit, are sequentially displayed on the display unit, with the last character as a delimiter, and are first displayed in all of the display digits. a first display step in which characters that can be displayed are displayed all at once, starting from the first character; the state displayed in the first display step;
a second display step for maintaining the character for a predetermined first time; a third display step for displaying the character by continuously shifting the character at a second time interval after the second display step; a fourth display step for displaying a display including the last character by detecting a certain last character to be displayed, and maintaining that state for a predetermined third time; A display method characterized in that the display steps are repeated in this order, and the second time is set shorter than the first and third times. 2. The method according to claim 1, characterized in that when the display is repeated from the fourth display step to the first display step, the display is switched to a non-display state before moving to the first display step. Display method.