JPS6338324A - Gate array with addressing circuit - Google Patents

Abstract

PURPOSE:To facilitate evaluation and analysis of troubles by applying a proper input signal to an input terminal of an IC even in a state where the IC is set onto a substrate and therefore outputting the state of an optional cell within the IC to an output terminal. CONSTITUTION:The cells formed with sets of transistors are arrayed on an IC chip in the form of a grid and a wiring connecting these cells is formed separately. Thus, a logic circuit is obtained. In such a gate array (IC), an input buffer 100 which inputs and holds a selection signal for one cell or a data signal is added together with the decoders (an X decoder 300 and a Y decoder 200) which inputs a selection signal and decodes it to select one of cells, and an output buffer 600 which holds and then inputs the cell selected by the decod er. Thus, it is possible to easily detect the output of the part where a malfunc tion is suspected in a defective analysis mode.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a custom IC, and particularly to a gate array that can be easily designed and tested. [Prior Art] Generally, when converting an existing or newly designed logic circuit into an IC, it is known that a method using a gate array is an easy method.
When performing evaluation and failure analysis of gate arrays, special I
Unless a C tester is used, it is not possible to see the status of internal terminals other than the output signal terminals of the IC. [Problems to be Solved by the Invention] As described above, in conventional gate arrays, it is not possible to easily see the state of the internal cells, which creates significant restrictions in evaluating and failure analysis of gate arrays. The purpose of the present invention is to test the gate array (I
By applying an appropriate input signal to the input terminal of C), the state of any cell in the IC is outputted to the output terminal, thereby facilitating IC evaluation and failure analysis. [+ stage for solving the problem] The gate array with addressing circuit of the present invention has a cell carrier, which is the minimum component constituting a logic circuit that realizes a simple function, that is, a cell array, and a gate array (I).
C) An input cover that converts the level etc. of an electrical signal input from the outside into a form that can be handled inside the IC, a decoder that decodes an address signal given from the outside to select only one cell, and an inside of the IC. It has an output buffer that converts the level of the signal sent out from the motor and amplifies the current so that it can drive a high load. [Example] The present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of an embodiment of the present invention. In the existing gate array, signals from outside the IC are input to the input terminal T.
1, perform electrical level conversion etc. using a human cover and fiber 100, and connect 1T electrical wiring between multiple cells through the signal line 10. The result of the logic operation performed here is sent to the output terminal T2 via the output buffer 600 that performs electrical interface matching with the circuit outside the IC. It will be done. In addition to the above functions, the present invention has the following functions. Among the input terminals T], in addition to the input terminals for realizing the functions of the gate array 1, there is also an input terminal for an address signal for specifying a unique cell among a plurality of cells (cell array 400). There is a book. That is, all cells in the cell array 400 are assigned a local address, which is designated by n address signal lines. The value of n must satisfy the relationship: total number of cells times 2°. The above n number of address signal lines are divided into two, and an X decoder 30 is connected via a signal line 30.
0, goes to the Y decoder 200 via the signal line 20. Then, based on the result of decoding the address signal line, the cell array 40
0 is selected, and the output of the cell, that is, the state value of the cell is sent to the sense amplifier 5 through the X decoder 300.
00, where the analog electrical signal is amplified. The amplified signal is sent to the output buffer 600, where it is matched with an external circuit in the same way as a general signal received from the cell array section 400, and electrical level conversion, current amplification, etc. 0 is output from the output terminal T2 to the outside of the IC.Next, indignant at Figure 2, I started working in detail on the cell, XY decoder, and sense amplifier circuit.

【explain. 410 in FIG. 2 is an embodiment of one cell. In reality, a plurality of these cells are connected vertically and horizontally to form a matrix and constitute the cell array 400. Now, the n address signal lines are divided into nx and ny lines (n=nx+ny), and each is connected to an X decoder. 300
and the Y decoder 200, the cell array section, 400 T)'! , line ('fj*))
In the i direction, cells 410 and equivalent to transmission gates 401 extend beyond K2ny1tal, and cells 410 and transmission gates 402 equivalent to 2°X or less are lined up in the column direction. Column selection signal X i - and U row A selection signal Y
J (i < 2nx, j < 2ny) are connected to an X decoder 300 and a Y decoder 200, respectively. Transmission is performed for columns where the only column selection signal Xi selected as a result of decoding nx signals (Xi locations) of the address signal lines by the X decoder 300 is "1" (high level). Gate 402 enters the 4s state. For other columns, the data lines are in a floating state. In addition, the signals of ny circles (X address) on the address signal line are also decoded by the Y decoder 200 in the same way as the X address, and as a result, the selected row retreating number Yj is rlJ (/-Irepel). The transmission gate 40] is opened for the row where ? is opened, and the data line is in a floating knob state for the other rows.One of the column selection signals Xi1 and ? The output of one cell is sent to the sense amplifier 500 through two transmission gates opened by the T selection signal Yj, where it is amplified and output to the output terminal via the buffer 600. If the gain of the cell is light, the sense amplifier 500 is not necessary.The single cell 410 in Figure 2 is a 0M08 circuit, and due to the wiring within the dotted line frame, a 2-input NAND circuit etc. In the present invention, the output node is connected to the input of the transmission gate 401 depending on the actual circuit (this is done using a CAD system).Also, in general, in a gate array, the part consisting of elements (transistors) Since it is divided into a channel part (wiring area) and a channel part (wiring area), it is necessary to increase the aluminum wiring layer by -1-1 or two layers for the column selection signal line and the row selection signal line. As explained, by making the gate array have the configuration of the present invention, it is possible to detect the output of the part that is thought to be malfunctioning in failure analysis, and the part that is thought to be related to it. It is possible to easily see the failure analysis and perform failure analysis more easily than before.Also, the gate array (I
In the tests for ff value and selection in C), deep logic parts, that is, internal logic circuits whose values do not appear at the output terminals unless a large number of test buttons are input from the input terminals of the IC, are tested. Since the output can be easily sent to the output terminal, it becomes possible to perform tests with a high failure detection rate even with short test bangs.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a gate array with an addressing circuit according to the present invention, and FIG. 2 is a partial circuit diagram thereof. 100...Incoming cover, F, 2oo...Y decoder, 300...X decoder, 400...
...Cell array, 500...Sense Anne 7', 6
00... Output power 0

Claims (1)

[Scope of Claims] A gate array in which a logic circuit is realized by arranging cells each consisting of a plurality of transistors in a grid on an IC chip and separately forming wiring connecting the cells, comprising: an input buffer that inputs and holds a selection signal or a data signal that selects one of the cells; a decoder that inputs and decodes the selection signal to select one of the cells;
1. A gate array with an addressing circuit, comprising: an output buffer that holds and transmits the output of the cell selected by the decoder.