JPS6337990B2 - - Google Patents
Info
- Publication number
- JPS6337990B2 JPS6337990B2 JP54005144A JP514479A JPS6337990B2 JP S6337990 B2 JPS6337990 B2 JP S6337990B2 JP 54005144 A JP54005144 A JP 54005144A JP 514479 A JP514479 A JP 514479A JP S6337990 B2 JPS6337990 B2 JP S6337990B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- dmi
- code
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010354 integration Effects 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
- H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes
Landscapes
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
【発明の詳細な説明】
本発明は伝送路符号としてDMI符号を用いた
パルス伝送方式等に用いられる回路に関し、特に
原符号を中継伝送路で生じた誤り信号と分離して
復号するDMI符号の復号回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit used in a pulse transmission method using a DMI code as a transmission path code, and in particular to a circuit for use in a DMI code that decodes the original code by separating it from an error signal generated on a relay transmission path. It relates to a decoding circuit.
DMI符号とは、第１図に示すように、２値の
情報系列の“１”に対して“１，１”，“０，０”
をバイポーラ則にしたがつて切りかえ、“０”に
対して“１，０”，“０，１”を直前の符号と反対
極性となるような変換を行なつた符号である。第
１図ａが原符号列であり、第１図ｂがDMI符号
列である。本符号から原符号は次のようにして得
られる。DMI符号列をＡ，Ａを1/2タイムスロツ
ト遅らせた符号列をＢとすると、ＡとＢの排他的
論理和の否定が原符号となる。このようにして復
調されたパルス列は、デユーテイ50％のRZ
（return to zero）信号であり、１タイムスロツ
ト内にて、常に一定位相で“０”となる部分があ
る。加えて、伝送路で誤りが発生する毎にこの
“０”の部分が“１”となる性質がある。従つて、
互いに180゜位相の異なるクロツクにて復調された
パルスを読み出すことによりデータ信号と誤り信
号とを分離できる。ところで、パルスを読み出す
ためのクロツクは、DMI符号識別に必要な２倍
の周波数のクロツクよりカウントダウンして得て
いるため、ここで、読み出された２系統のパルス
列のどちらが、データ信号であるかわからないこ
とに問題がある。 As shown in Figure 1, the DMI code is defined as "1, 1", "0, 0" for "1" in a binary information series.
is switched according to the bipolar rule, and "0" is converted to "1, 0" and "0, 1" to have the opposite polarity to the previous code. FIG. 1a is the original code string, and FIG. 1b is the DMI code string. The original code can be obtained from this code as follows. If the DMI code string is A, and the code string obtained by delaying A by 1/2 time slot is B, then the negation of the exclusive OR of A and B becomes the original code. The pulse train demodulated in this way is an RZ with a duty of 50%.
This is a (return to zero) signal, and there is a portion that is always "0" with a constant phase within one time slot. In addition, there is a property that this "0" portion becomes "1" every time an error occurs on the transmission path. Therefore,
Data signals and error signals can be separated by reading out pulses demodulated using clocks that are 180° out of phase with each other. By the way, since the clock for reading out the pulses is obtained by counting down from a clock with twice the frequency required for DMI code identification, it is difficult to determine which of the two pulse trains read out is the data signal. The problem is that you don't understand.
本発明の目的はこのような２系統のパルス列に
対してデータ信号と誤り信号とを判別するDMI
符号の復号回路を提供することにある。 The purpose of the present invention is to develop a DMI system that distinguishes between data signals and error signals for these two systems of pulse trains.
An object of the present invention is to provide a code decoding circuit.
次に本発明について図面を用いて詳しく説明す
る。 Next, the present invention will be explained in detail using the drawings.
第２図は本発明の一実施例である。参照数字１
はDMI信号入力端子、参照数字２はクロツク信
号入力端子、参照数字３はNRZ（non−return to
zero）信号出力端子、参照数字４は誤り信号出力
端子、参照数字５は遅延回路、参照数字６は排他
論理和回路、同様にして７は互いに180゜位相の異
なる２つのクロツクを与えるゲート回路、８，９
はパルス読出し回路、１０，１１は積分回路、１
２はスイツチ制御回路、１３はスイツチ回路であ
る。 FIG. 2 shows an embodiment of the present invention. Reference number 1
is the DMI signal input terminal, reference number 2 is the clock signal input terminal, reference number 3 is the NRZ (non-return to
reference numeral 4 is an error signal output terminal, reference numeral 5 is a delay circuit, reference numeral 6 is an exclusive OR circuit, similarly 7 is a gate circuit that provides two clocks with a phase difference of 180 degrees from each other, 8,9
is a pulse readout circuit, 10 and 11 are integration circuits, 1
2 is a switch control circuit, and 13 is a switch circuit.
端子１からのDMI信号は遅延回路５により1/2
タイムスロツト遅延され、排他的論理和回路６に
てもとの２値RZ信号に変換される。各部信号の
タイムチヤートを第３図に示す。同図ａが入力
DMI信号、同図ｂが1/2タイムスロツト遅延され
た信号であり、同図ｃが前記回路６出力の復調信
号である。第３図のタイムチヤートにて斜線で示
す部分が中継伝送路で生じた誤りとする。復調信
号（第３図ｃ）はパルス読出し回路８，９におい
て位相の180゜異なる２つのクロツクにて識別され
る。識別された２系統の信号は、第３図ｄ，ｅと
なる。ここで、第３図ｄがもとのデータ信号であ
り、同図ｅが誤り信号である。次に、それぞれの
信号を積分回路１０，１１にて積分し、その出力
情報を用いて端子３に常にデータ信号を送出する
ように、スイツチ回路１３をスイツチ制御回路１
２によつて制御する。このようにすれば、無信号
の場合および誤りが極端に多い場合を除いてデー
タ信号と誤り信号を判別することができる。 The DMI signal from terminal 1 is halved by delay circuit 5.
The signal is delayed by a time slot and converted into the original binary RZ signal by the exclusive OR circuit 6. A time chart of each part signal is shown in Fig. 3. Input a from the same figure
The DMI signal, b in the figure, is a signal delayed by 1/2 time slot, and c in the figure is a demodulated signal output from the circuit 6. In the time chart of FIG. 3, the shaded portion is assumed to be an error occurring in the relay transmission line. The demodulated signal (FIG. 3c) is identified by two clocks having a phase difference of 180 DEG in the pulse readout circuits 8 and 9. The identified two systems of signals are shown in Figure 3 d and e. Here, d in FIG. 3 is the original data signal, and e in FIG. 3 is the error signal. Next, the switch circuit 13 is connected to the switch control circuit 1 so that each signal is integrated by the integrating circuits 10 and 11, and the output information is used to constantly send a data signal to the terminal 3.
2. In this way, it is possible to distinguish between data signals and error signals except when there is no signal or when there are extremely many errors.
本発明の一実施例の回路を第４図に示す。端子
１からのDMI信号は前記回路５，６によつて元
の符号に復号され、前記回路８，９により、デー
タ信号と誤り信号とに分離される。ここで、パル
ス読出し回路８からの出力がデータ信号とされ
る。このとき積分回路１０の出力は“Ｌ”（low）
レベル積分回路１１からの出力は“Ｈ”（high）
レベルとなる。前記回路１０，１１の積分回路は
抵抗１６又は１７およびコンデンサ１８又は１９
の構成により、パルス幅を広げて積分を行なつて
いる。次に前記回路１０，１１の出力情報によつ
てスイツチ制御回路１２は、リセツトされ、Ｑ出
力が“Ｌ”レベル、出力が“Ｈ”レベルとなり
これよりノアゲート２７，２８が閉じられ、ノア
ゲート２６，２９が開かれる。従つて、前記回路
８からのデータ信号は、ノアゲート３０を介して
端子３に出力される。加えて、パルス読出し回路
９からの誤り信号はノアゲート３１を介して端子
４から出力される。前記回路９からの出力がデー
タ信号の場合も同様にして、端子からデータ信号
が、端子４から誤り信号がそれぞれ出力される。 A circuit according to an embodiment of the present invention is shown in FIG. The DMI signal from terminal 1 is decoded into the original code by the circuits 5 and 6, and separated into a data signal and an error signal by the circuits 8 and 9. Here, the output from the pulse readout circuit 8 is used as a data signal. At this time, the output of the integrating circuit 10 is “L” (low)
The output from the level integration circuit 11 is “H” (high)
level. The integration circuit of the circuits 10 and 11 includes a resistor 16 or 17 and a capacitor 18 or 19.
With this configuration, integration is performed by widening the pulse width. Next, the switch control circuit 12 is reset by the output information of the circuits 10 and 11, and the Q output becomes "L" level and the output becomes "H" level, which closes the NOR gates 27 and 28, and the NOR gates 26, 29 will be held. Therefore, the data signal from the circuit 8 is outputted to the terminal 3 via the NOR gate 30. In addition, the error signal from the pulse readout circuit 9 is outputted from the terminal 4 via the NOR gate 31. Similarly, when the output from the circuit 9 is a data signal, the data signal is output from the terminal and the error signal is output from the terminal 4.
以上のように、本発明によりDMI符号を復号
する際の２系統のパルス列に対して、データ信号
と誤り信号とを判別して復号することのできる優
れた特性をもつ復号回路を得ることができる。 As described above, according to the present invention, it is possible to obtain a decoding circuit with excellent characteristics capable of discriminating and decoding data signals and error signals for two pulse trains when decoding a DMI code. .
なお、上記実施例のほかに、本発明の適用され
る装置の入出形態に応じて各種の変形例が考えら
れ、これらによつても同様に本発明を実施するこ
とができる。 In addition to the above-mentioned embodiments, various modifications can be made depending on the entry/exit form of the device to which the present invention is applied, and the present invention can be similarly practiced using these.
第１図ａ，ｂは単純２値符号からDMI符号へ
の符号化のタイムチヤート、第２図は本発明の一
実施例の構成図、第３図ａからｅはDMI符号か
ら元の２値符号への復号化のタイムチヤートおよ
び第４図は本発明の一実施例の回路図を示す。
第２図および第４図において、１……DMI信
号入力端子、２……クロツク信号入力端子、３…
…NRZデータ信号出力端子、４……誤り信号出
力端子、５……遅延回路、６……排他的論理和回
路、７……クロツク分配回路、８，９……識別回
路、１０，１１……積分回路、１２……スイツチ
制御回路、１３……スイツチ回路、１４，１５…
…ダイオード、１６，１７，２４，２５……抵
抗、１８，１９……コンデンサ、２０，２１……
電源端子、２６〜３１……ノアゲート、２２，
２３……トランジスタ。
Figure 1 a and b are time charts for encoding from a simple binary code to a DMI code, Figure 2 is a block diagram of an embodiment of the present invention, and Figures 3 a to e are a time chart of encoding from a simple binary code to a DMI code. A time chart of decoding into codes and a circuit diagram of an embodiment of the present invention are shown in FIG. 2 and 4, 1...DMI signal input terminal, 2...clock signal input terminal, 3...
...NRZ data signal output terminal, 4...Error signal output terminal, 5...Delay circuit, 6...Exclusive OR circuit, 7...Clock distribution circuit, 8, 9...Identification circuit, 10, 11... Integrating circuit, 12... Switch control circuit, 13... Switch circuit, 14, 15...
...Diode, 16,17,24,25...Resistor, 18,19...Capacitor, 20,21...
Power terminal, 26-31...Noah gate, 22,
23...transistor.
Claims (1)
排他的論理和回路とを有しDMI符号化された信
号を原信号に復号する復号回路と、この復号回路
により復号された信号を互いに180゜位相の異なる
クロツクで読み出す２つの読出し回路と、これら
の読出し回路からの２つの信号をそれぞれ積分し
該積分値をスイツチ制御のために使用する積分回
路と、この積分回路の積分値に基いて動作が制御
され積分値が大きい方の前記読出し回路の出力を
データ信号出力端に、積分値が小さい方の前記読
出し回路の出力を誤り信号出力端にそれぞれ切替
えるスイツチ回路とを有するDMI符号の復号回
路。1 In a DMI code decoding circuit, there is a decoding circuit that has a delay circuit and an exclusive OR circuit and decodes the DMI encoded signal into the original signal, and a decoding circuit that decodes the DMI encoded signal into the original signal, and a decoding circuit that decodes the signal decoded by this decoding circuit with a phase difference of 180° from each other. Two readout circuits that read out signals using different clocks, an integration circuit that integrates the two signals from these readout circuits and uses the integrated values for switch control, and operations that are controlled based on the integrated values of these integration circuits. and a switch circuit for switching the output of the reading circuit having a larger integral value to a data signal output terminal, and switching the output of the reading circuit having a smaller integral value to an error signal output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP514479A JPS5597764A (en) | 1979-01-19 | 1979-01-19 | Decoding circuit for dmi code |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP514479A JPS5597764A (en) | 1979-01-19 | 1979-01-19 | Decoding circuit for dmi code |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5597764A JPS5597764A (en) | 1980-07-25 |
| JPS6337990B2 true JPS6337990B2 (en) | 1988-07-27 |
Family
ID=11603098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP514479A Granted JPS5597764A (en) | 1979-01-19 | 1979-01-19 | Decoding circuit for dmi code |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5597764A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5952948A (en) * | 1982-09-20 | 1984-03-27 | Nippon Telegr & Teleph Corp <Ntt> | Code transmitting system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5244108A (en) * | 1975-10-06 | 1977-04-06 | Hitachi Ltd | Code error detection equipment |
-
1979
- 1979-01-19 JP JP514479A patent/JPS5597764A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5244108A (en) * | 1975-10-06 | 1977-04-06 | Hitachi Ltd | Code error detection equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5597764A (en) | 1980-07-25 |
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