JPS6337961B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic flux control device used for controlling the beam direction of a phased array antenna, and particularly to an operation check circuit thereof.

One method of controlling the beam direction of a phased array antenna is an invention entitled ``Linearity Magnetic Flux Control Circuit'' published in Japanese Patent Publication No. 11021/1973 on March 14, 1971. In the invention disclosed above, the magnetic body to be controlled is excited so that it becomes magnetically saturated and has a constant magnetic flux value unique to the magnetic body (such excitation is referred to as a reset operation in this specification), and from this magnetic flux value It was excited in the opposite direction so as to change the magnetic flux value by a predetermined amount commanded in advance. (Such excitation is referred to as a set operation in this specification) The above-mentioned predetermined amount commanded to each magnetic flux control device (hereinafter referred to as input data) is transmitted in a digital code, and is converted into an analog amount within each magnetic flux control device,
This becomes the reference voltage for the circuit that performs the above set operation.

In general, the signal transmitted as input data is not a digital number representing the above-mentioned reference voltage value itself, but a digital code corresponding to this digital number, and this digital code is used in each magnetic flux control device. A ROM (read-only memory) for reading the digital number representing the value of the corresponding reference voltage, and a digital-to-analog converter (hereinafter abbreviated as DAC) that converts the output of this ROM into analog to obtain the reference voltage. The above-mentioned ROM must be installed to generate the above-mentioned reference voltage.
The reference voltage specified by the input data signal may not be obtained due to a failure in the DAC circuit, a failure in the input data signal transmission path, or the like.

In such a case, the conventional device has the disadvantage that there is no device for checking whether the reference voltage value is incorrect, and the magnetic flux is set with respect to the incorrect reference voltage value.

The present invention eliminates the above-mentioned drawbacks of conventional devices, and provides an operation that allows online checking of whether the value of the reference voltage generated within each magnetic flux control device matches the voltage value commanded from the control signal generator. Its purpose is to provide a check circuit. In the magnetic flux control used to control the beam direction of a phased array antenna, in addition to checking the reference voltage value mentioned above, many operation checks are performed, and the results of these operation checks are transmitted to the signal line common to each magnetic flux control device. It is used dividedly and reported to the control signal generation section, and the signal line common to each magnetic flux control device is also required to be used in a time-sharing manner to transmit the signal for checking the reference voltage value mentioned above. Reduce the number of signal lines as much as possible.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block connection diagram showing the overall configuration of the present invention, and in the figure, 501, 502, . . .
50M are the first, second, ... M-th phase shifters, which are magnetic bodies inserted into each element of the array antenna, and 601, 602, ... 60M are the phase shifters 501, 502, respectively. ,...50M are magnetic flux control circuits that supply excitation current to the exciting coils 601, 602,...60M, respectively, and 30 is common to the magnetic flux control circuits 401, 402...40M. This is a control signal generator.

1 is all the magnetic flux control circuits 401, 402,
...40M, a starting signal line that transmits a common starting signal S _C , 2 is a control signal generating unit 30 that sequentially generates a reference voltage value corresponding to an input data signal from each magnetic flux control circuit.
4 is a common address signal line that sequentially transmits each address signal S _B to each magnetic flux control circuit in a time division manner. 5 is a common address signal line that transmits the value of magnetic flux to be generated for each magnetic flux control circuit. A common data signal line that sequentially transmits command input data signals S _D in a time-division manner; 6 indicates all magnetic flux control circuits 401, 402;
...This is a data reset signal line that transmits an input data reset signal S common to 40M.

Next, FIG. 2 is a block connection diagram showing one embodiment of the present invention, and shows only the portions of the circuit shown in FIG. 1 that are necessary for explaining the invention. In FIG. 2, 2, 4, 5, 30, and 401 indicate the same parts as the same reference numerals in FIG. 1, and S _B and S _D indicate the same letters and the same signals in FIG. 1. 7a is an address signal detection circuit; 7b is a decoder for comparing the input of the second type of digital signal; 8 is a data register; 9
a, 9b are ROM, 10a is DAC, 10
b is an analog-to-digital converter (hereinafter abbreviated as ADC); 14 is a set pulse width setting circuit; 30
32 is a NAND gate; 33 is a constant current output type voltage-current converter circuit (hereinafter referred to as VIC) that inputs the output voltage of the DAC 10a and outputs a current proportional to the input voltage.
), 34 is a diode, 35 is a transistor, 36 and 37 are fixed resistors, and 38 is an operation check circuit of the present invention.

Further, S _G is the address match signal output from the address signal detection circuit 7a, S _R is the voltage signal generated across the resistor 37 by the constant current output from the VIC 33, and S _ST is the voltage signal S _R that is digitalized by the ADC 10b. S CH indicates a conversion start signal that controls the timing of conversion into a number, and S _CH indicates a check operation instruction signal that controls the operation timing of the decoder 7b.

The input data signal S _D is a digital code corresponding to the reference voltage, the output of the ROM 9a is a digital number representing the value of the reference voltage, and the output of the DAC 10a is the reference voltage, which is converted into the current value on the report signal line 2. Thus, the transmitted voltage signal S _R is proportional to the value of the reference voltage, and the output of the ADC 10b is a digital number representing the reference voltage value. ROM9b is ROM9
It is a ROM whose input/output relationship is reversed to a, and inputs a digital number representing a reference voltage value and outputs a digital code corresponding to the reference voltage value. Therefore, the reference voltage signal S _T which is the output of ROM9b is 5→
8 → 9a → 10a → 33 → 34 → 2 → 10b → 9
If there is no failure during period b, the signal should be restored to the same digital code as the signal _SD .

The decoder 7b compares the signal S _D and the signal _ST , detects a match, and outputs it as an output signal S _N.

FIG. 3 is an operation time chart showing an example of the operation of each part in FIGS. 1 and 2, and FIG.
shows each address signal S _B , Fig. 3b shows each input data signal S _D , Fig. 3c shows the address matching signal S _G , and Fig. 3d shows the voltage corresponding to the output of DAC10a of each magnetic flux control circuit The signal S _R is the conversion start signal in Figure 3 e.
S _ST , Fig. 3 f shows the check operation instruction signal S _CH ,
FIG. 3g shows the output S _N of the decoder 7b.

The operation of the circuits shown in FIGS. 1 and 2 will be explained below with reference to FIG.

If there are a total of M magnetic flux control circuits as in the example shown in Figure 1, the address that specifies which magnetic flux control circuit among them is generally 2 ^m M>
It consists of m-bit binary codes with a relationship of 2 ^m-1 . Therefore, each address signal of m-bit configuration is
As shown in Figure a, signals from S _B1 (address signal of the magnetic flux control circuit 401) to S _BM (address signal of the magnetic flux control circuit 40M) are sequentially sent to all addresses in the magnetic flux control circuit via the address signal line 4 in a time-sharing manner. The signals are simultaneously input to the signal detection circuit 7a. A code corresponding to its own address signal is set in the address signal detection circuit 7a, and when the address signal input via the address signal line 4 matches this set code, an address match signal S _G is generated. Output. FIG. 3c shows the address match signal S _G output from the address signal detection circuit 7a in which the code of the address signal S _BK is set in the K-th magnetic flux control circuit. The address match signal S _G is input as a control signal to the data register 8, and at this time, the data signal line 5
The input data signal S _D that is input to the data register 8 via the data register 8 is stored in the data register 8.

As shown in Figures 3a and 3b, the data input signal S _D to each magnetic flux control circuit is sent out in synchronization with the corresponding address signal, so the data register is controlled by the address match signal S _G in Figure 3c. 8, the input data signal ( _SDK in the example of FIG. 3) to the magnetic flux control circuit is stored in the data register 8 in the magnetic flux control circuit.

As mentioned earlier, the input data signal S _D is not a digital number representing the voltage value of the reference voltage applied to the set pulse width setting circuit 14, but a digital code corresponding to this reference voltage, so the output of the data register 8 is inputted to the ROM 9a, converted into a digital number representing the voltage value of the reference voltage, inputted to the DAC 10a, where converted into an analog voltage, and inputted as the reference voltage of the set pulse width setting circuit 14.

After inputting each input data signal to all magnetic flux control circuits, the control signal generator 30 generates a start signal.
S _C is applied to the total flux control circuit via a starting signal line 1 (not shown in FIG. 2). All the magnetic flux control circuits are activated all at once to perform a magnetic flux reset operation and subsequently a magnetic flux set operation, and set the value of the magnetic flux bias to the value indicated by the input data signal stored in its own data register 8.

On the other hand, the reference voltage output from DAC10a is
It is converted into a constant current proportional to the voltage value in the VIC 33 and output to the diode 34 and the transistor 35. Here, the reset/set operation check circuit 31 checks the operation of the magnetic flux control circuit one step before, and outputs a logic "1" signal if the operation is normal. The output of the NAND gate 32 becomes logic "0" only when the reset/set operation check circuit 31 outputs a logic "1" signal and the address signal detection circuit 7a outputs the address match signal S _G. , turns off transistor 35. The output of the VIC 33 is controlled to a constant current proportional to the output voltage value of the DAC 10a regardless of its load impedance, so when the transistor 35 is off, the current is transmitted to the control signal generator 30 and fixed. The resistor 37 generates a voltage signal S _R with a voltage value proportional to the output voltage value of the DAC 10a. At this time, the output of the VIC 33 of the other magnetic flux control circuit is the signal S _G is logic "0", and therefore the output of the NAND gate 32 is logic "1", so it flows to the transistor 35 and to the common report signal line 2. does not flow. The diode 34 prevents the current of the VIC 33 output to the common report signal line 2 from flowing into other magnetic flux control circuits.

Regarding _the K _- th magnetic _flux control circuit in FIG.
10b is given the conversion start signal S _ST , and the voltage signal
S _R is converted into a digital number indicating the voltage value,
This digital number is input to the ROM 9b and converted into the same digital code S _T as the input data signal.

After a predetermined time required for analog-to-digital conversion in the ADC 10b, a check operation instruction signal S _CH is applied to the decoder 7b at time t ₂ ', and the input data signal S _DK at that time is compared with the output _ST of the ROM 9b. Only when the two completely match, the output signal S _N of the decoder 7b is output as logic "1", reporting normal operation.

Since the operation check circuit 38 of the present invention operates as described above, it can detect disconnection of the input data signal line 5, address signal detection circuit 7a, data register 8,
If the reference voltage corresponding to the input data signal S _D is not input to the set pulse width setting circuit 14 due to a failure of the components of the input data converter including the ROM 9a, DAC 10a, and VIC 33, or drift of component constants or operating points, or 1 If the reset/set operation before the step is not normal, the input data signal S _D and the corresponding output signal S _T of the ROM 9b will not match.
Therefore, the report signal line 2 common to each magnetic flux control circuit
It is possible to check the operation of each magnetic flux control circuit and the reference voltage value at the same time.

In the embodiment shown in FIG. 2, the output of the DAC 10a is transmitted in the form of a current using a voltage-current conversion circuit 33 that converts the output into a constant current proportional to the voltage value regardless of the load impedance. The voltage-current conversion circuit 33
Alternatively, it may be transmitted in voltage form using a voltage buffer circuit.

As described above, according to the present invention, checking of the reference voltage for setting the set pulse width in the magnetic flux control circuit and checking of other reset/set operations can be monitored online, and moreover, the reference voltage check for setting the set pulse width in the magnetic flux control circuit can be monitored online. Since it transmits a signal representing voltage, it has the advantage of being able to perform the necessary monitoring with a minimum number of wires.

[Brief explanation of the drawing]

Fig. 1 is a block connection diagram showing a comprehensive configuration of the present invention, Fig. 2 is a block connection diagram showing an embodiment of the invention, and Fig. 3 shows an example of the operation of each part in Figs. 1 and 2. It is an operation time chart diagram shown. 1 is a start signal line, 2 is a report signal line, 4 is an address signal line, 5 is a data signal line, 30 is a control signal generator, 401, 402,...40M are each magnetic flux control circuit, 7a is an address signal detection circuit , 7b is a decoder, 8 is a data register, 9a and 9b are each ROM, 10a is a DAC, 10b is an ADC, 14
31 is a set pulse width setting circuit, 31 is a set/reset operation check circuit, and 33 is a VIC. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] 1. Means for time-divisionally transmitting the address signal of each magnetic flux control circuit from a control signal generation section to a plurality of magnetic flux control circuits via a common address signal line, and a means for transmitting a common data signal line from the control signal generation section to a plurality of magnetic flux control circuits. means for transmitting the input data signal to each of the magnetic flux control circuits to the plurality of magnetic flux control circuits in a time division synchronized with the time division of the address signal; an address signal detection circuit that detects an address signal for the magnetic flux control circuit and outputs an address match signal; and an input data signal provided in each of the magnetic flux control circuits at the time when the address match signal is outputted among the input data signals. means for generating a control voltage that is an analog voltage having a predetermined value; and means for sending a common activation signal from the control signal generating section to the plurality of magnetic flux control circuits to instruct the plurality of magnetic flux control circuits to simultaneously activate the magnetic flux updating operation. Then, using this common activation signal, a reset operation is performed to saturate the magnetic flux to be controlled in each of the plurality of magnetic flux control circuits, and then a set operation is performed to reduce the magnetic flux by an amount corresponding to the control voltage. means, a reset/set operation check circuit provided in each of the magnetic flux control circuits for checking whether or not the reset operation and set operation have been performed normally and storing the result until the next activation signal; and each of the magnetic flux control circuits. Only when the memory of the reset/set operation check circuit provided in the magnetic flux control circuit indicates normal operation, the control voltage is sent to the control signal generator via the common report signal line until the address of the magnetic flux control circuit matches. means for transmitting in a time division manner determined by the output time of the signal, and in the control signal generating section, the value of the control voltage sent from each of the magnetic flux control circuits indicates a value corresponding to the input data signal of the magnetic flux control circuit. 1. An operation check circuit for a magnetic flux control device, comprising means for controlling the common start signal to be sent out only in certain cases.