JPH0512136A - Rom address controller - Google Patents

Abstract

PURPOSE:To confirm the operation of other than an erroneous ROM code by providing a comparator circuit. CONSTITUTION:A comparator circuit 15 comparing the output of a writable register 13 with the output of a program counter 12 is provided. Switching between an address to be outputted from an up-counter 14 jumping the output of the program counter 12 to the next address and the address to be outputted from the program counter 12 is performed with the output of the comparator circuit 15 by a multiplexer 16. Here, it is assumed that the ROM code of the n-th address of the program counter 12 is erroneous. In such case, when the n-th address is inputted to the register 13, the comparator circuit 15 outputs a coincidence signal when the output of the program counter 12 coincides with the output of the register 13. With the coincidence signal, the multiplexer 16 outputs the (n+1)-th address by means of the up-counter 14, and a ROM cell 11 outputs the contents other than the n-th address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read only memory (ROM), and more particularly to a ROM address control circuit.

[0002]

2. Description of the Related Art Conventionally, a ROM shown in FIG. 3 has been known as a ROM of this type, and an R storing a ROM code.
An address was supplied from the program counter 22 to the OM cell 21 to read the ROM code. In the conventional ROM development stage, when an error in the ROM code was found, the ROM code was corrected again and spread to correct the ROM code. As a result, product development has been delayed and user function confirmation has been delayed.

[0003]

In the above-mentioned technique, R
Even if you know that the OM code is incorrect, RO
Since M cannot be used and it has to be recreated from the beginning, there is a drawback that other circuits, functions and characteristics cannot be confirmed.

An object of the present invention is to provide a ROM address control device capable of confirming other operations.

[0005]

The ROM address control device of the present invention is erroneous when a memory cell section for holding a plurality of readable codes at each address and a program counter for designating an address of the memory cell section. A register that stores an address holding a code, an up counter that jumps the output of the program counter to the next address, and a multiplexer that supplies either the output of the up counter or the output of the program counter to the memory cell unit. , And a comparator circuit for comparing the output of the register with the output of the program counter and supplying a signal for selecting the output of the up counter to the multiplexer when they match.

Therefore, in the read-only memory device according to the present invention, the comparison circuit detects that the output value of the program counter and the output value of the register match, and the match / mismatch signals output from this comparison circuit are selected by the multiplexer. The output from the program counter or the output from the up counter is supplied to the address line in the ROM, and the functions and characteristics other than some erroneous codes can be confirmed without re-spreading. ..

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, the writable register 13 is used.
And an address output from the up-counter 14 and an address output from the program counter 12 that causes the output of the program counter to jump to the next address. Are switched by the multiplexer 16 according to the output of the comparison circuit 15.

Here, it is assumed that the ROM code at the n-th address of the program counter is incorrect. Therefore, when the n-th address is input to the register 13 and the output of the program counter 12 matches the output of the register 13, a match signal is output from the comparison circuit 15, and the match signal causes the multiplexer 16 to output the up-counter. The n + 1th address is output by 14 and the ROM cell 11
The contents other than the nth address are output from.

FIG. 2 is a block diagram of a second embodiment of the present invention, which has a logic gate 37 between the output of the comparison circuit 15 and the multiplexer 16 in the first embodiment.

If there is no error in the ROM code, TEST
By activating the MODE signal 38, the output of the multiplexer 36 is always the output of the program counter 32. If the ROM code has an error, the TEST MODE signal 38 is made inactive to output either the output of the program counter 32 or the output of the up counter 34 from the multiplexer 36 by the output of the comparison circuit 35.

[0012]

As described above, the ROM address control device of the present invention has the comparison circuit between the up counter and the address register and the program counter, thereby confirming the operation other than the erroneous ROM code. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional ROM.

[Explanation of symbols]

 11, 21, 31 ROM 12, 22, 32 Program counter (PC) 13, 33 Register 14, 34 Up counter (UC) 15, 35 Comparison circuit 16, 36 Multiplexer (MPX) 37 Logic gate 38 TEST MODE signal

Claims (1)

Claim: What is claimed is: 1. A memory cell section for holding a plurality of readable codes at respective addresses, a program counter for specifying an address of the memory cell section, and an incorrect code. A register storing an address, an up counter for jumping the output of the program counter to the next address, a multiplexer for supplying either the output of the program counter or the output of the up counter to a memory cell section, and the register Of the program counter and the output of the program counter are compared with each other to supply a signal for selecting the output of the up counter to the multiplexer when they match each other.