JP2009281860A - Method for testing semiconductor device and mask circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for testing a semiconductor device capable of corresponding to a case where there is no unused pin and capable of adding a function B to a test mode A without performing a logic change of the test mode A. <P>SOLUTION: The method is related to testing a semiconductor device. The semiconductor device includes a plurality of I/O pins 9, 10 to be connected to an external device, a test mode B using only a part of the I/O pins, the test mode A using all of the pins, a function C3 to be added to the test mode B, and a test mode switching key semaphore circuit 12 that temporarily stores a signal from the I/O pin 10 in unused pins in the test mode B during the power-on state. This method for testing includes a step of inputting a predetermined input signal from the I/O pin 10 and storing it in the test mode B and a step of executing the function C3 in the test mode A in accordance with the stored signal while maintaining the power-on state from the test mode B. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device test method and a mask circuit using a temporary memory circuit.

  In a semiconductor device, there is a pin multiplex as a method of sharing and using two input / output signals by one pin. Patent Document 1 describes a pin multiplex.

  FIG. 1 shows an example of a circuit configuration when a test is performed in the test mode A by additionally setting a function C and adding a test pin for the test mode A in the semiconductor device using the pin multiplex. It is.

  The shared pin 1 is connected to the multiplexer 2. The multiplexer 2 is connected to an additional pin 5 added for inputting a selection signal. The output section of the multiplexer 2 is connected to the function C3 and the test mode A4. The test mode A4 includes a logic function D8. The logic function D8 is connected to the existing pins 6 and 7, and signals are input and output through the existing pins 6 and 7.

  The multiplexer 2 has a function of selecting whether to set the shared pin as a pin for setting the function C3 or as an input pin in the test mode A4 according to the selection signal.

  When the test of the test mode A4 is performed by setting the function C3, the function C3 and the shared pin 1 are connected by the selection signal and the multiplexer 2. After setting the function C3, the test is performed by switching the shared pin 1 to the input terminal of the test mode A4 by the multiplexer 2 for the test of the test mode A4.

  However, in the configuration shown in FIG. 1, since the shared pin 1 is shared by the setting terminal for the function C3 and the input terminal for the test mode A4, the pin used in the test mode A4 is changed to the shared pin 1, It is necessary to newly add an unused pin as an additional pin 5 for a selection signal. However, the additional pin 5 cannot be added if there is no free pin when the test mode A4 is executed.

  As a method for dealing with this problem, there is a method in which a selection signal is output from the test mode A4 as shown in FIG. In FIG. 2, in the test mode A4, the selection signal output circuit 14 is added to the logic function D8. The logic function D8 and the selection signal output circuit 14 are connected to the existing pins 6 and 7 and the multiplexer 2, and have a function of giving a selection signal to the multiplexer 2 according to the setting input from the existing pins 6 and 7.

  When the function C3 is set and the test of the test mode A4 is performed, the function C3 and the shared pin 1 are first connected by the multiplexer 2 using the existing pins 6 and 7 and the selection signal output circuit 14, and the function C3 is set. Do. After setting the function C3, the test is performed by switching the shared pin 1 to the input of the test mode A4 by the multiplexer 2 in order to perform the test of the test mode A.

United States Patent patent No.US7,199,607, B2 date Apr.3,2007

  However, in the method shown in FIG. 2, since the selection signal is output using the existing pin in the test mode A4, it is necessary to change the existing logic function, that is, the test mode A4. Assuming that the test mode A4 has a track record with the previous generation product, there is a problem that it is not preferable to change the logic in the dark clouds because the reliability is lowered by changing the logic.

  The present invention has been made in order to solve the above-described problems, and does not require an additional pin, that is, can be used when there is no empty pin, and without changing the logic of the test mode A4. It is an object of the present invention to obtain a test method for a semiconductor device capable of adding a function C3 to the test mode A4. It is another object of the present invention to obtain a mask circuit using the circuit according to the present invention.

  The invention according to an embodiment of the present invention relates to a method for testing a semiconductor device, wherein the semiconductor device uses a plurality of pins for connecting to the outside and only a part of the plurality of pins. Test mode, a second test mode using all of the plurality of pins, a predetermined function added to the second test mode, and a signal from a predetermined pin among unused pins in the first test mode A temporary storage circuit for temporarily storing power on is provided. Further, in the first test mode, a step of inputting a predetermined input signal from an unused pin and storing it in the temporary storage circuit, and in the second test mode, the power is turned on temporarily from the first test mode while being kept on. A step of executing a predetermined function by a signal stored in the storage circuit is configured.

  A mask circuit according to an embodiment of the present invention includes a shift register circuit that sequentially stores an input signal according to a clock signal, a comparison circuit that compares a signal input to the shift register circuit with a signal recorded in advance, Means for maintaining the coincidence output from the comparison circuit by stopping the clock signal when the comparison coincides, a logic circuit for inputting the output of the comparison circuit and the masked signal and masking the masked signal according to the output of the comparison circuit It is configured with.

  In the semiconductor device test method according to an embodiment of the present invention, the circuit that inherits a set value of a predetermined function is preferably constituted by a shift register circuit and a comparison circuit. It is determined whether the signal recorded in the memory or the like and the signal from the I / O pin match bit by bit by the shift register and the comparison circuit. If they match, a predetermined function is set. When the number of signal bits to be matched in the comparison circuit is increased, the probability of matching is lowered, and when the function is not necessary, the function setting is not performed carelessly. When the clock signal is stopped in the state of coincidence, the set value is held in the shift register circuit. If the test mode is switched without turning off the power, the set value of a predetermined function can be inherited without an input signal. Therefore, it is not necessary to add an I / O pin in the second test mode by setting a predetermined function in the first test mode. In addition, since a predetermined function can be set only by this circuit, there is an effect that no logic change is required in the test mode after switching. If it is desired to perform the test in the second test mode without using a predetermined function, it can be realized by performing the test after turning off the power supply once to erase the inheritance information when switching the test mode.

  By using the mask circuit according to the present invention, after masking a masked signal, it is possible to maintain the mask signal without requiring an input signal.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
(Constitution)
FIG. 3 shows a schematic configuration diagram of the semiconductor device according to the present embodiment.

  The semiconductor device includes a plurality of pins for connecting to the outside, a test mode B (first test mode) using only a part of the plurality of pins, and a test mode A using all of the plurality of pins. (Second test mode).

  In FIG. 3, a plurality of pins in the test mode B indicate I / O pins 9 and 10, and some pins used in the test mode B indicate I / O pins 9. Accordingly, in the test mode B, the I / O pin 10 is vacant.

  Further, the semiconductor device temporarily stores a signal from a predetermined pin (in the present embodiment, the I / O pin 10) among unused pins in the test mode B while the power is turned on. A switching key semaphore circuit (temporary storage circuit) 12 is provided. The I / O pin 10 is connected to the test mode switching key semaphore circuit 12, and the test mode switching key semaphore circuit 12 is connected to the function C3. A function C3 indicates a predetermined function added in the test mode A.

  On the other hand, in the test mode A, all the existing pins 11 are used. The existing pins 11 indicate all pins including the I / O pins 9 and 10.

  In the test mode B of FIG. 3, only one test mode switching key semaphore circuit 12 connected to the function C3 is provided, but a plurality of test mode switching key semaphore circuits 12 may be provided. In that case, a plurality of I / O pins 10 to be connected are also provided.

  Next, the configuration of the test mode switching key semaphore circuit 12 will be described with reference to FIG.

  The test mode switching key semaphore circuit 12 is connected to the I / O pin 10 and the clock control unit 23, and sequentially stores the I / O pin signal input from the I / O pin 10 in accordance with the clock signal. Is provided.

  Also provided is a comparison circuit 20 connected to the shift register circuit 22 and the output section of a storage section (not shown) installed in the semiconductor device. The storage unit has a function of outputting a predetermined signal recorded in advance. The comparison circuit 20 has a function of comparing a signal input to the shift register circuit 22 with a signal recorded in advance in the storage unit. The output unit of the comparison circuit 20 is connected to the clock control unit 23. When the comparison is matched by the comparison circuit 20, the clock control unit 23 stops the clock signal to the shift register circuit 22 and outputs the coincidence output from the comparison circuit 20. Has the function to maintain.

  Further, an AND circuit 21 for inputting the output of the comparison circuit 20 and the reset signal is provided. The output part of the AND circuit 21 is connected to the function C3 shown in FIG. The output signal of the AND circuit 21 is a signal for controlling the setting of the function C3.

(Operation)
Next, a method for testing a semiconductor device according to the present embodiment will be described.

  As shown in FIG. 3, before adding the function C3 in the test mode A having no vacant pins, first, the test mode B having vacant pins is set. In the test mode B, a predetermined signal is input from the unused I / O pin 10 to the test mode switching key semaphore circuit 12.

  As shown in FIG. 5, the input signal is subjected to serial-parallel conversion by the shift register circuit 22, and the comparison circuit 20 determines whether or not each bit matches. When they match, the function setting value is output. That is, the low level signal is switched to the high level output signal.

  After the comparison circuit 20 determines that there is a match, the clock signal input to the shift register circuit 22 is stopped by the clock control unit 23. When the clock signal is stopped, the output of the shift register circuit 22 does not change and the register value is held, and the function setting value, that is, a high level signal is continuously output from the comparison circuit 20. That is, in the test mode B, a predetermined input signal is inputted from the unused I / O pin 10 and stored in the test mode switching key semaphore circuit 12.

  As for the AND circuit 21, while the reset signal is at the low level, the AND circuit 21 outputs the output signal of the comparison circuit 20, and when the reset signal is at the high level, outputs a signal fixed at the low level. Therefore, since the AND circuit 21 is connected to the output unit, the circuit can be reset by switching the test mode.

  While the reset signal is at the low level and the timing of the shift register circuit 22 is stopped and the comparison circuit 20 continues to output the high level signal, the AND circuit 21 also continues to output the high level signal.

  As shown in FIG. 3, the function C3 is set while a high-level signal is output from the test mode switching key semaphore circuit 12 in the test mode B.

  As described above, a plurality of test mode switching key semaphore circuits 12 and I / O pins 10 may be provided, and the function C3 may be set by a plurality of pins.

  After the function C3 is set, the output of the shift register circuit 22 is maintained unless the clock signal is input or the power is turned off, and the set value is inherited in the test mode switching key semaphore circuit 12. As shown in FIG. 3, the test mode is switched from the test mode B to the test mode A while the clock signal in the test mode switching key semaphore circuit 12 is stopped and the power is maintained.

  Thereafter, even if the input signal of the I / O pin 10 used for setting the function C3 is changed, the function C3 is maintained. Therefore, all the pins can be used while the function C3 is maintained. Therefore, it is possible to execute the test mode A that requires using all pins. That is, in the test mode A, the function C3 is executed by the signal stored in the test mode switching key semaphore circuit 12 while the power is turned on from the test mode B.

(effect)
In the present embodiment, the semiconductor device includes a test mode switching key semaphore circuit 12, and after setting the function C3, the clock signal of the shift register circuit 22 is stopped and the test mode is switched without turning off the power. , Function C3 is maintained. Therefore, the function C3 can be set without an input signal in the test mode A, and the number of I / O pins to be used can be reduced, and the function C3 can be set and tested even when there is no empty pin.

  Further, when performing the test in the test mode A without adding the function C3, the power is turned off once when the test mode is switched, and the information held in the shift register circuit 22 is deleted, so that the comparison circuit 20 does not determine the match. Setting values are not inherited. Thus, since the function can be set only by the test mode switching key semaphore circuit 12, there is an effect that the logic change in the test mode A is not required. When the number of signal bits to be matched by the comparison circuit 20 is 128 bits, the numbers match with a probability of 1/38. In this way, the probability of erroneous function setting can be reduced, and inadvertent function setting can be avoided when no function is required.

<Embodiment 2>
(Constitution)
The configuration of the test mode switching key semaphore circuit 12 according to the present embodiment will be described with reference to FIG.

  The test mode switching key semaphore circuit 12 includes a frequency dividing circuit 24 that is connected to the clock signal line output from the clock control unit 23 and the clock terminal of the shift register circuit 22 and divides the clock signal.

  Since the other configurations of the semiconductor device and the test mode switching key semaphore circuit 12 are the same as those in the first embodiment, detailed description thereof is omitted here.

(Operation)
Next, the operation of the test mode switching key semaphore circuit 12 according to the present embodiment will be described.

  As shown in FIG. 5, the clock signal output from the clock control unit 23 is frequency-divided by the frequency dividing circuit 24 and input to the shift register circuit 22. For example, in the case of a divide-by-4 circuit, a clock having a quarter frequency with respect to the original clock is input to the shift register circuit 22. The shift register circuit 22 operates based on the clock.

  Since other operations are the same as those in the first embodiment, a detailed description thereof is omitted here.

(effect)
When the signal input from the I / O pin 10 and the signal recorded in advance in the storage unit coincide with each other in the comparison circuit 20, the function setting value is output. If the power is not turned off, the output continues to be held unless the clock signal is transited. However, when glitch noise is mixed in the clock signal, the signal of the shift register circuit 22 changes and does not match in the comparison circuit 20, and the setting signal may not be held. In order to prevent signal transition due to this glitch, the frequency divider 24 is connected to the clock signal terminal of the shift register circuit 22. For example, when a divide-by-4 circuit is used, it is possible to withstand pulses due to glitches up to three times.

<Embodiment 3>
(Constitution)
FIG. 6 is a diagram showing a configuration of the high mask circuit 40 according to the present embodiment.

  The high mask circuit 40 includes a test mode switching key semaphore circuit 12. The test mode switching key semaphore circuit 12 has the same configuration as that shown in the first embodiment.

  That is, the shift register circuit 22 that sequentially stores the input signal according to the clock signal, the comparison circuit 20 that compares the signal input to the shift register circuit 22 with the signal recorded in advance, and the clock signal when the comparisons match Is provided with a clock control unit 23 for maintaining the coincidence output from the comparison circuit 20 by stopping.

  The High mask circuit 40 receives the output of the test mode switching key semaphore circuit 12 and the masked signal, and is an OR circuit 30 that is a logic circuit that masks the masked signal in accordance with the output of the test mode switching key semaphore circuit 12. Is provided.

(Operation)
Next, the operation of the mask circuit 40 will be described.

  While the same signal as the signal stored in advance is not input to the test mode switching key semaphore circuit 12 from the I / O pin, the output signal of the test mode switching key semaphore circuit 12 is at the low level. While the low level signal is input to the OR circuit 30, the masked signal input to the OR circuit 30 is output as it is as the output signal of the OR circuit 30.

  On the other hand, when the same signal as the signal stored in advance is input to the test mode switching key semaphore circuit 12 from the I / O pin, the clock of the test mode switching key semaphore circuit 12 is stopped and the test mode switching key semaphore 12 is stopped. The circuit 12 continues to output a high level signal. The high level signal is input to the OR circuit 30, and the OR circuit 30 outputs a high level signal regardless of the masked signal. That is, high mask processing is performed. Unless the power is turned off, the signal from the I / O pin is not used and the High mask circuit continues.

  When the power is turned off or the clock is shifted, the output of the test mode switching key semaphore circuit 12, that is, one of the inputs of the OR circuit 30 becomes Low and the input / output is the same. That is, the masked signal is output as it is as an output signal of the OR circuit 30.

(effect)
By using the test mode switching key semaphore circuit 12 as a high mask circuit, once set as a mask circuit, it is possible to continue outputting mask signals without using signals from the I / O pins.

<Embodiment 4>
(Constitution)
FIG. 7 is a diagram showing a configuration of the Low mask circuit 41 according to the present embodiment.

  The low mask circuit 41 includes a test mode switching key semaphore circuit 12. The test mode switching key semaphore circuit 12 has the same configuration as that shown in the first embodiment.

  That is, the shift register circuit 22 that sequentially stores the input signal according to the clock signal, the comparison circuit 20 that compares the signal input to the shift register circuit 22 with the signal recorded in advance, and the clock signal when the comparisons match Is provided with a clock control unit 23 for maintaining the coincidence output from the comparison circuit 20 by stopping.

  The Low mask circuit 41 receives the output of the test mode switching key semaphore circuit 12 and the masked signal, and performs AND processing on the masked signal according to the output of the test mode switching key semaphore circuit 12. Is provided.

(Operation)
Next, the operation of the low mask circuit 41 will be described.

  While the same signal as the signal stored in advance is not input to the test mode switching key semaphore circuit 12 from the I / O pin, the output signal of the test mode switching key semaphore circuit 12 is at the low level. While a high level signal is input to the AND circuit 31, the AND circuit 31 outputs a low level signal regardless of the masked signal. That is, low mask processing is performed.

  On the other hand, when the same signal as the signal stored in advance is input to the test mode switching key semaphore circuit 12 from the I / O pin, the clock of the test mode switching key semaphore circuit 12 is stopped and the test mode switching key semaphore 12 is stopped. The circuit 12 continues to output a high level signal. The high level signal is input to the AND circuit 31, and the masked signal input to the AND circuit 31 is output as it is as the output signal of the AND circuit 31.

  When the power is turned off once or the clock is changed, one of the outputs of the test mode switching key semaphore circuit 12, that is, the input of the AND circuit 31, becomes Low and becomes a Low mask circuit.

(effect)
By using the test mode switching key semaphore circuit 12 as a low mask circuit, it is possible to continue outputting a mask signal without using a signal from the I / O pin.

  The present invention is intended to add a new function after switching the test mode, but there is no free pin after switching the test mode, and the logic of the circuit cannot be changed, or there is no I / O pin that can be used after switching the test mode, and the high mask It can be applied to the case where it is desired to add a test with a low mask.

It is a circuit block diagram which shows an example of the prior art which concerns on test mode switching. It is a circuit block diagram which shows an example of the prior art which concerns on test mode switching. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a block diagram which shows the structure of the test mode switching key semaphore circuit which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the test mode switching key semaphore circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the mask circuit which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the mask circuit based on Embodiment 4 of this invention.

Explanation of symbols

  1 shared pin, 2 multiplexer, 3 function C, 4 test mode A, 5 additional pin, 6, 7, 11 existing pin, 8 logic function D, 9, 10 I / O pin, 12 test mode switching key semaphore circuit, 13 Test mode B, 14 selection signal output circuit, 20 comparison circuit, 21, 31 AND circuit, 22 shift register circuit, 23 clock control unit, 24 divider circuit, 30 OR circuit, 40 High mask circuit, 41 Low mask circuit.

Claims (7)

A method for testing a semiconductor device,
The semiconductor device includes:
Multiple pins to connect with the outside,
A first test mode using only a part of the plurality of pins;
A second test mode using all of the plurality of pins;
A predetermined function added to the second test mode;
A temporary storage circuit that temporarily stores a signal from a predetermined pin among unused pins in the first test mode during power-on,
In the first test mode, inputting a predetermined input signal from the unused pin and storing it in the temporary storage circuit;
In the second test mode, the step of executing the predetermined function by a signal stored in the temporary storage circuit while maintaining the power-on from the first test mode,
A method for testing a semiconductor device. The temporary storage circuit is
A shift register circuit that sequentially stores input signals according to a clock signal;
A comparison circuit for comparing a signal input to the shift register circuit with a signal recorded in advance;
Means for maintaining the coincidence output from the comparison circuit by stopping the clock signal when the comparison coincides,
A test method for a semiconductor device according to claim 1. The temporary storage circuit is
A frequency dividing circuit for dividing the clock signal;
A test method for a semiconductor device according to claim 1. The temporary storage circuit is
An AND circuit for inputting an output of the comparison circuit and a reset signal;
A test method for a semiconductor device according to claim 1. A shift register circuit that sequentially stores input signals according to a clock signal;
A comparison circuit for comparing a signal input to the shift register circuit with a signal recorded in advance;
Means for maintaining the coincidence output from the comparison circuit by stopping the clock signal when the comparison coincides;
A logic circuit that inputs an output of the comparison circuit and a masked signal and masks the masked signal according to the output of the comparison circuit;
Mask circuit. The logic circuit is an OR circuit, and the mask processing is high mask processing.
The mask circuit according to claim 5. The logic circuit is an AND circuit, and the mask process is a Low mask process.
The mask circuit according to claim 5.

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