JPS6337696A - Manufacture of circuit board - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a circuit board, particularly a dry process circuit board.

F Background Technology] Multilayer circuit boards are used as circuit boards that respond to the increasing integration of semiconductor devices and the increasing functionality, miniaturization, and cost reduction of electronic devices. Various studies have been conducted on plates using inorganic plates as substrates because they have excellent properties in terms of thermal strength and mechanical strength. When manufacturing a multilayer circuit board using such an inorganic substrate, circuit formation has conventionally been carried out by a paste method or an electroless plating method.

The paste method is performed by the process shown in Figure 97 (showing the multilayer method). First, a conductive paste 10 of copper, silver, gold, etc. is screen printed in a pattern shape on the surface of an inorganic substrate 1 such as an alumina substrate, and a circuit is applied. 7(a), (b)), heat-treat this (FIG. 7(c)), and then apply an insulating paste 11 such as 7 liters on the surface of the inorganic substrate 1 by screen printing. (Fig. 7(d)). At this time, the conductive paste 10 is connected to the pie hole 12 provided in the insulating paste 11.
A predetermined portion of the circuit is exposed, and after the insulating paste 11 is screen printed in this way, it is heat treated (FIG. 7(e)). And further insulating paste 11
A second circuit is applied by screen printing the conductive paste 10 in a pattern shape on the surface of the circuit (FIG. 7(r)), and heat-treated (FIG. 7(g)). At this time, the conductive paste 10 provided as the second circuit is The paste 10 is connected to the conductive paste 10 provided as the first circuit through the wire hole 12, and a two-layer circuit can be formed in a state where the paste 10 is connected through the wire hole 12. Thereafter, similar operations can be performed to form further multilayer circuits to obtain a multilayer circuit board.

Further, the electroless plating method is performed in the steps shown in FIG. 8 (showing a single layer). First, the surface of the inorganic substrate 1 such as alumina is treated with molten alkali or hot phosphoric acid to roughen the surface (Fig. 8(a), (b)), and then the inorganic substrate 1 is treated with P dC1.
Nucleation is performed to attach catalyst nuclei 13 such as Pd nuclei to the surface of the Wk machine substrate 1 by immersing it in a 2-solution (see Fig. 8(c)).
)) A copper conductor layer 14 is formed by electroless plating on the surface of the inorganic substrate 1 with the core attached (FIG. 8(d)). At this time, in order to thicken the conductor layer 1.t, A square-shaped etching lens 15 is provided on the surface of the sixth conductor layer 14, which is used in combination with plating, and a pattern mask 16 is formed.
8(e)), and then expose and develop to remove unnecessary portions of the etching resist 15 (see FIG. 8(f)).
)) Then, the portions of the conductor layer 14 that are not covered with the etching lens 15 are removed by etching using an etching solution (FIG. 8(g)), and the etching lens 15 is further removed (FIG. 8(g)). As shown in Figure (h), a circuit board can be obtained by forming a circuit using the conductor layer 14 by electroless plating.

However, since the paste method forms circuits by screen printing conductive paste 10 and insulating paste 11, there is a limit to miniaturization of patterning, and it is difficult to form circuits with a line width of 100 μm or less. However, there is a problem in that it is difficult to implement, and it is not possible to cope with the increase in the degree of integration of semiconductor devices. Furthermore, in the electroless 77-ki method, there are many processing steps such as surface roughening and catalyst nucleation for electroless plating, and it is necessary to control the temperature, pH, ion concentration, etc. of the plating solution, making the equipment larger and further plating. The cost of the plating solution is high, which poses problems in terms of manufacturing costs, and furthermore, residual ionic impurities such as P dC1 may cause problems in properties such as insulation and moisture resistance.

In the electroless plating method, a circuit is formed by etching the conductor layer 14 with an etching solution, but impurity ions due to the remaining etching solution may adversely affect properties such as insulation, or There is also the problem that the circuit becomes thinner due to the wraparound, making it difficult to form a precise circuit.

[Object of the Invention] The present invention has been made in view of the above points, and it is possible to form a circuit with a fine pattern without using a paste method or an electroless plating method, and shorten the manufacturing process. It is an object of the present invention to provide a method for manufacturing a circuit board, in which circuits can be formed without using an etching solution.

[Disclosure of the Invention 1] However, the method for manufacturing a circuit board according to the present invention covers the surface of an inorganic substrate 1 such as a ceramic plate or a metal plate with a mask 2 having holes in the shape of a circuit pattern. A conductor layer 4 is formed by a physical plating method such as evaporation, sputtering, or ion plating over the inside of the hole 3,
Next, the mask 2 is removed together with the conductor layer 4 on the surface of the mask 2, and the conductor layer 4 in the hole 3 of the mask 2 is left as a circuit 5 on the surface of the inorganic substrate 1.
The present invention will be explained in detail below.・! ! & Machine board board 1 It is made of lamic or metal plate, and ceramics include alumina, steatite (MgO-3io
□) etc. can be used, and when a metal plate such as an aluminum plate or a steel plate is used as the inorganic substrate 1, the surface needs to be insulated with a resin insulating layer or the like. To form a circuit on the surface of the inorganic substrate 1, the surface of the inorganic substrate 1 is first covered with a mask 2. The mask 2 can be formed, for example, by an organic film 24, and tIf
As shown in Fig. 12(a), it is preferable to line the back side of the fi-film A24 with metal foil 25 as a back metal.As the fi-film 24, polyimide (PI) or polyneech, which is easy to laser process, is used. ether ketone (PEEK), polyphenylene salt 7-fluoride (P P
S), polyester (PEs), polyamideimide (FAI), and other heat-resistant u4N, and metals [25] include AltjK, Fe1i, Ni foil, CrMSC, which have high laser reflectance and low cost.
The organic film 24 and the metal M25 are preferably laminated by thermocompression bonding, etc., and the front surface of the organic film 24 is coated with heat-resistant material such as polyimide or epoxy resin. No adhesive is applied.

And as shown by the arrow in Figure 2(b), is there? ! ! The film 24 is irradiated with laser light to form holes.

Since the laser beam is reflected by the metal M25, it acts only on the organic film 24, and holes 3 are formed in the organic film 24. Further, the hole processing is performed in accordance with the circuit pattern formed on the inorganic substrate 1, and the holes 3 of the circuit pattern are formed in the W1 film 24.

Organic film 2 with holes 3 in a circuit pattern like this
4 as a mask 2 to form a circuit on the inorganic substrate 1. First, an organic film 24 is adhered to the surface of the inorganic substrate 1 while the metal f'125 is laminated as a pack metal (FIG. 1(b)). Then, the metal M25 is peeled off and removed from the organic film 24 (FIG. 1(c)). In this way, the inorganic substrate 1 is covered with the mask 2 formed of the organic film 24. The inorganic substrate 1 is exposed in the circuit pattern in the hole 3 provided. Then, a conductor layer 4 is formed extending from the surface of the mask 2 to the surface of the inorganic substrate 1 within the hole 3 (Fig. 111(d)).
). The conductor layer 4 is formed by physical plating methods (P, V
, D: physical vapor dep
The conductor layer 4 formed by the physical plating method is formed using a conductor paste or metallization method, which eliminates the need for processing steps such as surface roughening and catalyst nucleation, which are required in the case of electroless plating. It has better adhesion to inorganic substrates such as ceramics than conductor layers formed by electroless plating, and the adhesion can be further improved when physical plating is applied to heated W&G substrates, and when sputtering is used. In order to further increase the adhesion, it is preferable to perform high-speed sputtering to coat at high speed.After forming the conductive layer 4 from the surface of the mask 2 to the surface of the inorganic substrate 1 in the hole 3 in this way, The mask 2 formed of the W1 film 24 is peeled off from the surface of the inorganic substrate 1 and removed. By peeling off the mask 2, the conductor layer 4 on the surface of the mask 2 is removed.
is also removed at the same time, and only the conductor /i14 formed in the hole 3 of the mask 2 remains on the surface of the inorganic substrate 1 as a circuit 5, and a circuit can be formed by the so-called 7-to-7 method (Fig. 1(e) )) In this way, the circuit 5 will be formed in the pattern of the holes 3 formed in the mask 2,
Circuit 5 compared to screen printing conductive paste
The pattern can be miniaturized and formed.

Furthermore, when manufacturing a circuit board as a multilayer circuit board, a photosensitive resin 6 is applied to the surface of the inorganic substrate 1 from above the circuit 5.
At the same time, a pattern mask 20 is set on the surface of the photosensitive resin 6.
a)) The photosensitive resin 6 is used to form an interlayer insulation layer, and the circuit 5 is completely covered with the photosensitive resin 6.

As the photosensitive resin 6, photosensitive polyimide, photosensitive epoxy resin, etc. can be used 6. Then, by exposing and developing, the photosensitive resin 6 is removed in the areas covered with the pattern mask 20 and not exposed to light, and the removed areas are removed. A predetermined portion of the circuit 5 is exposed as a pie hole 7 (FIG. 1(g) and FIG. 4(b)). Next, Figure 2 (a
) In the same manner as in (b), an organic film 24 with holes 3 formed in a circuit pattern as shown in FIG. 6 and also has extra P! 1 Peel off the metal [25] from the film 24 (Fig. 1 (h)), and 8! A second conductive layer 8 is formed by physical plating from the surface of the mask 2 formed by the film 24 to the surface of the photosensitive resin 6 in the holes 3 of the mask 2.
(FIG. 1(i)), at this time, a portion of the conductor layer 8 enters into the wire hole 7, and is integrally connected to the circuit 5 within the wire hole 7. After forming the second conductor layer 8 in this way, the organic film 24 is
The mask 2 formed by is peeled off from the surface of the photosensitive resin 6 and removed. When this mask 2 is peeled off, the conductor layer 8 on the surface of the mask 2 is also removed at the same time, and only the conductor layer 8 formed in the hole 3 of the mask 2 remains on the surface of the photosensitive resin 6 as a second circuit 9, and the circuit can be formed. The second circuit 9 has photosensitive resin 6 as an interlayer insulating layer to ensure insulation from the first circuit 5 shown in iq, and also has a pie hole 7.
The first circuit 5 and the second circuit 9 can be connected by this method, and in this way, a multilayer circuit board with a two-layer circuit configuration can be obtained (see FIG. 1(j) and FIG. 4(C)). )).

Here, the photosensitive resin 6 can be subjected to precise optical processing using photolithography technology, and the reliability of the interlayer connection between the circuits 5 and 9 can be ensured by the precisely formed pie holes 7. Furthermore, Figure 1 (
By repeating the steps f) to FIG. 1(j), a multilayer circuit board having a multilayer circuit structure can be obtained, and for example, a multilayer circuit board having a structure as shown in FIG. 5 can be manufactured. . In FIG. 5, a is a circuit serving as a power supply layer or a ground layer, and b to f are signal layer circuits of the first to fifth layers. It is best to form all of these signal layer circuits as microstrip lines, and using a microstrip structure like this makes it easier to set the characteristic impedance.
It is easy to match with mounted elements and parts, and ringing can be reduced.

In the multilayer circuit board obtained as described above, the circuit can be formed finely and precisely by the pattern of the holes 3 formed in the mask 2, but the line width W1 of the circuit is It is preferable to form the layer with a thickness of about 20 to 80 μm. In view of the limitations of laser processability, W is 2o.
It is difficult to make it less than μ, and if Wl exceeds 80 μ, the line width of the circuit is large, making it impossible to arrange circuits at high density. Also, the distance W2 between adjacent circuits in the same layer is 2
It is best to set it to about 4~120μ so that W 2 / W + is 1°2~1.5 -W z / W
By setting the + ratio within this range of 1.2 or more, it is possible to reduce the occurrence of cross strokes.

Furthermore, the line thickness T of each circuit is preferably set to 5 to 20 microns. 'If F1 is less than 5μ, electrical characteristics will deteriorate in terms of flow rate and circuit impedance, and making T1 more than 20μ is the limit of thickening the conductive layer using physical plating. This makes it difficult to form circuits with high density.Also, the interlayer spacing W2 of the circuits in each layer is set to 6 to 30μ, and W2
/W+ is preferably 1.2 to 1.5. (For Wl, W2, r1, and T2, each FAG
(Illustrated in Figures (a) and (b)) In the above, a mask 2 made of an organic film 24 was used, and holes 3 were formed in the mask 2 by laser processing. It is also possible to form using a renost such as a dry film resist or a liquid renost.

That is, the surface of the black iso substrate 1 is coated with renost, which is further covered with a pattern mask, and exposed and developed to remove a portion of the renost and form the holes 3 of the circuit pattern. In this way, the mask 2 is formed using the lenost with the ζ holes 3 (the state shown in Fig. 1(e) is obtained), and after the conductor /+! 4 is metal-lined using the physical plating method ( As shown in FIG. 1(d), the mask 2 made of lenost is dissolved in a solvent and removed.By dissolving and removing the mask 2 made of resist in this way, the surface of the mask 2 is removed. The conductor layer 4 is also removed at the same time, and only the conductor layer 4 formed in the hole 3 of the mask 2 remains on the surface of the inorganic substrate 1 as a circuit 5 (the state shown in FIG. 1(e)). In the following, the present invention will be specifically explained with reference to examples.

1" [L 96% purity alumina substrate (manufactured by Kyocera, size 75w
+ Kapton (with polyimide adhesive), and is lined with A1 metal foil 25 as the back metal. Then, a wiring pattern is drawn on mask 2 using a YAG laser,
A hole 3 is formed. This hole 3 is formed to have a line width of 50 .mu.m and a line spacing of 75 .mu.m, and a 100 .mu..phi. hole for forming a land etc. is also formed. After laminating the mask 2 on the inorganic substrate 1 in this way, the mask 2 is packed with Methano C metal! 25 was peeled off and copper was sputtered to form a conductor layer 4 (first eiffl(c
)(d)), where copper sputtering is performed using 8
Den 7 Nerva! JD, C magnetron type high speed sputtering vc1! (SPF-210H), vacuum level 6 x 10'-' Torr, Ar pressure 3 x 1
A conductor layer 4 having a copper thickness of 8 μm was formed under the following conditions: 0-T orr, output 600 V, 0.8 AS inorganic substrate temperature 200° C., and time 20 minutes. Next, the mask 2 is peeled off, the conductor layer 4 on the surface of the mask 2 is removed, and the holes 3 of the mask 2 are removed.
A circuit 5 is formed by leaving only a portion of the conductor layer 4 on the surface of the inorganic substrate 1.
was formed (Fig. 1(e)). The first layer circuit was formed as described above.

Next, as the photosensitive resin 6, photosensitive polyimide (DN-6) manufactured by Asahi Kasei Industries, Ltd. was used, and spin coating was performed on the surface of the inorganic substrate 1 from above the circuit 5 at 300 Orpm+ for 30 seconds to a film thickness of 20μ. It was applied in a clean open oven at 70°C for 2 hours (Fig. 1(f)). Next, the photosensitive resin 6 was exposed, baked, and developed at 140°C for 1 hour and 400°C in an N2 atmosphere.
℃ for 1 hour TFT], the photosensitive resin 6 was cured and formed as an interlayer insulating layer, and a part of the circuit 5 was exposed through the pie hole 7 formed in the photosensitive resin 6 (see Fig. 1). (g)). Here, the exposure is 2
200J/cII using a 50W supercommercial pressure mercury lamp12.
Baking was performed for 25 seconds, and baking was performed for 10 minutes in a clean oven at 70°C. Further, development was carried out using a special developer (A-135) for 100 seconds, and rinsing was performed for 60 seconds using a special rinse (C-200).

Thereafter, the steps of laminating the mask 2, sputtering copper, and peeling off the mask 2 are repeated in the same manner as described above to form a second layer of circuit 9.
Figure (j)), a circuit board with a two-layer circuit configuration was obtained.

- Using an alumina substrate similar to that in Example 1 as the inorganic substrate 1, the holes 3 formed in the mask 2 were formed with a line width of 25μ and a line spacing of 3.
Example 1 except that the diameter of the small hole for forming a land etc. was 50 μm.
A circuit board having a two-layer circuit configuration was obtained by carrying out the same process as above.

U As the inorganic substrate 1, a ST7 tie F substrate with a dielectric constant lower than that of alumina (manufactured by Kyocera, 50 x 50 x 0,63
A circuit board having a two-layer circuit configuration was obtained in the same manner as in Example 1. As with alumina, there was no problem in the adhesion of the substrate to the mask 2, the sputtered copper, and the photosensitive resin.

Dog 1'' [( Using an alumina substrate similar to that in Example 1 as the inorganic substrate 1, laminating the mask 2 in the same manner as in Example 1, and then depositing aluminum to a thickness of 8 μm using the vacuum evaporation method, a conductor layer 4 was formed. Here, in order to reduce heat radiation to the inorganic substrate, the vacuum evaporation was performed using an electron beam evaporation device at a vacuum level of 2 x 10' Torr, a temperature of the inorganic substrate 1 of 200°C, and a time of 10 minutes. The rest was carried out in the same manner as in Example 1 to obtain a circuit board having a two-layer circuit configuration.

and 1 Property 1 A photosensitive epoxy resin was used as the photosensitive resin 6, and the curing conditions were set to 100°C for 1 hour and 150°C for 1 hour.
A circuit board having a two-layer circuit configuration was obtained in the same manner as in Example 1.

K Crest 9 1 As the inorganic substrate 1, a 75m x 75a + m x 1mm aluminum plate with a polyimide insulating layer of 50μ thick on the surface was used, and the rest was carried out in the same manner as in Example 1 to obtain a circuit board with a two-layer circuit configuration. .

No 8! An alumina substrate similar to that in Example 1 was used as the substrate 1. On the surface of the inorganic substrate 1, Odeil manufactured by Tokyo Ohka Co., Ltd. was applied as a lenost to a thickness of 50 μm, and this was exposed and developed to obtain a line width of 50 μm and a line spacing. Hole 3 was formed in the lenost with a circuit pattern having a diameter of 75μ. A circuit board having a two-layer circuit structure was obtained in the same manner as in Example 1, except that the mask 2 was formed using lenost with holes 3 in this manner.

A circuit board with a two-layer circuit structure was fabricated in the same manner as in Example 1, except that an alumina substrate similar to that in Example 1 was used as the inorganic substrate 1, and the line width of the hole 3 of the mask 2 was set to 50 μm, and the line spacing was set to 60 μm. Obtained. In this case, the line width Wl of the circuit is 50μ
, the line spacing W2 was 60μ, and W2/W=1.2. Further, the thickness T1 of the circuit was 8 μ, the interlayer spacing T2 of the circuit was 10 μ, and T2/TI=1.25. Further, the pie hole 7 was formed as a truncated cone with a bottom surface of 50 μφ and a top surface of 100 μφ.

[Dog] Doctor L'' - A two-layer fabrication was carried out in the same manner as in Example 1, except that an alumina substrate similar to that in Example 1 was used as the inorganic substrate 1, and the line width of the hole 3 of the mask 2 was set to 25μ, and the line spacing was set to 30μ. A circuit board with a circuit configuration was obtained. In this case, the line width Wl of the circuit is 25μ
, the line spacing W2 was 30μ, and W2/W=1.2. *The thickness T of the circuit is 8μ, and the layer spacing of the circuit is 2
was 10μ, and T2/T=1.25. Furthermore, the pie hole 7 was formed as a truncated cone with a bottom surface of 25 μφ and a top surface of 50 μφ.

- Using an alumina substrate similar to that in Example 1 as the inorganic substrate 1, the line width of the hole 3 of the mask 2 was set to 25μ, the line spacing was set to 30μ, and the conductor layers 4 and 8 were formed by vapor deposition of Al. The pond was formed in the same manner as in Example 1 to obtain a circuit board having a two-layer circuit structure. In this case, the line width WI of the circuit is 25μ
, the line spacing W2 was 30μ, and W2/W+=1.2. Further, the thickness T of the circuit was 6 μ, the interlayer spacing T2 of the circuit was 9 μ, and T2/T=1.5. At ζ, the via hole 7 was formed as a truncated cone with a bottom surface of 25 μφ and a top surface of 50 μφ.

A two-layer fabrication was carried out in the same manner as in Example 1, except that the same steatite as in Example 3 was used as the inorganic substrate 1, and the line width of the hole 3 of the mask 2 was set to 50μ, and the line spacing was set to 60μ. A circuit board with a circuit configuration was obtained. In this case, the line width W1 of the circuit is 50μ
, the line spacing W2 was 60μ, and W2/W was 1.2. Also, the thickness T of the circuit is 8μ, and the layer spacing T2 of the circuit
was 10μ, and T2/T =: 1.25. Furthermore, the via hole has a bottom surface of 50μφ and a top surface of 10μφ.
It was formed by a truncated cone with a diameter of 0μφ.

An alumina substrate similar to that in Example 1 was used as the K1 1 mm inorganic substrate 1, the line width of the hole 3 of the mask 2 was set to 50μ, the line spacing was set to 60μ, and the photosensitive resin was made photosensitive in the same manner as in Example 5. A circuit board having a two-layer circuit configuration was obtained in the same manner as in Example 1 except that epoxy resin was used. In this device, the line width W of the circuit was 50 μ, the line spacing W2 was 60 μ, and W2/W was 1.2. Also, the thickness of the circuit T1
is 8μ, the layer spacing T2 of the circuit is 12μ, and T 2 /
T+=1.5. Further, the pie hole 7 was formed as a truncated cone with a bottom surface of 50 μφ and a top surface of 100 μφ.

As the inorganic substrate 1, a thickness of 50 mm is placed on the surface of an A1 plate with a thickness of 1-1.
Using a polyimide insulating layer of μ, this
A copper foil with a thickness of 9 μm is applied to the surface of the layer, and the circuit of the first layer is formed by etching the copper foil.
The circuits after the Gi were formed by laminating mask 2 in Figure 1 and battering with copper to obtain a circuit board with a multilayer circuit configuration.

[Effects of the Invention] As described above, in the present invention, the surface of an inorganic substrate such as a ceramic plate or a metal plate is covered with a mask having holes in the shape of a circuit pattern, and the holes are formed from the surface of the mask to the inside of the holes. A conductive layer is formed using a physical plating method such as vapor deposition, sputtering, or ion plating, and then the mask is removed along with the conductive layer on the mask surface, leaving the conductive layer in the hole of the mask as a circuit on the surface of the inorganic substrate. This method eliminates the problems of man-hours and other issues that arise when forming a conductor layer using electroless plating, and also allows circuits to be formed with high precision according to the pattern of holes formed in the mask. In the paste method, it is possible to form a circuit that is thinner than in the case of forming a circuit by screen printing. In addition, the circuit can be formed by removing the mask, and the circuit can be formed by a dry process that does not use an etching solution. This makes it possible to form circuits without problems such as thinning.

[Brief explanation of the drawing]

FIGS. 1(a) to (j) are schematic cross-sectional views showing each step in an embodiment of the present invention, FIGS. 2(a) and (b) are cross-sectional views of a mask, and FIG. 3 is a schematic cross-sectional view of a mask. Cross-sectional view of the mask, Figure 4(a)
(bOc) is a schematic perspective view of a part of the process in the same example, FIG. 5 is a schematic cross-sectional view of a multilayer circuit board obtained by the same process, and FIGS. line width and line spacing,
Schematic cross-sectional view schematically showing thickness and distance between eyebrows, Figure 7 (a
) to (8) and FIGS. 8(a) to (h) are sectional views showing respective process parts of the conventional example. 1 is an inorganic substrate, 2 is a mask, 3 is a hole in the mask, and 4 is a conductor layer.

Claims (3)

[Claims] (1) Cover the surface of an inorganic substrate such as a ceramic plate or metal plate with a mask that has holes in the shape of a circuit pattern, and perform physical plating such as vapor deposition, sputtering, or ion plating from the surface of the mask to the inside of the holes. 1. A method for manufacturing a circuit board, comprising forming a conductor layer by a method, and then removing the mask together with the conductor layer on the surface of the mask, so that the conductor layer in the hole of the mask remains as a circuit on the surface of an inorganic substrate. (2) The method for manufacturing a circuit board according to claim 1, characterized in that the mask is removed from the inorganic substrate together with the conductor layer on the surface of the mask by peeling the mask from the surface of the inorganic substrate. (3) The method for manufacturing a circuit board according to claim 1, characterized in that the mask is removed from the inorganic substrate together with the conductor layer on the surface of the mask by dissolving the mask.