JPS6337531B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to frequency divider circuits in electronic circuits, and more particularly to programmable frequency divider circuits.

A 1/n frequency divider is commonly used as a conventional frequency divider, but there are types with a fixed frequency division ratio and types with a variable frequency divider. The variable frequency divider consists of a binary flip-flop and a latch for setting the frequency division value.

On the other hand, a frequency divider that keeps the frequency constant and makes the duty variable is also known. In this frequency divider, an inverting circuit is added to the 1/n frequency divider. 1st
The figure shows an example of a variable duty frequency divider. Further, FIG. 2 is a time chart for explaining the operation of FIG. 1. Here, the preset value is (a) 0 (12
=0, 13=0) and (b)2 (12=0, 13=1). The operation shown in FIG. 1 will be explained with reference to FIG. 2. The frequency of the divided clock φ is divided by binary flip-flops 3 and 4 with reset. One state of this frequency division result is 00 (3Q=0, 4Q=0)
is detected by the AND gate 5, and the output of the AND gate 5 is read into the delayed flip-flop 6 which operates with the divided clock φ.
The output of the AND gate 5 hits the trigger flip-flop 7 and inverts the output of the trigger flip-flop 7. Furthermore, the positive phase output of delayed flip-flop 6 is applied to NAND gates 8 and 9 to control them. Furthermore, since the reverse phase output is applied to the AND gate 5, the output of the AND gate 5 does not become active (1) for more than two clocks of the divided clock φ. The outputs of the NAND gates 8 and 9 serve as reset signals for the binary flip-flops 3 and 4, respectively, and the positive phase output 60 of the delayed flip-flop 6.
When is active (1), the contents of data latches 12 and 13 are set in binary flip-flops 3 and 4 via inverting circuits 10 and 11 and NAND gates 8 and 9.
Codes are set in the data latches 12 and 13 by the processor 14 in advance. First, if the code is (a), 3Q=4Q=0 and AND gate 5=1
Then, the trigger flip-flop 7 is inverted. In the next clock cycle, 6Q = 1, so the NAND gates 8 and 9 become active after an appropriate delay in the delay circuit 15, but at this time, the clock φ is added in advance, so 3Q = 4Q = 1. . Also, if it is reversed to 7Q=0, data latch 12,
The outputs of 13 are inverted by inverting circuits 10 and 11 and both become 1, and the conditions are met by NAND gates 8 and 9, so that the outputs of NAND gates 8 and 9 both become 0. Therefore, both binary flip-flops 3 and 4 are reset so that 3Q=4Q=0. At this timing, the AND gate 5 is inhibited by the reverse phase output of the delayed flip-flop 6, so the output becomes 0.

In addition, the clock input signal of binary flip-flop 3 is 6Q, which is the OR gate 1 and the divided clock φ.
Therefore, binary flip-flops 3 and 4 do not change in the next clock cycle. Next, 6Q=0 again, so AND gate 5=1 again
Then, the trigger flip-flop 7 is inverted. In this cycle, 7Q=1, so the contents of data latches 12 and 13 are transmitted as they are to NAND gates 3 and 4. Next clock cycle 6Q
=1, so the NAND gates 8 and 9 become active, but since the outputs of the inverting circuits 10 and 11 are both 0, the outputs of the NAND gates 8 and 9 both remain 1. On the other hand, since the binary flip-flops 3 and 4 have 3Q=4Q=1 due to the clock φ at this time, they start counting down from this state from the next clock cycle. And again 3Q＝
When 4Q=0, AND gate 5 becomes 1 and the same operation as above is repeated. Next, the operation in case (b) is that for the first 6Q=1 in Figure 2, 3Q=0, 4Q=
1, the next 6Q=1, 3Q=1, 4Q=0. The operation is exactly the same as in operation (a), but when comparing the outputs of the trigger flip-flop 7, it can be seen that the wave numbers are the same and only the duty is different. That is, by changing the contents of the data latches 12 and 13, it is possible to obtain signals with the same wave number and different duties.

When this circuit is incorporated into, for example, a microcomputer, its duty can be freely changed by operating the controller 14 using software. However, in some application fields, the variable duty function is not necessary but a variable frequency signal is desired, or there are cases where it is desired to switch between the two. At this time, separately providing frequency variable hardware is extremely wasteful in terms of circuit configuration, leading to increased costs.

The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to improve the efficiency of hardware by making a variable frequency circuit and a variable duty circuit common and switching them using a control signal. .

The present invention includes a frequency divider in which a plurality of binary flip-flops are connected in cascade to divide an input clock signal, and a first gate that generates an output signal when the frequency divider reaches a predetermined value. a trigger flip-flop whose state is inverted by the output signal of the first gate circuit; and a delayed flip-flop which inputs the output signal of the first gate circuit in response to the clock signal. a latch circuit in which information to be preset in the frequency divider is stored; an inversion circuit that inverts the output of the latch circuit; and a signal obtained by delaying the output of the inversion circuit and the output of the delayed flip-flop. a second gate circuit which takes as an input and applies the output of the inverting circuit to a preset terminal of the frequency divider, and a third gate circuit which is opened and closed by a control signal to connect the output of the trigger flip-flop. applying the output of the trigger flip-flop to the inverting circuit when the third gate circuit is opened by the control signal;
A frequency-divided signal having a duty ratio according to the information stored in the latch circuit is obtained, and when the third gate circuit is in a closed state, a frequency-divided signal having a frequency according to the information stored in the latch circuit is obtained. It is characterized in that it can be obtained.

The present invention will be explained below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention. The composition is the first
It is the same as the figure, but a control gate 16 is inserted at the output of the trigger flip-flop. Here, if the control signal 17 which is the output of the controller 14 is "1", the output of the trigger flip-flop 7
Since 7Q is directly transmitted to the inverting circuits 10 and 11, the operation is exactly the same as in FIG. 1. Next, when the control signal 17 becomes "0", the output of the control gate 16 always becomes "0", and the inverting circuits 10 and 11 do not perform inverting/non-inverting operation but always become inverting circuits. Therefore, the contents of the data latches 12, 13 are always applied to the reset terminals R of the binary flip-flops 3, 4. The operation in this case is shown in Figure 4 (a) 12 = 0, 13
Two examples will be shown: =0, (b)12=0, and 13=1. Looking at the output 7Q of the trigger flip-flop 7, it can be seen that the frequency changes depending on the contents of the data latches 12 and 13. In this circuit example, the output frequency ₇₀ of the trigger flip-flop 7 is the frequency of the divided clock and the data latch 12,
With a frequency division value N of 13, it is expressed as ₇₀ = /2 (2 + N).

As explained above, according to the present invention, variable duty output or variable frequency output can be obtained by simply adding a control gate, and hardware with extremely high usage efficiency can be realized at low cost, which is highly effective.

Although 2 bits are used as the binary flip-flop in the explanatory diagrams of the present invention, the present invention is not limited to this, and the circuit configuration itself can of course be equivalently replaced with other circuits.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional circuit for obtaining variable duty output. FIG. 2 is an operational waveform diagram of FIG. 1. FIG. 3 is a circuit diagram according to the present invention.
FIG. 4 shows the operating waveforms of FIG. 3. 3, 4...Binary flip-flop, 6...
Delayed flip-flop, 7...Trigger flip-flop, 10, 11...Inverting circuit, 12,
13...Data latch, 14...Controller,
16...Control gate, 17...Control signal.

Claims (1)

[Claims] 1. A frequency divider in which a plurality of binary flip-flops are connected in cascade, which divides the frequency of an input clock signal, and a first gate circuit that generates an output signal when the frequency divider reaches a predetermined content. , a trigger flip-flop whose state is inverted by the output signal of the first gate circuit, and a delayed flip-flop that inputs the output signal of the first gate circuit in response to the clock signal. , a latch circuit in which information to be preset in the frequency divider is stored, an inversion circuit for inverting the output of the latch circuit, and a signal obtained by delaying the output of the inversion circuit and the output of the delayed flip-flop. a second gate circuit that applies the output of the inversion circuit to a preset terminal of the frequency divider; and a third gate circuit that applies the output of the trigger flip-flop to a preset terminal of the frequency divider; applying the output of the trigger flip-flop to the inverting circuit and applying it to the latch circuit when the third gate circuit is opened by the control signal; A frequency-divided signal having a duty ratio according to the stored information is obtained, and when the third gate circuit is in a closed state, a frequency-divided signal having a frequency according to the information stored in the latch circuit is obtained. A frequency dividing circuit characterized by the following.