JPS6337442A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To clearly demonstrate the validity or invalidity of tag memory data, to prevent an error due to random data and to speed up initialization by adding a V(validity) bit to data in a tag memory. CONSTITUTION:The V bit is added to a data Au in the tag memory 12, and it is assumed that data is valid and invalid according as '1' or '0' of the bit. Data in the memory 12 is read at an address Ad, and a read-out data RD is inputted to a comparator 14. It compares inputs RD and CD. If they are the same, a coincidence output S1 outputted to a NAND gate G. When the data in the memory 12 is read out at the address Ad, the V bit in a V bit part 12a is also read out, and an output S2 is inputted to the gate G. Even if the S1 is at a level H(coincidence output), the S2 comes to a level L with the V bit set to zero. Accordingly an output S3 is not outputted from the gate G, and 'OK' of reading data memory is not specified. Thus an error caused by random data is prevented, and initialization can be sped up by simultaneously clearing the V bits.

Description

[Detailed Description of the Invention] [Summary] A V bit is attached to each data in the tag memory, and this is initialized all at once when the power is turned on. From then on, each time data is written, that ■ bit is also corrupted, causing the data to become corrupted. Clarified valid/invalid.

[Industrial application field]

The present invention relates to a semiconductor memory device, and particularly to a tag memory for a cache memory of a computer.

[Conventional technology]

Computer memory (main memory) is a process.

Because they are connected through a bus and have a large capacity using DRAM (dynamic RAM), there is a problem of long access times. Using a memory, data read from the main criminal jQ is stored in a cache memory, and the same data is supplied from the cache memory to increase speed.

It is difficult to increase the capacity of the cache due to the use of SRAM (static RAM), etc., and the capacity of the cache is usually only a portion of the main memory. There are various ways to configure the main memory, but generally the main memory is made up of a plurality of books (blocks) each consisting of one, two, or four books. FIG. 3 shows a direct map type cache whose data memory has a capacity for one book, and FIG. 4 shows an associative type cache whose data memory has a capacity for two books. To give a numerical example, one sheet is 16 bytes, one sheet is 512 sheets, and the entire main memory is 524°288 sheets. In terms of address bits, it is A.

~ Select 1 byte (1 line) out of 16 bytes per sheet on A3,
Select 1 sheet out of 512 sheets in one book with A4~AI2, AI3~
Select 1 book out of 524.288 books in A31.

Data is stored in the cache in units of 16 bytes for one disk of main memory. The address to be stored is the same data memory address as the lower addresses A4 to AI2 in the main memory. However, with this alone, the one card is 524, 28 in the main memory.
Since it is not known which of the eight books the item was in, the upper addresses AI3 to A31 indicating this are stored in another memory (tag memory). Access the tag memory using the lower address, read the upper address, and save the memory (main memory).
Comparator COM
At P, it is compared with the upper address read from the tag, and if they match, it means that the required data is in the cache, so the lower address is read from the data memory of the cache and output.

FIG. 5 schematically shows the relationship between the main memory and the cache.

The main memory data is stored in 16-byte units at the same data memory address as the lower address A4 to AI2 of the main memory, and at the same time, the upper address A13 of the data memory is stored in the tag memory. ~A31 is written. In this example, the data memory has a capacity equivalent to four books in the main memory.

Therefore, in this example, up to four cards with the same lower addresses A4 to A12 can be stored in the cache.

The cache has the capacity for multiple books, but a certain address A
4 to A12 have already been stored, and in order to read out one sheet with the same address A4 to AI2 from the main memory and store it in the cache, it is necessary to purge what has already been stored. be. LRU is often used as this replacement algorithm.

[Problem that the invention seeks to solve]

The tag memory stores high-order addresses, and if the high-order address of the address that accesses the main culprit 4, a matches the high-order address read from the tag memory, the data in question is in the cache, but when the power is turned on, the memory data is is random. Therefore, if the main memory access upper address and the tag memory read data match by chance, the data will be in the cache, and there is a risk that the data will be read from the random data memory. . The present invention attempts to improve these points by simple means.

For this purpose, in the present invention, a V (Validity) bit is attached to the tag memory data (upper address) to clearly indicate whether the tag memory data is valid or invalid, but this V bit is also random when the power is turned on. Therefore, when the power is turned on, initialize the V bits all at once to 0, for example.
From then on, each time data is written to the cache, the ■ bit is set to 1.
to clearly indicate whether the data is valid or invalid. If this initialization is performed by sequentially writing 0 to each V bit, it will take time. The present invention also attempts to perform this simultaneous initialization at high speed.

[Means for solving problems]

The present invention uses an upper address (Au) that specifies a number of books in a cache memory that stores data for n books (n < N) in a main memory that has N books each consisting of a plurality of sheets. In a semiconductor memory device that stores data at a lower address (Ad) that specifies a value, a V bit indicating whether data (Au) at the address is valid or invalid is stored in each address of the memory device (12), It is also characterized by the provision of an initialization circuit that invalidates (0) the bits all at once when the power is turned on.The initialization circuit also includes a circuit (PO2゜N Go
, N G + , =-) and all bit lines of the data (Au) section are disconnected from the power supply, and ■ the bit lines of the bit section are disabled (
0) Data adding circuit (PCB, Q+ to Q5.Qi)
It is characterized by having the following.

[Effect]

According to this storage device (Tag Memo January), it is possible to clearly indicate the validity/invalidity of the data in the tag memory and eliminate the inconvenience of incorrect hint output.Also, the V bit indicating validity/invalidity is cleared all at once, and the data Every time (Au) is written, the v bit of the address concerned is set to valid "1", so ■It does not take time to clear the bit, and at this time, excessive current does not flow from the power supply. Benefits can be obtained.

〔Example〕

As shown in FIG. 1, in the present invention, a V bit is attached to each data (Au) in the tag memory 12, and if this bit is 1, the data is valid, and if it is 0, the data is invalid.

A comparator 14 compares the tag memory read data RD and the upper address Au (comparison data CD) of the address accessing the main memory, and if they match, generates a signal S1 (S
+ to H level). 16 is a write buffer which, when a write signal WS is input, writes the upper address Au of the address accessing the main memory to the position of the same lower address Ad of the tag memory 12 as write data WD. At this time, data 1 is simultaneously written to the ■ bit portion of the same lower address Ad.

Reading of the tag memory 12 is performed using a lower address Ad of the address accessing the main memory, and the read data RD becomes one input of the comparator 14. The upper address Au of the address accessing the main memory becomes comparison data CD and becomes the other input of the comparator 14. When these RD and CD match, the comparator 14 produces a match output S+, which becomes one input of the Nant gate G. When the tag memory is read in the above Ad, the V bit of the bit section 12a is also read out, and this (indicated by S2) becomes the other input of the Nant gate G. S+ is H level (coincidence output), S2 is also H
If the level (V pit -1, data valid), the output S3 of Nant gate G becomes L level, and this inverted output matches (
This signal becomes a hit signal and instructs OK to read data from the cache memory. Even if the comparator 14 produces a coincidence output SI, if the ■ bit is 01, so 32=L, a hit output S3 will not be produced. This prevents errors due to random data.

For writing, input the upper address Au as write data WD to the write buffer 16, give the write signal WS to the buffer and the tag memory 12, access the tag memory 12 with the lower address Ad, and write the tag data part 12b determined by MAd. Add Au again to the address ■Pi I・Part 12a
Write 1 to the address.

FIG. 2(a) shows a circuit that initializes all the v bits of the ■ bit part 12a of the tag memory 12 all at once when the power is turned on. Although not shown in FIG. 1, the circuit of FIG. 2 is incorporated into the tag memory 12 and is therefore provided on the same semiconductor substrate (chip) 10. BL and BL are bit line pairs of the bit section 12a, and BLi and BLi are bit line pairs of the tag data section 12b (there are as many as the number of bits of Au, but only one pair is shown). Bit line pair BL, BL is n-channel MOS) transistor Q1. Q4. and n-channel MOS) transistor Q2. The power supply Vcc is pulled up through Q5, and the bit line pair BLi, BLi is also n-channel MOS) transistor Qi and n-channel MOS l-
Ransistor Q6. Q? It is applied to the power supply Vcc through the power supply Vcc. Further, bit line BL is pulled down to ground by n-channel MO3I-transistor Q3. Wo
, W+, . . . are word lines, and WD is the output of a word decoder that selects one of these word lines by a lower address Ad. NG o, NG +,・
. . . is a NOR gate, 1o, I+, . . . are inverters, NG is a Nant gate, CG is a column gate, and MC is a memory cell. Since it is an SRAM, the memory cells are composed of flip-flops. The other ends of the bit line pairs BL, BL, BLi, BLi are connected to a data bus (not shown) through a column gate CG.

With this tag memory, when the power is turned on, the v of each address (Ad) is
To set the bit to O, input the purge signal PURG from the outside, that is, set it to the L level as shown in FIG. 2(b). When the signal PURG goes to the L level, an internal signal generation circuit (not shown) changes the signal PC+ to the H level.
Signal PG+ goes to L level. So Q+ is off, Q3
on, Qi off. Therefore, BL and LXBL become H, and BLi and BLi are disconnected from the power supply Vcc. Further, the output of the NAND game 1-NG is also the output of the H1 inverter (2), so the column gate CG is turned off. The above signal generation circuit then generates the signal PG2 (high level), thereby causing the NOR gates NGo, NG+, . . .
The output of ... is L1 inverter Io, I+.

......'s output becomes H, and all word lines Wo, W+
.

... is selected. As a result, all memory cells MC
The transfer gate of MC is opened and the MC is connected to each bit line, but the bit line pair BLi,
Since BLi is in an open state, no data is written to the memory cell of the data section, but since the bit line pair of the bit section 12a is BL=L and BL=H (this represents data O), the memory of the bit section 12a is written. O's are written to the cells all at once. After writing, set Pt1RG to H, which causes sequential PG
2=L, PG+=L, PC+=H.

According to this V-bit simultaneous clearing method, it is possible to initialize all V bits simultaneously in one to several cycles, and since all bit lines are disconnected from the power supply Vcc at this time, no current flows from the power supply. (If you select all word lines while the bit line is connected to the power supply, excessive current will flow from the power supply to the bit line).

(2) Although one bit may be sufficient, reliability can be increased by setting multiple bits and assuming that data is valid when all of them are 1.

The simultaneous clearing method shown in FIG. 2 can also be used to clear the memory that stores old and new information on ways in the LRU section.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to clearly indicate the validity/invalidity of data in the tag memory, and eliminate the inconvenience of erroneous hit output. In addition, the v bits indicating validity/invalidity are cleared all at once, and each time data (Au) is written, the V bit of the corresponding address is set to valid "L", so it does not take time to clear the ■ bits, and At this time, advantages such as no excessive current flowing out from the power source can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram and waveform diagram of an initialization circuit section thereof, and FIGS. 3 to 5 are explanatory diagrams of a cache memory. In FIGS. 1 and 2, 12 is a tag memory, 12a is its V bit part, 12b is a data (Au) part, PO2 is a word line all selection signal, NGo, NG+. ... is the gate, Q+, Q2. Qa, Q5.
Qa is a transistor that connects the bit line to a power supply, and Qa is a transistor that connects to ground.

Claims (2)

[Claims] (1) A cache memory that stores data for n books (n<N) in a main memory that has N books each consisting of a plurality of sheets.
In a semiconductor storage device that stores an upper address (Au) that specifies the book in a lower address (Ad) that specifies a sheet in the book, the data (Au) of the address is valid for each address of the storage device (12). What is claimed is: 1. A semiconductor memory device comprising an initialization circuit that stores V bits indicating whether the V bits are valid or invalid, and that invalidates (zero) the V bits all at once when power is turned on. (2) The initialization circuit is a circuit that selects all word lines of the storage device (PG_2, NG_0, NG_1, . . .
...) and a circuit (PG_1, Q_1 to Q_5, Qi) that disconnects all bit lines of the data (Au) part from the power supply and adds invalid (0) data to the bit lines of the V bit part. A semiconductor memory device according to claim 1.