JPH073660B2 - Semiconductor memory device - Google Patents

Description

Detailed Description [Overview] Each bit of data in a tag memory is attached with a V bit, which is initialized at the same time when the power is turned on, and each time the data is written, the V bit is also written to write the data. Clarified valid / invalid.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a tag memory of a cache memory of a computer.

[Prior Art] The memory (main memory) of a computer is connected to the processor through a bus, and also DRAM (dynamic RA).
M) is used to increase the capacity, so there is a problem that the access time is long, and it is faster to improve this.
A cache memory composed of SRAM is used, data read from the main memory is stored in the cache memory, and the same data is supplied from the cache memory to increase the speed.

It is difficult to increase the capacity of the cache due to the use of SRAM (static RAM), etc., and there is usually only a capacity equivalent to a part of the main memory. Although there are various methods of constructing the cache, it is general that the main memory is made up of a plurality of books (blocks), and one, two or four of them are provided. FIG. 3 shows a direct map type cache in which the cache data memory has a capacity of one volume, and FIG.
The figure shows an associative cache with a capacity of two volumes. A numerical example is 16 bytes for one sheet and 51 for one volume.
Two, 524,288 in the main memory. Speaking of address bits, 1 byte out of 16 bytes (1 row) for A _{0 to} A ₃
Select one of the 512 sheets of A _{4 to} A ₁₂ and select A _{13 to} A ₃₁
Choose one out of 524,288.

Data is stored in the cache in units of 16 bytes for each main memory. Store addresses are the same data memory address and lower address A ₄ to A ₁₂ of the main memory in. However, this alone does not tell which one of the 524,288 main memories was in the main memory, so the upper address indicating this is
Store A _{13 to} A ₃₁ in another memory (tag memory).
The tag memory is accessed by the lower address, the upper address is read, the upper address of the address that accesses the memory (main memory) is compared with the upper address read from the tag by the comparator COMP, and if there is a match, the required data is in the cache. Therefore, the data memory of the cache is read at the lower address and is output.

FIG. 5 schematically shows the relationship between the main memory and the cache.
The main memory data is a 16-byte unit in the data memory,
Stored as lower address A ₄ to A ₁₂ the one on the main memory in the same data memory on the address, high address A ₁₃ to A ₃₁ of one such is written in the tag memory at the same time. In this example, the data memory has a capacity of four main memories.

Therefore until four even in this example in the sheets of the same lower address A ₄ to A ₁₂ it can be stored in the cache.

The cache has the capacity for multiple books, but some address A ₄
All of ~ A ₁₂ have already been stored, and it is necessary to purge one that has already been stored in order to read one of the same addresses A _{4 to} A ₁₂ from a certain volume of main memory and store it in the cache. There is. LRU is often used as this replacement algorithm.

[Problems to be solved by the invention]

The high-order address is stored in the tag memory, and if the high-order address of the address that accesses the main memory matches the high-order address read from the tag memory, the relevant data is in the cache, but the memory data is random when the power is turned on. Is. Therefore, until then, the main memory access upper address and the tag memory read data coincided by chance,
Since the data is stored in the cache, there is a possibility that the data is also read from the random data memory. The present invention seeks to improve these points by simple means.

For this purpose, in the present invention, V (Validity) bit is added to the data (upper address) of the tag memory to clearly indicate the validity / invalidity of the tag memory data, but when the power is turned on, this V bit is also random. Therefore, when the power is turned on, the V bits are simultaneously initialized, for example, 0, and each time data is written in the cache, the V bit is set to 1 to clearly indicate the validity / invalidity of the data. It takes time if this initialization is performed by sequentially writing 0 to each V bit. The present invention also seeks to perform this simultaneous initialization at high speed.

[Means for solving problems]

According to the present invention, the main memory n is provided with N books each including a plurality of books.
A semiconductor memory device in which a high-order address (Au) designating a book is stored in a low-order address (Ad) designating a book in a cache memory that stores data for a book (n <N). (12) comprises a plurality of word lines, a plurality of bit lines, a memory cell (MC) connected to the word line and the bit line, and the plurality of bit lines for each address of the storage device (12). A V bit indicating whether the data (Au) of the address is valid or invalid is stored in a memory cell (MC) connected to a predetermined part of the bit lines in the memory cell, and the V bit is powered by a power source. An initializing circuit for invalidating (0) all at the time of turning on is provided, and the initializing circuit is
Circuit for selecting all word lines of the memory device (PG ₂ , NG ₀ , NG ₁ ...
...) and a circuit (PG ₁ , Q _{1 to} Q ₅ ) for disconnecting all bit lines of the data (Au) part from the power source and adding invalid (0) data to the bit line of the V bit part. To do.

[Action]

According to this storage device (tag memory), it is possible to clearly indicate the validity / invalidity of the data in the tag memory and eliminate the inconvenience of outputting an incorrect hit output. Further, the V bit indicating valid / invalid is cleared all at once, and each time the data (Au) is written, the V bit of the relevant address is set to valid "1", so that it does not take time to clear the V bit, and At this time, there is an advantage that an excessive current does not flow out from the power source.

〔Example〕

As shown in FIG. 1, in the present invention, each data (Au) in the tag memory 12 is provided with a V bit. If this is 1, for example, the data is valid, and if it is 0, the data is invalid. Reference numeral 14 is a comparator, which compares the tag memory read data RD with the upper address Au (comparison data CD) of the address for accessing the main memory, and generates a signal S ₁ if they match (sets S ₁ to H level). . Reference numeral 16 is a write buffer, which writes the upper address Au of the address for accessing the main memory as write data WD at the same lower address Ad of the tag memory 12 when the write signal WS is inputted. At this time, data 1 is simultaneously written in the V bit part of the same lower address Ad.

The reading of the tag memory 12 is performed by the lower address Ad of the address for accessing the main memory, and the read data RD becomes one input of the comparator 14. The upper address Au of the address for accessing the main memory becomes the comparison data CD and the comparator
It becomes the other input of 14. When these RD and CD match, comparator 14 produces a match output S ₁ , which is one input of NAND gate G. When the tag memory is read with the above Ad, V
The V bit of the bit part 12a is also read, and this (shown by S ₂ )
Becomes the other input of the NAND gate G. If S ₁ is at H level (match output) and S ₂ is at H level (V bit = 1, data valid), the output S _{3 of the} NAND gate G becomes L level, and this inverted output becomes a match (hit) signal, and the cache Instruct to read data memory OK. Comparator 14 coincident output
Even if S ₁ is generated, the V bit is 0, so if S ₂ = L, the hit output S ₃ is not generated. In this way, errors due to random data are prevented.

For writing, the upper address Au is input to the write buffer 16 as the write data WD, the write signal W is applied to the buffer and the tag memory 12, and the lower address Ad is used for the tag memory 12.
To write Au to the address of the duck data portion 12b determined by the Ad and write 1 to the address of the V bit portion 12a.

FIG. 2A shows each V of the V bit portion 12a of the tag memory 12.
A circuit that initializes all bits at the same time when the power is turned on is shown. Although not shown in FIG. 1, this second circuit is incorporated in the tag memory 12 and therefore provided on the same semiconductor substrate (chip) 10. BL, ▲ ▼ is a bit line pair of the V bit section 12a, and BLi, ▲ ▼ i is a bit line pair of the tag data section 12b (there are a large number, that is, the number of bits of Au but only one pair is shown). The bit line pair BL, ▲ ▼ are p-channel MOS transistors Q ₁ , Q ₄ , and n-channel MOS transistors Q ₂ , Q ₅
Is pulled up to the power supply Vcc through the bit line pair BLi, ▲
I is also pulled up to the power supply Vcc through the p-channel MOS transistor Qi and the n-channel MOS transistors Q ₆ and Q ₇ . The bit line BL is pulled down to the ground by n-channel MOS transistor Q _3. W ₀ , W ₁ , ... Are word lines, and WD is the output of a word decoder that selects one of these word lines according to the lower address Ad. NG ₀ ,
NG ₁ , ... are NOR gates, I ₀ , I ₁ , ... are inverters, NG is a NAND gate, CG is a column gate, and MC is a memory cell. Since it is SRAM, the memory cell is composed of flip-flops. Bit line pair BL, ▲ ▼, BLi, ▲
The other end of i is connected to a data bus (not shown) through the column gate CG.

In order to set the V bit of each address (Ad) to 0 when the power is turned on in this tag memory, a purge signal ▲ ▼
Is input, that is, it is set to the L level as shown in FIG. When the signal ▲ ▼ becomes L level, the signal PG ₁ becomes H level and the signal ▲ ▼ ₁ becomes L level by an internal signal generating circuit (not shown). So Q ₁ is off, Q _{3 is} on, and Qi is off. Therefore, BL becomes L and ▲ ▼ becomes H, and BLi and ▲ ▼ i are disconnected from the power source Vcc. Further, the output of the NAND gate NG is H and the output of the inverter I is L, so that the column gate CG is turned off. The above signal generating circuit subsequently generates the signal PG ₂ (sets it to the H level), whereby the outputs of the NOR gates NG ₀ , NG ₁ ,.
The output of the inverters I ₀ , I ₁ , ... becomes H, and all word lines
W ₀ , W ₁ , ... are selected. As a result, the transfer gates of all the memory cells MC are opened and the MCs are connected to the respective bit lines. However, since the bit line pair BLi, ▲ ▼ i of the data section 12b is in the open state, the memory cells of the data section are written. However, the bit line pair of the V bit part 12a is BL = L,
Since ▲ ▼ = H (this represents data 0), 0 is written all at once in the memory cells of the V bit portion. After writing, ▲ ▼ is set to H, so that PG ₂ = L, PG ₁ =
L, ▲ ▼ ₁ = H.

According to this V bit simultaneous clear method, all V bits can be initialized simultaneously in one to several cycles, and at this time, since all bit lines are disconnected from the power supply Vcc, current may flow from the power supply. Not available (excessive current flows from the power supply to the bit line if all word lines are selected while the bit line is connected to the power supply).

The V bit may be 1 bit, but if the data is a plurality of bits and all of them are 1, then the reliability can be increased.

The simultaneous clearing method shown in Fig. 2 can be used for clearing the memory that stores the old and new information of the way of the LRU part.

〔The invention's effect〕

As described above, according to the present invention, it is possible to disclose the validity / invalidity of the data in the tag memory and eliminate the inconvenience of outputting an incorrect hit output. Further, the V bit indicating valid / invalid is cleared all at once, and each time the data (Au) is written, the V bit of the relevant address is set to valid "1", so that it does not take time to clear the V bit, and At this time, there is an advantage that an excessive current does not flow out from the power source.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram and waveform diagram of its initialization circuit section, and FIGS. 3 to 5 are explanatory diagrams of a cache memory. In FIGS. 1 and 2, 12 is a tag memory and 12a is its V
Bit part, 12b is a data (Au) part, PG ₂ is a word line full selection signal, NG ₀ , NG ₁ , ... Is its gate, Q ₁ , Q ₂ , Q ₄ , Q ₅ , Q ₆ are bit lines. The transistor connected to the power supply, Q ₃ is the transistor connected to ground.

Claims (1)

[Claims] 1. A high-order address (Au) for designating a book in a cache memory for storing data for n books (n <N) in a main memory having N books each consisting of a plurality of books. In a semiconductor memory device for storing in a lower address (Ad) that specifies a memory cell, the memory device (12) includes a plurality of word lines, a plurality of bit lines, and the memory cells (MC) connected to the word lines and the bit lines. The data (Au) of the address is valid for the memory cells (MC) connected to a predetermined part of the bit lines of the plurality of bit lines for each address of the storage device (12). Is provided with a V bit indicating whether it is invalid or invalid, and an initialization circuit that invalidates (0) the V bits at the same time when power is turned on is provided.
Circuit for selecting all word lines of the memory device (PG ₂ , NG ₀ , NG ₁ ...
...) and a circuit (PG ₁ , Q _{1 to} Q ₅ , Qi) for disconnecting all bit lines of the data (Au) part from the power source and adding invalid (0) data to the bit line of the V bit part. A characteristic semiconductor memory device.