JPS6336719B2 - - Google Patents

Info

Publication number
JPS6336719B2
JPS6336719B2 JP11187081A JP11187081A JPS6336719B2 JP S6336719 B2 JPS6336719 B2 JP S6336719B2 JP 11187081 A JP11187081 A JP 11187081A JP 11187081 A JP11187081 A JP 11187081A JP S6336719 B2 JPS6336719 B2 JP S6336719B2
Authority
JP
Japan
Prior art keywords
control signal
communication path
digital
fixed line
digital terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11187081A
Other languages
Japanese (ja)
Other versions
JPS5813097A (en
Inventor
Hitoshi Shirai
Shuichi Ashihara
Yoshiaki Sutani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11187081A priority Critical patent/JPS5813097A/en
Publication of JPS5813097A publication Critical patent/JPS5813097A/en
Publication of JPS6336719B2 publication Critical patent/JPS6336719B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing

Description

【発明の詳細な説明】 本発明は固定回線収容方式、特に各々音声信号
と制御信号とを伝送する複数の通話路を収容する
複数のデイジタル端局ユニツトと多重化装置とか
ら成り、音声分離形式制御信号路を具備するデイ
ジタル多重化通話路を構成するデイジタル端局装
置における固定回線収容方式に関す。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fixed line accommodating system, and more particularly to a fixed line accommodating system, which comprises a plurality of digital terminal units and a multiplexing device, each accommodating a plurality of communication channels for transmitting voice signals and control signals, and a voice separation format. The present invention relates to a fixed line accommodating system in digital terminal equipment that configures a digital multiplex communication path including a control signal path.

第1図はこの種従来あるデイジタル端局装置と
時分割交換器との接続例を示す図である。第1図
において、デイジタル端局装置DTは、5組のデ
イジタル端局ユニツトDTU0乃至DTU4と、多
重化装置MPXとから構成されている。各デイジ
タル端局ユニツトDTU0乃至DTU4は、各々音
声信号Vとフツキング信号等の制御信号Sを伝送
する通話路CHを24通話路含む通話路群CHG0乃
至CHG4をそれぞれ収容する。各通話路群CHG
0乃至CHG4は、第2図は例示される如きフレ
ーム構成を有する時分割通話路群とする。第2図
において、公知の如く周期125マイクロ秒で繰返
される各フレームF(CHG)は、1ビツトの同期
ビツトFbと、それぞれ8ビツトより成る24個の
タイムスロツトTSから構成される。各タイムス
ロツトTSはそれぞれ24通話路CHに割当てられ、
通常8ビツトが総べて音声信号Vの伝送に用いら
れる。なお6フレーム毎に各タイムスロツトTS
のビツトb7は対応通話路CHの制御信号Sの伝送
に流用される。なお制御信号Sは最大2ビツトを
必要とするので、制御信号Sは12フレーム(1.5
ミリ秒)を周期として伝送される。以上の如き通
話路群CHG0乃至CHG4はデイジタル端局ユニ
ツトDTU0乃至DTU4を経由して多重化装置
MPXに導びかれて、120通話路CHを含むデイジ
タル多重化通話路HWを構成する。該デイジタル
多重化通話路HWは第3図に例示される如きフレ
ーム構成を有する。第3図において、125マイク
ロ秒で繰返される各フレームF(HW)はそれぞ
れ8ビツトから成る128個のタイムスロツトTSか
ら構成される。そのうちタイムスロツトTS4乃
至TS63およびタイムスロツトTS68乃至12
7は各々120通話路CHに割当てられ、8ビツト
が総べて音声信号Vの伝送に用いられる(以後前
記各タイムスロツトTSを音声信号路VCHと称
す)。またタイムスロツトTS64および65は、
120通話路CH分の制御信号Sが16フレーム(2
ミリ秒)を周期として、それぞれ2ビツト宛によ
り伝送される(以後タイムスロツトTS64およ
び65を制御信号路SHWと称す)。以上の如きデ
イジタル多重化通話路HWは時分割交換機の時分
割ネツトワークTD−NWに接続され、中央制御
装置CCの制御により各通話路CH毎に所要の加入
者SUB等に接続される。なお中央制御装置CCは
前記接続制御のために、デイジタル多重化通話路
HWから分岐挿入回路DIにより前記制御信号路
SHWを抽出し、制御信号Sを授受する。また加
入者SUBの制御に当つても、公知の如く対応す
る加入者回路LCとの間に制御信号Sの授受を行
う。
FIG. 1 is a diagram showing an example of a connection between a conventional digital terminal device of this type and a time division switch. In FIG. 1, the digital terminal equipment DT is composed of five sets of digital terminal units DTU0 to DTU4 and a multiplexer MPX. Each of the digital terminal units DTU0 to DTU4 accommodates a channel group CHG0 to CHG4, each including 24 channels CH for transmitting a voice signal V and a control signal S such as a hooking signal. Each channel group CHG
CHG 0 to CHG 4 are time-division communication paths having a frame structure as illustrated in FIG. In FIG. 2, each frame F (CHG), which is repeated at a period of 125 microseconds as is well known, consists of a 1-bit synchronization bit Fb and 24 time slots TS each consisting of 8 bits. Each time slot TS is assigned to 24 channels CH,
Normally all 8 bits are used for transmitting the audio signal V. In addition, each time slot TS is set every 6 frames.
Bit b7 is used for transmitting the control signal S of the corresponding channel CH. Note that the control signal S requires a maximum of 2 bits, so the control signal S requires 12 frames (1.5
It is transmitted with a period of milliseconds). The communication path groups CHG0 to CHG4 as described above are connected to the multiplexer via the digital terminal units DTU0 to DTU4.
A digital multiplex channel HW including 120 channels CH is configured based on the MPX. The digital multiplex communication path HW has a frame structure as illustrated in FIG. In FIG. 3, each frame F(HW), which is repeated every 125 microseconds, consists of 128 time slots TS, each consisting of 8 bits. Of these, time slots TS4 to TS63 and time slots TS68 to 12
7 are respectively assigned to 120 communication paths CH, and all 8 bits are used for transmitting the audio signal V (hereinafter, each time slot TS will be referred to as an audio signal path VCH). Also, time slots TS64 and TS65 are
The control signal S for 120 communication channels CH is 16 frames (2
The time slots TS64 and TS65 are hereinafter referred to as the control signal path SHW. The digital multiplexed communication paths HW as described above are connected to the time division network TD-NW of the time division exchange, and each communication path CH is connected to a required subscriber SUB etc. under the control of the central controller CC. Note that the central controller CC uses a digital multiplex communication path for the connection control.
The control signal path is
Extracts SHW and sends and receives control signal S. Furthermore, in controlling the subscriber SUB, control signals S are sent and received between the subscriber circuit LC and the corresponding subscriber circuit LC, as is well known.

以上の説明から明らかな如く、従来あるデイジ
タル端局装置DTは第3図に示される如きフレー
ム構成のデイジタル多重化通話路HWにより時分
割交換機に接続され、制御信号路SHWにより伝
達される制御信号Sは、必ず中央制御装置CCを
介して加入者回路LCに伝達される。従つて、特
定の通話路CHを特定の加入者SUB等に固定的に
接続し、中央制御装置CCの管理外に置く、所謂
固定回線サービスの適用が不可能となる。その対
策として、従来全通話路CHに対して各通話路
CHあたり2個の音声信号路VCHを割当て、時分
割ネツトワークTD−NW内も2個の音声信号路
により所望の加入者回路LCに接続し、一方の音
声信号路VCHにより音声信号Vを伝送し、他方
の音声信号路VCHにより制御信号Sも直接加入
者回路LCとの間に伝送する等の方策も採られて
いるが、かゝる方策によれば、デイジタル多重化
通話路HWの通話路CH収容能力は半減し、デイ
ジタル端局装置DTの経済性を損なうことゝな
る。
As is clear from the above explanation, the conventional digital terminal equipment DT is connected to the time division exchange through a digital multiplex communication path HW having a frame structure as shown in FIG. 3, and control signals transmitted through the control signal path SHW. S is always transmitted to the subscriber circuit LC via the central control unit CC. Therefore, it becomes impossible to apply a so-called fixed line service in which a specific communication channel CH is fixedly connected to a specific subscriber SUB or the like and placed outside the control of the central controller CC. As a countermeasure for this, each channel has been
Two audio signal paths VCH are assigned per CH, and the time division network TD-NW is also connected to the desired subscriber circuit LC via two audio signal paths, and the audio signal V is transmitted through one audio signal path VCH. However, measures have also been taken such as directly transmitting the control signal S to the subscriber circuit LC through the other voice signal path VCH. The channel CH accommodation capacity will be halved, which will impair the economic efficiency of the digital terminal equipment DT.

本発明の目的は、前述の如き従来あるデイジタ
ル端局装置の欠点を除去し、前記固定回線を経済
性を損なうこと無く収容可能な手段を実現するこ
とに在る。
An object of the present invention is to eliminate the drawbacks of the conventional digital terminal equipment as described above, and to realize means capable of accommodating the fixed line without impairing economic efficiency.

この目的は、各々音声信号と制御信号とを伝送
する複数の通話路を収容する複数のデイジタル端
局ユニツトと多重化装置とから成り、デイジタル
多重化通話路を経由して時分割ネツトワークとの
間で音声信号および制御信号を送受するデイジタ
ル端局装置において、前記多重化装置から前記時
分割ネツトワークへ至るデイジタル多重化通話路
より音声信号および制御信号を抽出する抽出回路
と、前記時分割ネツトワークから前記多重化装置
へ至るデイジタル多重化通話路に制御信号を挿入
する挿入回路とを備え、且つ前記抽出回路より送
られる音声信号および制御信号の中から任意の通
話路チヤネルに対応する制御信号を取出し多重化
装置に送る第1のメモリと、多重化装置から制御
信号用通話路を経由して送られる制御信号を対応
する通話チヤネルに割当てて取出し、前記挿入回
路に送る第2のメモリとから成る制御信号ユニツ
トを、複数の前記デイジタル端局ユニツトの内の
一つと置換えて設けたことことにより達成され
る。
This purpose consists of a plurality of digital terminal units and a multiplexer, each accommodating a plurality of channels for transmitting voice signals and control signals, and connects to a time division network via the digital multiplex channel. A digital terminal device that transmits and receives voice signals and control signals between the multiplexing device and the time-division network includes an extraction circuit that extracts voice signals and control signals from a digital multiplex communication path from the multiplexing device to the time-division network; an insertion circuit for inserting a control signal into a digital multiplexed communication path from the workpiece to the multiplexing device, and a control signal corresponding to an arbitrary communication path channel from among the audio signals and control signals sent from the extraction circuit; a first memory that takes out the control signal and sends it to the multiplexing device; a second memory that allocates the control signal sent from the multiplexer via the control signal communication path to a corresponding communication channel, takes it out, and sends it to the insertion circuit; This is achieved by replacing one of the plurality of digital end station units with a control signal unit consisting of:

以下、本発明の一実施例を第4図および第5図
により説明する。第4図は本発明の一実施例によ
る固定回線収容方式を示す図であり、第5図は第
4図におけるデイジタル端局装置の構成例を示す
図である。なお、全図を通じて同一符号は同一対
象を示す。第4図において、デイジタル端局装置
DT′には24通話路CHから成る通話路群CHG0乃
至CHG3を収容するデイジタル端局ユニツト
DTU0乃至DTU3が4組設けられ、第1図にお
けるデイジタル端局ユニツトDTU4に代り制御
信号ユニツトSGUが多重化装置MPXに接続され
ている。該制御信号ユニツトSGUは、他のデイ
ジタル端局ユニツトDTU0乃至DTU3の如く通
話路群CHGは収容しないが、多重化装置MPXに
対しては、該デイジタル端局ユニツトDTU0乃
至DTU3と同一の接続条件で、24通話路CH分
(以後制御信号用通話路群SCHGと称す)の音声
信号Vおよび制御信号Sの授受を可能とする。従
つて、多重化装置MPXは該制御信号用通話路群
SCHGをも含め第3図に示される如き120通話路
容量のデイジタル多重化通話路HWを組立てる。
なおデイジタル多重化通話路HWの制御信号路
SHWは、第5図により詳細に示される如く制御
信号ユニツトSGUに接続される。第5図におい
て、多重化装置MPXの組立てるデイジタル多重
化通話路HWは、送信多重化通話路HWSと受信
多重化通話路HWRとにより伝送方向別に示さ
れ、また多重化装置MPXと制御信号ユニツト
SGUとの間に設けられる制御信号用通話路群
SCHGは、それぞれ伝送方向別に示される。送信
多重化通話路HWSに含まれる制御信号路SHWは
点Bから制御信号ユニツトSGU内のメモリRAM
2にも導びかれ、書込指示信号W2により、120
通話路CH分の制御信号Sの中から任意の通話路
CHに対応する制御信号Sを格納することが出来
る。メモリRAM2は24語(1語8ビツト)の記
憶容量を持ち、計数回路CTRからの読出指示信
号R2により、デイジタル端局ユニツトDTU0
乃至DTU3と同一条件で、1通話路CH当り1語
の速度で格納内容を多重化装置MPXに送出する。
またメモリRAM1も24語(1語8ビツト)の記
憶容量を持ち、計数回路CTRからの書込指示信
号W1により、デイジタル端局ユニツトDTU0
乃至DTU3と同一条件で、多重化装置MPXから
伝達される制御信号用通話路群SCHGの信号を1
通話路CH当り1語の速度で格納する。該格納内
容は読出指示信号R1により任意の時点に抽出さ
れ、挿入回路Iを介して受信多重化通話路HWR
に含まれる音声分離形式制御信号路SHWの伝送
する120通話路CH分の制御信号Sの中の任意の
通話路CHに対応する制御信号Sとして挿入する
ことが出来る。前記書込指示信号W2および読出
指示信号R1の発生時点は、時分割交換機の中央
制御装置CCから受信多重化通話路HWR内の制御
信号路SHWおよび多重化装置MPXを経由して制
御信号ユニツトSGUに伝達され、制御回路CTL
によりメモリRAM0に格納される固定回線割当
データにより定められる。今通話路群CHG0乃
至CHG3に含まれる96通話路CHが何れも固定回
線として使用されぬ場合には、何等の固定回線割
当データも伝達されぬので、送信多重化通話路
HWS内の制御信号路SHWに含まれる何れの通話
路対応の制御信号SもメモリRAM2に格納され
ず、また受信多重化通話路HWR内の制御信号路
SHWにはメモリRAM1から抽出される制御信
号Sが挿入されることは無い。次に通話路群
CHG0乃至CHG3に含まれる96通話路CHの任
意の通話路CHを固定回線FCHとして使用する場
合には、使用開始時に、時分割交換機の中央制御
装置CCから前述の経路を介して制御信号ユニツ
トSGUの制御回路CTLに、固定回線割当データ
が伝達される。該固定回線割当データは、固定回
線用通話路FCHと、制御信号用通話路群SCHG
内の任意の空き通話路(以後制御信号用通話路
SCHを称す)とを指定する。該固定回線割当デ
ータはメモリRAM0に格納され、メモリRAM
2に対する書込指示信号W2およびメモリRAM
1に対する読出指示信号R1を、送信多重化通話
路HWSおよび受信多重化通話路HWR内の制御
信号路SHWにより伝送される固定回線用通話路
FCH対応の制御信号Sを前記制御信号用通話路
SCHに伝達する如く発生させる。その結果、固
定回線用通話路FCHの音声信号Vは公知の如く
送信多重化通話路HWSおよび受信多重化通話路
HWR内の固有の音声信号路VCHにより、また
固定回線用通話路FCHの制御信号Sは前記制御
信号用通話路SCHに固有の音声信号路VCHによ
り、それぞれ時分割交換機に伝送される。一方時
分割交換機においては、中央制御装置CCがデイ
ジタル端局装置DT′に固定回線割当データを送達
した時点に、デイジタル多重化通話路HW内の固
定回線用通話路FCHおよび制御信号用通話路
SCHに各々固有の音声信号路VCHを、時分割ネ
ツトワークTD−NWを介して固定回線サービス
の対象となる加入者回路FLCの具備する2つの
音声信号路端子に固定接続し、以後該固定接続は
管理対象から除く。その結果固定回線用通話路
FCHの制御信号Sは、制御信号用通話路SCHに
固有の音声信号路VCHおよびこれに固定接続さ
れる時分割ネツトワークTD−NW内の音声信号
路を介して直接固定回線用加入者回路FLCに伝
送される。更に実施中の固定回線サービスを解除
する場合には、中央制御装置CCが固定回線解除
データを固定回線割当データと同一経路で制御信
号ユニツトSGU内の制御回路CTLに伝達し、ま
た時分割ネツトワークTD−NW内に設定されて
いる前記固定接続を解放する。制御回路CTLは
受領した固定回線解除データに基づき、メモリ
RAM0内に格納されている固定回線割当データ
を削除し、前記書込指示信号W2および読出指示
信号R1の送出を中止する。その結果、制御信号
路SHWから抽出される固定回線用通話路FCH対
応の制御信号Sの前記制御信号用通話路SCHに
より伝送は中止され、固定回線用通話FCHは一
般の通話路CH状態に戻り、また制御信号用通話
路SCHは、他の固定接続に使用可能となる。
An embodiment of the present invention will be described below with reference to FIGS. 4 and 5. FIG. 4 is a diagram showing a fixed line accommodation system according to an embodiment of the present invention, and FIG. 5 is a diagram showing an example of the configuration of the digital terminal equipment in FIG. 4. Note that the same reference numerals indicate the same objects throughout the figures. In Figure 4, the digital terminal equipment
DT' is a digital terminal unit that accommodates communication path groups CHG0 to CHG3 consisting of 24 communication paths CH.
Four sets of DTU0 to DTU3 are provided, and a control signal unit SGU is connected to the multiplexer MPX in place of the digital terminal unit DTU4 in FIG. Although the control signal unit SGU does not accommodate the channel group CHG like the other digital terminal units DTU0 to DTU3, it does not accommodate the communication path group CHG to the multiplexer MPX under the same connection conditions as the digital terminal units DTU0 to DTU3. , 24 communication paths CH (hereinafter referred to as control signal communication path group SCHG) can transmit and receive audio signals V and control signals S. Therefore, the multiplexer MPX has a group of communication paths for the control signals.
A digital multiplex channel HW with a capacity of 120 channels as shown in FIG. 3 including SCHG is assembled.
In addition, the control signal path of the digital multiplex communication path HW
SHW is connected to the control signal unit SGU as shown in more detail in FIG. In FIG. 5, the digital multiplex channel HW assembled by the multiplexer MPX is shown in each transmission direction by a transmit multiplex channel HWS and a receive multiplex channel HWR, and the multiplex device MPX and the control signal unit
Control signal communication path group established between SGU
SCHG is shown for each transmission direction. The control signal path SHW included in the transmission multiplexed communication path HWS runs from point B to the memory RAM in the control signal unit SGU.
2, and by the write instruction signal W2, 120
Select any communication path from the control signal S for the communication path CH.
A control signal S corresponding to CH can be stored. The memory RAM2 has a storage capacity of 24 words (8 bits per word), and is read out from the digital terminal unit DTU0 by the read instruction signal R2 from the counting circuit CTR.
Under the same conditions as DTU3 to DTU3, the stored contents are sent to the multiplexer MPX at a rate of one word per channel CH.
The memory RAM1 also has a storage capacity of 24 words (8 bits per word), and is written to the digital terminal unit DTU0 by the write instruction signal W1 from the counting circuit CTR.
Under the same conditions as DTU3, the control signal channel group SCHG signal transmitted from the multiplexer MPX is
It is stored at a rate of one word per channel CH. The stored contents are extracted at any time by the read instruction signal R1, and sent to the reception multiplexing channel HWR via the insertion circuit I.
It can be inserted as a control signal S corresponding to any channel CH among the control signals S for 120 channels CH transmitted by the voice separation format control signal channel SHW included in the control signal channel SHW. The write instruction signal W2 and the read instruction signal R1 are generated from the central control unit CC of the time division switch via the control signal path SHW in the receiving multiplex communication path HWR and the multiplexer MPX to the control signal unit SGU. and the control circuit CTL
is determined by fixed line assignment data stored in memory RAM0. If none of the 96 communication paths CH included in communication path groups CHG0 to CHG3 are currently used as fixed lines, no fixed line allocation data will be transmitted, so the transmission multiplexed communication path
The control signal S corresponding to any communication path included in the control signal path SHW in HWS is not stored in the memory RAM2, and the control signal S in the reception multiplex communication path HWR is not stored in the memory RAM2.
The control signal S extracted from the memory RAM 1 is never inserted into SHW. Next, the communication path group
When using any of the 96 communication channels CH included in CHG0 to CHG3 as a fixed line FCH, at the beginning of use, the control signal unit SGU is sent from the central control unit CC of the time division exchange via the above-mentioned route. The fixed line allocation data is transmitted to the control circuit CTL of. The fixed line allocation data includes fixed line communication path FCH and control signal communication path group SCHG.
(hereinafter referred to as control signal communication path)
SCH). The fixed line allocation data is stored in memory RAM0, and memory RAM
Write instruction signal W2 for 2 and memory RAM
1 is transmitted through the control signal path SHW in the sending multiplexing path HWS and the receiving multiplexing path HWR.
The control signal S compatible with FCH is transmitted through the control signal communication path.
Generate as transmitted to SCH. As a result, the voice signal V of the fixed line communication path FCH is divided into the transmission multiplex communication path HWS and the reception multiplex communication path HWS, as is well known.
The control signal S of the fixed line communication path FCH is transmitted to the time division exchange by the voice signal path VCH unique to the HWR, and the control signal S of the fixed line communication path FCH is transmitted to the time division exchange by the voice signal path VCH unique to the control signal communication path SCH. On the other hand, in a time-division switch, when the central controller CC sends fixed line allocation data to the digital terminal equipment DT', the fixed line channel FCH and the control signal channel in the digital multiplex channel HW are
A voice signal path VCH unique to each SCH is fixedly connected to two voice signal path terminals of a subscriber circuit FLC targeted for fixed line service via the time division network TD-NW, and thereafter the fixed connection is made. are excluded from management. As a result, the fixed line communication path
The FCH control signal S is transmitted directly to the fixed line subscriber circuit FLC via the voice signal path VCH specific to the control signal communication path SCH and the voice signal path in the time division network TD-NW fixedly connected to this. transmitted to. Furthermore, when canceling the fixed line service in progress, the central controller CC transmits the fixed line cancellation data to the control circuit CTL in the control signal unit SGU via the same route as the fixed line allocation data, and also transmits the fixed line cancellation data to the control circuit CTL in the control signal unit SGU. Release the fixed connection set within the TD-NW. The control circuit CTL stores data in memory based on the received fixed line release data.
The fixed line assignment data stored in RAM0 is deleted, and the sending of the write instruction signal W2 and read instruction signal R1 is stopped. As a result, transmission of the control signal S corresponding to the fixed line communication path FCH extracted from the control signal path SHW is stopped by the control signal communication path SCH, and the fixed line communication FCH returns to the general communication path CH state. , and the control signal channel SCH can be used for other fixed connections.

以上の説明から明らかな如く、本実施例によれ
ば、デイジタル端局装置DT′の収容し得る120通
話路CHの内24通話路CHを制御信号用通話路
SCH用に転用するのみで、96通話路CH中の任意
の通話路CHが、24通話路迄は固定回線用通話路
FCHとして使用可能となる。
As is clear from the above explanation, according to this embodiment, 24 channels CH out of 120 channels CH that can be accommodated by the digital terminal device DT′ are used as control signal channels.
By simply converting it to SCH, any channel CH out of 96 channels can be used as a fixed line channel up to 24 channels.
Can be used as FCH.

なお、第4図および第5図はあく迄本発明の一
実施例に過ぎず、例えばデイジタル端局装置
DT′、デイジタル端局ユニツトDTUおよび制御
信号ユニツトSGUに収容される通話路数に限定
されることは無く、他に幾多の変形が考慮される
が、何れの場合にも本発明の効果は変らない。ま
た通話路群CHGおよびデイジタル多重化通話路
HWのフレーム構成も第2図および第3図に示さ
れるものに限定されることは無く、他のフレーム
構成の場合にも本発明の効果は変らない。
It should be noted that FIGS. 4 and 5 are only one embodiment of the present invention, and may be used, for example, in a digital terminal equipment.
The number of communication paths accommodated in DT', digital terminal unit DTU, and control signal unit SGU is not limited, and many other modifications may be considered, but the effects of the present invention will not change in any case. do not have. Also, channel group CHG and digital multiplex channel
The frame structure of the HW is not limited to that shown in FIGS. 2 and 3, and the effects of the present invention remain the same even in the case of other frame structures.

以上、本発明によれば、デイジタル端局装置の
通話路収容能力を大幅に低下させること無く固定
回線サービスが導入することが出来る。
As described above, according to the present invention, fixed line services can be introduced without significantly reducing the communication path capacity of the digital terminal equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来あるデイジタル端局装置と時分割
電子交換機との接続例を示す図、第2図は通話路
群のフレーム構成を例示する図、第3図はデイジ
タル多重化通話路のフレーム構成を例示する図、
第4図は本発明の一実施例による固定回線収容方
式を示す図、第5図は第4図におけるデイジタル
端局装置の構成例を示す図である。 図において、DTおよびDT′はデイジタル端局
装置、DTU0乃至DTU4はデイジタル端局ユニ
ツト、SGUは制御信号ユニツト、MPXは多重化
装置、TD−NWは時分割ネツトワーク、SUBは
加入者、LCは加入者回路、FLCは固定回線用加
入者回路、DIは分岐挿入回路、CCは中央制御装
置、HWはデイジタル多重化通話路、CHG0乃
至CHG4は通話路群、Iは挿入回路、RAM0,
RAM1,RAM2はメモリ、CTLは制御回路、
CTRは計数回路、W1およびW2は書込指示信
号、R1およびR2は読出指示信号、SCHG制御
信号用通話路群、Fはフレーム、Fbは同期ビツ
ト、TSはタイムスロツト、CHは通話路、Vは音
声信号、Sは制御信号、VCHは音声信号路、
SHWは制御信号路、を示す。
Fig. 1 is a diagram showing an example of the connection between a conventional digital terminal equipment and a time division electronic exchange, Fig. 2 is a diagram illustrating the frame structure of a group of communication paths, and Fig. 3 is a diagram showing the frame structure of a digital multiplex communication path. A diagram illustrating,
FIG. 4 is a diagram showing a fixed line accommodation system according to an embodiment of the present invention, and FIG. 5 is a diagram showing an example of the configuration of the digital terminal equipment in FIG. 4. In the figure, DT and DT' are digital terminal equipment, DTU0 to DTU4 are digital terminal units, SGU is a control signal unit, MPX is a multiplexer, TD-NW is a time division network, SUB is a subscriber, and LC is a Subscriber circuit, FLC is subscriber circuit for fixed line, DI is add-drop circuit, CC is central control unit, HW is digital multiplex communication path, CHG0 to CHG4 are communication path group, I is insertion circuit, RAM0,
RAM1 and RAM2 are memories, CTL is a control circuit,
CTR is a counting circuit, W1 and W2 are write instruction signals, R1 and R2 are read instruction signals, SCHG control signal communication path group, F is a frame, Fb is a synchronization bit, TS is a time slot, CH is a communication path, and V is the audio signal, S is the control signal, VCH is the audio signal path,
SHW indicates a control signal path.

Claims (1)

【特許請求の範囲】 1 各々音声信号と制御信号とを伝送する複数の
通話路を収容する複数のデイジタル端局ユニツト
と多重化装置とから成り、デイジタル多重化通話
路を経由して時分割ネツトワークとの間で音声信
号および制御信号を送受するデイジタル端局装置
において、 前記多重化装置から前記時分割ネツトワークへ
至るデイジタル多重化通話路より音声信号および
制御信号を抽出する抽出回路と、 前記時分割ネツトワークから前記多重化装置へ
至るデイジタル多重化通話路に制御信号を挿入す
る挿入回路とを備え、 且つ前記抽出回路より送られる音声信号および
制御信号の中から任意の通話路チヤネルに対応す
る制御信号を取出し多重化装置に送る第1のメモ
リと、 前記多重化装置から制御信号用通話路を経由し
て送られる制御信号を対応する通話チヤネルに割
当てて取出し、前記挿入回路に送る第2のメモリ
とから成る制御信号ユニツトを、複数の前記デイ
ジタル端局ユニツトの内の一つと置換えて設けた
ことを特徴とする固定回線収容方式。
[Scope of Claims] 1. Consisting of a plurality of digital terminal units and a multiplexing device each accommodating a plurality of communication paths for transmitting audio signals and control signals, a time-division network is transmitted via the digital multiplex communication paths. A digital terminal device that transmits and receives audio signals and control signals to and from a workpiece, an extraction circuit that extracts audio signals and control signals from a digital multiplex communication path from the multiplexing device to the time division network; an insertion circuit for inserting a control signal into a digital multiplexed communication path from the time division network to the multiplexing device, and corresponds to any communication path channel from among the audio signals and control signals sent from the extraction circuit. a first memory for extracting control signals sent from the multiplexer to the multiplexing device; 1. A fixed line accommodating system characterized in that a control signal unit consisting of two memories is provided in place of one of the plurality of digital terminal units.
JP11187081A 1981-07-17 1981-07-17 Fixed circuit containing system Granted JPS5813097A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11187081A JPS5813097A (en) 1981-07-17 1981-07-17 Fixed circuit containing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11187081A JPS5813097A (en) 1981-07-17 1981-07-17 Fixed circuit containing system

Publications (2)

Publication Number Publication Date
JPS5813097A JPS5813097A (en) 1983-01-25
JPS6336719B2 true JPS6336719B2 (en) 1988-07-21

Family

ID=14572221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11187081A Granted JPS5813097A (en) 1981-07-17 1981-07-17 Fixed circuit containing system

Country Status (1)

Country Link
JP (1) JPS5813097A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0535213Y2 (en) * 1988-03-31 1993-09-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0535213Y2 (en) * 1988-03-31 1993-09-07

Also Published As

Publication number Publication date
JPS5813097A (en) 1983-01-25

Similar Documents

Publication Publication Date Title
US4555782A (en) Base-band equipment for ground stations of satellite telecommunication system
EP0147865A2 (en) Digital exchange system
CA1169169A (en) Method of and system for satellite-switched time- division multiple access
US5452307A (en) Data multiplexing system having at least one low-speed interface circuit connected to a bus
EP0250075A3 (en) Isdn d channel handler
US4748621A (en) TDMA/TDM interfacing
JPS6262636A (en) Multiplexer and multiplexer separator for synchronous digital link with variable communication amount and variablemodulation speed
US5717762A (en) WACS-type mobile communication with a unified frame format
US4466095A (en) Speech path control system
JPS6336719B2 (en)
JPS60250736A (en) Multi-direction time division radio communication system
US5761207A (en) Multiplex communication system using variable multiframe format
JPH089058A (en) Multiplexer with transmission line backup function
JP2687705B2 (en) Digital transmission system
JPS61171243A (en) Time slot assignment system of multi-channel frame
JPH06120928A (en) Data communication method and device therefor
JP2928378B2 (en) Method of transmitting call connection information in digital switching system and digital switching device
JP2828417B2 (en) Unified switching system for analog line-related information signals and ISDN line-related information signals in telephone exchanges
JP3107152B2 (en) Baud rate mixed multiple paging system
JP2545538B2 (en) Time division multiplexing transmission method
EP0112477A1 (en) Apparatus for multiplexing and demultiplexing data sources
JPH0723014A (en) Time slot signal phase alligner device
JP2907661B2 (en) Digital multiplex transmission equipment
JPH03104334A (en) Control channel termination system
JPS6239596B2 (en)