JPS6336575B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter device that configures different types of filters with the same circuit configuration.

Conventionally, it has been considered to use digital filters to configure filters such as low-pass filters, high-pass filters, and band-pass filters.

One way to design such a digital filter is to use the transfer function H of an analog filter.
Find (s) and apply some kind of transformation to it,
There is a method of finding the transfer function H(z) of a digital filter. Here, in the analog filter, a reference low-pass filter is created, and then a predetermined frequency conversion is performed to configure a low-pass filter, a high-pass filter, a band-pass filter, etc. That is,
When the transfer function of the reference low-pass filter is H ₁ (s), for example, the transfer functions H _L (s) and H _H (s) of the low-pass filter and high-pass filter are expressed by the following equations (1) and (2).
It is determined by

H _L (s)=H ₁ (s) | s=jω/ωc ...Formula (1) H _H (s)=H ₁ (s) | s=ωc/jω ...Formula (2) However, the cutoff frequency Let c be ωc=
It is 2πc.

Now, if we focus on the second-order analog Butterworth type filter as shown in Figure 1, its poles have conjugate roots as shown in Figure 2, as is well known, and the analog transmission of the reference low-pass filter The function H ₁ (s) is H ₁ (s)=1/(S ² +√2S+1)...Equation (3).

Therefore, based on equation (1), the transfer function of a low-pass filter with cut-off frequency c is H _L (s)=ωc ² / (S ² +√2Sωc+ωc ² )...Equation (4), and as shown in FIG. cutoff frequency as shown in
Based on equation (2), the high-pass filter c is H _H (s)S ² / (S ² +√2Sωc+ωc ² )...Equation (5).

To construct the digital filter's transfer function H(z) from the transfer function H(s) obtained in this way, we now need to perform bilinear Z transformation S=2/T _S (1-Z ^-1 /1+Z ^-1 ) ...Execute equation (6). Note that T _S is the sampling time.
Therefore, when calculating the transfer function H _L (z) of the low-pass filter, from equations (4) and (6), H _L (z) = K _L (1 + z ^-1 ) ² /1 + b ₁ z ^-1 + b ₂ z ^-2 ……formula
(7), and the transfer function H _H (z) of the high-pass filter is obtained from equations (5) and (6), H _H (z) = K _H (1-z ^-1 ) ² /1 + b ₁ z ^-1 + b ₂ z ^-2 ……formula
(8) becomes.

However, considering frequency distortion during conversion, each coefficient is set as ωc=2/T _S tanω _D・T _S /2 ...Equation (9), and A=tanω _D・T _S /2 ...Equation (10) B=1+√2A+A ² ...As formula (11), b ₁ =2(A ² -1)/B ...Formula (12) b ₂ = (1-√2A+A ² )/B ...Formula (13) K _L = A ² /B ... Equation (14) K _H = 1/B ... Equation (15).

Figure 4 is a block diagram of the digital filter device expressed by equations (7) and (8) when the cutoff frequency c is made variable. It has an adder 2 to which it is supplied, and multipliers 4 and 5 to which the output of the adder 1 is applied via a unit time T _S delay element 3. This multiplier 4 is further supplied with data b ₁ selected according to the cutoff frequency data c applied to the ROM 6 , and the input signal is multiplied by b ₁ and applied to the adder 1 . Note that this input signal instructs the adder 1 to perform subtraction. Further, the multiplier 5 simply has the function of multiplying the input signal by two in the case of a low-pass filter, and by -2 in the case of a high-pass filter, and its output is given to the adder 2. That is,
From ROM6, a ₁ = ± according to the switching signal L/H
A value of 2 is given to multiplier 5. Furthermore, the output of the delay element 3 is applied to the adder 1 via the unit time T _S delay element 7 and further via the multiplier 8, and is also applied to the adder 2 via the multiplier 9. Note that in this case, the multiplier 9 has no effect. That is,
a ₂ =1. The multiplier 8 is further supplied with data b ₂ selected by the cutoff frequency c applied to the ROM 6, and the input signal is multiplied by b ₂ and applied to the adder 1. Note that this input signal instructs the adder 1 to perform subtraction. Then, the output of the adder 1, the output of the multiplier 5, and the output of the multiplier 9 are supplied, and the output of the adder 2 that adds them is supplied with the output K of the ROM 6 selected by the cutoff frequency c. Multiplier 1
0 and is multiplied by K to become an output signal.

However, in the digital filter device described above, the capacity of the ROM 6 addressed by the cutoff frequency c is equal to the selected cutoff frequency.
The larger the type of c, the larger it had to be, and therefore the larger the ROM had to be.

This invention was made in view of the above circumstances,
at least one of the coefficients of the transfer function is calculated using other coefficients of the transfer function, and at the time of calculation,
By switching and controlling the calculation method according to the type of filter to be realized, the coefficients of the transfer functions of different types of filters are obtained, and different types of filters such as a low-pass filter and a high-pass filter are configured with the same circuit configuration. The purpose of the present invention is to provide a digital filter device consisting of the following.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

That is, the coefficient data K _L and K _H in equations (14) and (15) described above are b ₁ and b ₂ in equations (12) and (13).
can be converted as follows using .

K _L = (1+b ₁ + b ₂ )/4 ...Formula (16) K _H = (1-b ₁ +b ₂ )/4 ...Formula (17) Figure 5 shows the above equations (16) and (17). This figure shows the configuration of a digital filter device when calculating coefficients K _L and K _H (collectively referred to as K) based on the relationship. In order to simplify the explanation, the same parts as in FIG. 4 are given the same reference numerals, and the explanation thereof will be omitted.

In the case of this embodiment, the multiplier 5 has a switching signal L/H.
is supplied, and when forming a low-pass filter, the output of the delay element 3 is doubled and output, and when forming a high-pass filter, it is multiplied by -2 and output. Further, the output of the delay element 7 is directly transmitted to the adder 2
supplied to

In FIG. 5, reference numeral 11 is an arithmetic circuit as shown in FIG. That is, the coefficient data b ₁ and b ₂ supplied from the ROM 6' are applied to the adder 12.
Furthermore, the value "1" is also applied to this adder 12. A switching signal L/H is further supplied to this adder 12, and when configuring a low-pass filter, the adder 12 performs the calculation of "1 + b ₁ + b ₂ ", and when configuring a high-pass filter, it performs the addition Switching control is performed in the unit 12 so that the calculation of "1-b ₁ +b ₂ " is performed.

Then, the output of this adder 12 is sent to the multiplier 13
is applied to and divided by "4". in particular,
Division is performed by shifting the decimal point position by two bits to the left. This output is then supplied as coefficient data K to the multiplier 10.

Next, the operation of the digital filter device configured as described above will be explained.

That is, when operating this digital filter device as a low-pass filter, the switching signal L/
For example, when H is set to "0", the multiplier 5 performs an operation of "x2", that is, shifts the decimal point position by 1 bit to the right. Commands that data (b ₁ , b ₂ , 1) be added. Therefore, the transfer function H _L (z) of the digital filter device is as shown in equation (7), and the digital filter device operates as a low-pass filter.

On the other hand, when operating this digital filter device as a high-pass filter, the switching signal L/
H is set to "1" and the multiplier 5 and arithmetic circuit 11 are instructed so that the multiplier 5 performs an operation of "x(-2)" and the arithmetic circuit 11 performs an operation such as equation (17). Therefore, the transfer function H _H (z) of the digital filter device is as shown in equation (8), and the digital filter device operates as a high-pass filter.

In this way, switching between the low-pass filter and the high-pass filter is only commanded by the switching signal L/H, and the digital filter device operates as a low-pass filter or a high-pass filter, and moreover, the digital filter device operates as a low-pass filter or a high-pass filter, and moreover, the digital filter device operates as a low-pass filter or a _high-pass filter. _H ) are both coefficients
Since it is calculated by b ₁ and b ₂ , the coefficient is stored in ROM6'.
You only need to memorize b ₁ and b ₂ , and the ROM
It is possible to reduce the storage capacity of 6'.

In the above embodiment, a Butterworth filter was explained, but in general, when the transfer function H(z) of a digital filter is expressed as the following equation, H(z)=K・1+a ₁ z ^-1 +a ₂ z ^-2 /1+b ₁ z ^-1 +b ₂ z ^-2
...Equation (18) Regarding the amplitude characteristic of the low-pass filter, |H(z)| approaches 0 dB (that is, the gain is 1) as the frequency becomes lower. That is, on the z ^-1 plane, as z ^-1 approaches 1 on the unit circle, |H(z)|=1 (see FIG. 7A).

Therefore, from equation (18) Since K represents gain and is usually a positive value, K=|1+b ₁ +b ₂ /1+a ₁ +a ₂ |...Equation (19).

On the other hand, the amplitude characteristic of a high-pass filter is that as the frequency increases, |H(z)| becomes 0 dB (gain is 1)
In other words, on the z ^-1 plane, z ^-1 =
As it approaches 1, |H(z)|=1 (7th
(See Figure B).

Therefore, from equation (18) K represents gain and is usually a positive value, so K=|1-b ₁ +b ₂ /1-a ₁ +a ₂ |...Equation (20).

Therefore, in both the low-pass filter and the high-pass filter, the coefficient K can be expressed using other coefficients a ₁ , a ₂ , b ₁ , and b ₂ . FIG. 8 shows a circuit configuration for calculating the coefficient K based on equations (19) and (20). Reference numerals 14 and 15 represent adders, and in the case of a low-pass filter (switching signal L/H is, for example, "0"), the adder 14 performs the calculation of "1+b ₁ +b ₂ ", and the adder 15 performs the calculation of "1+a ₁ +a ₂ ". Then, in the multiplier 16, division within the absolute value sign of equation (19) is executed, and the result is input to the absolute value circuit 17, where the value of the coefficient K is determined. In addition, when operating as a high-pass filter, the switching signal L/H
becomes “1”, and the adder 14 outputs “1−b ₁ +b ₂ ”.
is calculated, and the adder 15 calculates "1-a ₁ + a ₂ ".
As a result, the multiplier 16 executes division within the absolute sign of equation (20). The resulting output is then input to the absolute value circuit 17 to determine the value of the coefficient K. In this way, the present invention can be implemented not only in Butterworth type filters but also in general digital filter devices.

Furthermore, although the above embodiments have been described with respect to second-order filters, the present invention can be similarly applied to higher-order filters.

In other words, in the case of a high-order digital filter,
The transfer function H(z) is H(z) = K(1+a ₁ Z ^-1 +a ₂ Z ^-2 +...+a _n Z ^-m )/1+b ₁ Z ^-1 +
b ₂ Z ^-2 +...+b _o Z ^-n ... Expressed by the general formula (21).

Here, the amplitude characteristic of the low-pass filter becomes |H(z)|=1 as the frequency becomes lower,
On the Z ^-1 plane, as Z ^-1 approaches 1 on the unit circle, |H(z)|=1, holds true. Therefore, when formula (21) is substituted into formula (22), K=1+b ₁ +b ₂ +...+b _o /1+a ₁ +a ₂ +...+a _n ...
...The relational expression (23) is obtained, and K can be calculated from this equation (23).

Furthermore, the amplitude characteristic of the high-pass filter becomes |H(z)|=1 as the frequency increases, and Z ^-1
On a plane, as you approach Z ^-1 = -1 on the unit circle, |H(z)| = 1, holds true. Therefore, by substituting (21) into equation (24), K=1−b ₂ +b ₂ −…+(−1) ⁿ b _o /1−a ₁ −a ₂ −…
+(-1) ^m a _n ...The relational expression (25) is obtained, and K can be calculated by this equation (25).

It goes without saying that various other modifications and applications may be made without departing from the gist of the present invention.

As explained in detail above, the present invention calculates at least one coefficient of a transfer function using other coefficients of the transfer function, and also switches the calculation method depending on the type of filter to be realized at the time of calculation. Since the coefficients of the transfer functions of different types of filters are obtained through control, the capacity of the memory for storing coefficients can be significantly reduced, and the same circuit configuration can be used for different types of filters, such as low-pass filters and high-pass filters. In integrating digital filter devices, it is possible to calculate coefficient values, etc.
This is extremely effective.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the amplitude characteristics of a Butterworth type low-pass filter, Figure 2 is a diagram showing the poles of a second-order Butterworth type filter, Figure 3 is a diagram showing the amplitude characteristics of a Butterworth type high-pass filter, and Figure 3 is a diagram showing the amplitude characteristics of a Butterworth type high-pass filter. 4 is a diagram showing the configuration of a conventional digital filter device, FIG. 5 is a diagram showing the configuration of an embodiment of the present invention, FIG. 6 is a detailed view of the main part of FIG. 5, and FIG. FIG. 8 is a diagram illustrating the main part of the other embodiment described above. 1, 2... Adder, 3, 7... Delay element, 4, 5,
8, 10... Multiplier, 6'... ROM, 11... Arithmetic circuit, 12... Adder, 13... Multiplier, 14, 15...
Adder, 16... Multiplier, 17... Absolute value circuit.

Claims (1)

[Claims] 1. The transfer function is H(z) = K(1+a ₁ Z ^-1 +a ₂ Z ^-2 +...+a _n Z ^-m )/1+b ₁ Z ^-1 +
In the digital filter device expressed as b ₂ Z ^-2 +...+b _o Z ^-n , at least one of the multiple coefficients of the above transfer function
storage means for storing coefficients other than the coefficients;
When the conditional expression [Formula] or [Formula] holds true, from the coefficients stored in the storage means, based on the expression of the transfer function and the conditional expression, at least one of the For the arithmetic logic means that calculates one coefficient, and for the above arithmetic logic means, when specifying a low-pass filter, it is based on the conditional expression of [expression], and when specifying a high-pass filter, it is based on the conditional expression of [expression]. and a control means for performing switching control so as to cause the coefficients to be calculated by the above-mentioned storage means, and filtering the input signal according to the coefficients read from the storage means and the coefficients calculated by the arithmetic logic means, and the control means A digital filter device comprising a low-pass filter and a high-pass filter according to switching control. 2 The above digital filter device is a second-order Butterworth type filter, and the transfer function of the low-pass filter is expressed as H _L (z) = K _L (1 + Z ^-1 ) ² /1 + b ₁ Z ^-1 +b ₂ Z ^-2. , the transfer function of the high-pass filter is expressed as H _H (z) = K _H (1-Z ^-1 ) ² /1 + b ₁ Z ^-1 + b ₂ Z ^-2 , and the above storage means is determined according to the cutoff frequency. Coefficients b ₁ and b ₂ are stored, and the arithmetic logic means calculates a coefficient K _L from the coefficients b ₁ and b ₂ as K _L = (1 + b ₁ + b ₂ )/4 when the low-pass filter is designated by the control means. When the high-pass filter is specified by the control means, the coefficient K _H is calculated from the coefficients b ₁ and b ₂ by executing the calculation K _H = (1-b ₁ + b ₂ )/4. 2. The digital filter device according to claim 1, wherein the digital filter device performs the calculation by executing the following. 3 The above digital filter device is a quadratic filter whose transfer function is expressed as H(z)=K・1+a ₁ Z ^-1 +a ₂ Z ^-2 /1+b ₁ Z ^-1 +b ₂ Z ^-2 , and the above The storage means stores coefficients a ₁ , a ₂ , b ₁ , b ₂ determined according to the cutoff frequency, and the arithmetic logic means stores the coefficients a 1 , a 2 , b 1 , b 2 determined according to the cutoff frequency, and the arithmetic logic means stores the coefficients a ₁ , a 2 , b 1 , b 2 when the low-pass filter is specified by the control means. _a2 ,
The coefficient K is calculated from b ₁ and b ₂ by executing the calculation K=|1+b ₁ +b ₂ /1+a ₁ +a ₂ |, and when the high-pass filter is specified by the control means, the coefficient a ₁ , Claim 1, characterized in that the coefficient K is calculated from a ₂ , b ₁ , _and b ₂ by performing the following calculation: K=|1−b ₁ +b ₂ /1−a ₁ +a 2 | digital filter device.