JPS6336536B2 - - Google Patents

Info

Publication number
JPS6336536B2
JPS6336536B2 JP58172410A JP17241083A JPS6336536B2 JP S6336536 B2 JPS6336536 B2 JP S6336536B2 JP 58172410 A JP58172410 A JP 58172410A JP 17241083 A JP17241083 A JP 17241083A JP S6336536 B2 JPS6336536 B2 JP S6336536B2
Authority
JP
Japan
Prior art keywords
address
buffer memory
registered
tag
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58172410A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6063650A (ja
Inventor
Nobuhiko Kuribayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58172410A priority Critical patent/JPS6063650A/ja
Publication of JPS6063650A publication Critical patent/JPS6063650A/ja
Publication of JPS6336536B2 publication Critical patent/JPS6336536B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58172410A 1983-09-19 1983-09-19 バッファメモリ一致制御方式 Granted JPS6063650A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58172410A JPS6063650A (ja) 1983-09-19 1983-09-19 バッファメモリ一致制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58172410A JPS6063650A (ja) 1983-09-19 1983-09-19 バッファメモリ一致制御方式

Publications (2)

Publication Number Publication Date
JPS6063650A JPS6063650A (ja) 1985-04-12
JPS6336536B2 true JPS6336536B2 (enrdf_load_stackoverflow) 1988-07-20

Family

ID=15941436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58172410A Granted JPS6063650A (ja) 1983-09-19 1983-09-19 バッファメモリ一致制御方式

Country Status (1)

Country Link
JP (1) JPS6063650A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0271187B1 (en) * 1986-10-17 1995-12-20 Amdahl Corporation Split instruction and operand cache management
JP2806930B2 (ja) * 1987-10-20 1998-09-30 富士通株式会社 主記憶一致制御方式

Also Published As

Publication number Publication date
JPS6063650A (ja) 1985-04-12

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