JPS6336231B2 - - Google Patents

Info

Publication number
JPS6336231B2
JPS6336231B2 JP13137480A JP13137480A JPS6336231B2 JP S6336231 B2 JPS6336231 B2 JP S6336231B2 JP 13137480 A JP13137480 A JP 13137480A JP 13137480 A JP13137480 A JP 13137480A JP S6336231 B2 JPS6336231 B2 JP S6336231B2
Authority
JP
Japan
Prior art keywords
voltage
isolation transformer
transistor
switching transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13137480A
Other languages
Japanese (ja)
Other versions
JPS5755430A (en
Inventor
Toshibumi Fukuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP13137480A priority Critical patent/JPS5755430A/en
Publication of JPS5755430A publication Critical patent/JPS5755430A/en
Publication of JPS6336231B2 publication Critical patent/JPS6336231B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/338Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in a self-oscillating arrangement

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 この発明は、絶縁トランスを用いた自励式スイ
ツチングレギユレータに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a self-excited switching regulator using an isolation transformer.

自励式スイツチングレギユレータは通常チヨー
クコイルを用い、非絶縁型(入力と出力とが)の
ものとして構成される。絶縁トランスを用いて入
力と出力とを分離しようとすると、自励式のもの
は実現困難である。これは入力側と出力側とがト
ランスの相互インダクタンスで結合されているた
め、入力側で常時何らかの形で発振していなけれ
ば発振が持続できないからである。そのため従来
では第1図に示すように、周波数可変形の発振器
4を設けた他励式のものとして構成しなければな
らない。この第1図において1,5は整流平滑回
路であり、2は絶縁トランス、3はスイツチング
トランジスタ、6は電圧検出回路、7はフオトカ
プラである。出力電圧を電圧検出回路6で検出
し、フオトカプラ7を介して発振器4の周波数を
変えるようにして出力電圧を一定に保つのであ
る。しかしながらこのような構成では発振器を備
えなければならず、回路構成が複雑で小型化でき
ないという欠点がある。
A self-excited switching regulator usually uses a choke coil and is constructed as a non-isolated type (input and output). If an attempt is made to separate the input and output using an isolation transformer, it is difficult to realize a self-excited type. This is because the input side and the output side are coupled by the mutual inductance of the transformer, so oscillation cannot be sustained unless the input side always oscillates in some form. Therefore, conventionally, as shown in FIG. 1, it has to be configured as a separately excited type with a variable frequency oscillator 4. In FIG. 1, 1 and 5 are rectifier and smoothing circuits, 2 is an isolation transformer, 3 is a switching transistor, 6 is a voltage detection circuit, and 7 is a photocoupler. The output voltage is detected by a voltage detection circuit 6, and the frequency of the oscillator 4 is changed via a photocoupler 7 to keep the output voltage constant. However, such a configuration requires an oscillator, and has the disadvantage that the circuit configuration is complicated and cannot be miniaturized.

本発明は上記に鑑み、絶縁トランスを用いて入
力と出力とを分離しながら自励式として構成した
自励式スイツチングレギユレータを提供すること
を目的とする。
In view of the above, an object of the present invention is to provide a self-excited switching regulator configured as a self-excited type while separating input and output using an isolation transformer.

以下、本発明の一実施例について第2図を参照
しながら説明する。第2図において、10はダイ
オードブリツジ11とコンデンサ12とでなる整
流平滑回路であり、20は絶縁トランス、30は
スイツチングトランジスタである。50はダイオ
ード51とコンデンサ52とでなる整流平滑回路
であり、60は抵抗61と定電圧ダイオード62
とLED(発光ダイオード)63とによりなる電圧
検出回路であり、LED63はPHT(フオトトラン
ジスタ)47と光結合してフオトカプラをなして
いる。80はスイツチングトランジスタ30がス
イツチングしたときに絶縁トランス20の1次巻
線に生じるスパイク電圧を吸収するための保護回
路であり、ダイオード81とコンデンサ82と抵
抗83とにより構成される。抵抗41は電流検出
用であり、この抵抗41の両端に生じた電圧が抵
抗42とコンデンサ46とによりなる積分回路で
積分され、その積分電圧が抵抗43を通じて
PHT47のベースに印加される。また、スイツ
チングトランジスタ30のコレクタとPHT47
のベースとの間には正帰還用抵抗44が接続され
ている。スイツチングトランジスタ30は抵抗4
5で構成されるベース電流供給回路によりベース
電流の供給を受けターンオフするが、このベース
電流がPHT47のオンによつて遮断されるよう
になつている。
An embodiment of the present invention will be described below with reference to FIG. In FIG. 2, 10 is a rectifying and smoothing circuit consisting of a diode bridge 11 and a capacitor 12, 20 is an isolation transformer, and 30 is a switching transistor. 50 is a rectifying and smoothing circuit consisting of a diode 51 and a capacitor 52, and 60 is a resistor 61 and a constant voltage diode 62.
This is a voltage detection circuit consisting of an LED (light emitting diode) 63, and the LED 63 is optically coupled to a PHT (phototransistor) 47 to form a photocoupler. 80 is a protection circuit for absorbing the spike voltage generated in the primary winding of the isolation transformer 20 when the switching transistor 30 switches, and is composed of a diode 81, a capacitor 82, and a resistor 83. The resistor 41 is for current detection, and the voltage generated across the resistor 41 is integrated by an integrating circuit consisting of a resistor 42 and a capacitor 46, and the integrated voltage is transmitted through the resistor 43.
Applied to the base of PHT47. In addition, the collector of the switching transistor 30 and the PHT47
A positive feedback resistor 44 is connected between the base of the positive feedback resistor 44 and the base of the positive feedback resistor 44 . The switching transistor 30 is a resistor 4
The base current supply circuit 5 is supplied with a base current and turned off, but this base current is cut off when the PHT 47 is turned on.

第2図のa,b,c及びe,fの各点における
電圧波形は第3図にそれぞれ示されており、また
LED63の光出力dも第3図に示されている。
この第3図を参照しながら第2図の動作について
説明する。なお、以下の記述でV1〜V7は、 V1、V2;a点の電圧(V1<V2) V3;LED63が点灯するC点の電圧 V4;LED63が消灯するC点の電圧(V3>V4) V5;光入力がないときPHT47がオンするe点
の電圧 V6;光入力がないときPHT47がオフするe点
の電圧 V7;光入力がないときPHT47がオンするベー
ス電圧 とする。まず電源が投入されてa点の電圧が0か
らV1になるとトランジスタ30が直ちにオンし、
e点の電圧は徐々に上昇していく。この電圧が
V5に達するとPHT47がオンし、抵抗45を通
じてトランジスタ30のベースに流れていた電流
がPHT47を通じて流れるようになるため、ベ
ース電流が遮断されてトランジスタ30はオフと
なる。するとコンデンサ46は放電を始めるので
e点の電圧は徐々に下がり、V6にまで下がると
PHT47がオフとなり、トランジスタ30に再
びベース電流が供給されてこのトランジスタ30
がオンになる。最初のうちはこの動作が繰り返さ
れ、トランジスタ30は一定周期でオンとなり、
オンとなつている時間はt1となる。この過程でコ
ンデンサ52に徐々に充電が行なわれ、c点の電
圧が徐々に上昇していく。そのため、電源投入時
に過大な電流がコンデンサ52に流れ急速充電さ
れることが避けられ、コンデンサ52の寿命及び
信頼性が向上する。そして何回目かにトランジス
タ30がオンになつたとき、e点の電圧がV5に
達する前にc点の電圧が逐にV3に達する。従つ
てPHT47はe点の電圧がV5に達する前にLED
63の光出力によつてオンし、ベース電流を遮断
してトランジスタ30をオフとする。するとc点
の電圧が下がつてV4に達すると、LED63は消
灯する。トランジスタ30がオフとなつている間
コンデンサ46は放電しているので、e点の電圧
は更に下がつており、V6よりも下になつている。
そのため光入力がなくなるとPHT47は直ちに
オフになり、その結果トランジスタ30がオンに
なる。そのため再びc点の電圧が上昇する。そし
てV3に達するとLED63が点灯し、PHT47が
オンになり、トランジスタ30がオフになる。こ
の動作が繰り返されてトランジスタ30はオン・
オフを繰り返すが、この過程ではe点の電圧は常
にV6よりも下にあり、トランジスタ30のオ
ン・オフ周期(特にトランジスタ30がオンにな
つている時間t2)はLED63とPHT47の光
結合を含む閉ループの定数で決まり、t2はt1
より小さくなる。
The voltage waveforms at points a, b, c and e, f in Fig. 2 are shown in Fig. 3, and
The light output d of the LED 63 is also shown in FIG.
The operation shown in FIG. 2 will be explained with reference to FIG. In the following description, V1 to V7 are as follows: V1, V2; Voltage at point a (V1<V2) V3; Voltage at point C where LED 63 lights up V4; Voltage at point C where LED 63 goes off (V3>V4) V5 ; Voltage V6 at point e at which the PHT 47 is turned on when there is no optical input; Voltage V7 at point e at which the PHT 47 is turned off when there is no optical input; Base voltage at which the PHT 47 is turned on when there is no optical input. First, when the power is turned on and the voltage at point a changes from 0 to V1, the transistor 30 immediately turns on.
The voltage at point e gradually increases. This voltage
When V5 is reached, the PHT 47 is turned on, and the current that was flowing to the base of the transistor 30 through the resistor 45 begins to flow through the PHT 47, so the base current is cut off and the transistor 30 is turned off. Then, capacitor 46 starts discharging, so the voltage at point e gradually decreases, and when it drops to V6,
PHT47 is turned off, base current is again supplied to transistor 30, and this transistor 30
is turned on. At first, this operation is repeated, and the transistor 30 is turned on at regular intervals.
The time it is on is t1 . During this process, the capacitor 52 is gradually charged, and the voltage at point c gradually increases. Therefore, when the power is turned on, an excessive current flows into the capacitor 52 and rapid charging is avoided, and the life and reliability of the capacitor 52 are improved. When the transistor 30 is turned on several times, the voltage at point c reaches V3 one after another before the voltage at point e reaches V5. Therefore, PHT47 turns on the LED before the voltage at point e reaches V5.
The transistor 30 is turned on by the optical output of the transistor 63, and the base current is cut off, thereby turning off the transistor 30. Then, when the voltage at point c decreases and reaches V4, the LED 63 turns off. Since the capacitor 46 is discharging while the transistor 30 is off, the voltage at point e has further decreased and is now below V6.
Therefore, when there is no optical input, PHT 47 is immediately turned off, and as a result, transistor 30 is turned on. Therefore, the voltage at point c rises again. When the voltage reaches V3, the LED 63 lights up, the PHT 47 turns on, and the transistor 30 turns off. This operation is repeated and the transistor 30 is turned on.
Although it is repeatedly turned off, the voltage at point e is always lower than V6 during this process, and the on/off period of the transistor 30 (particularly the time t2 when the transistor 30 is on) includes the optical coupling between the LED 63 and the PHT 47. Determined by the closed loop constant, t2 is t1
become smaller.

正帰還用抵抗44は、上記の積分回路を介した
ループによる発振及び光結合を介したループによ
る発振のいずれの場合にも、トランジスタ30の
スイツチングスピードを向上させ、波形の立上
り、立下りをよくし、トランジスタ30での電力
ロスを抑える働きをする。更にこの抵抗44と抵
抗43の比は、積分回路を介したループによる発
振の場合のヒステリシス電圧V5−V6及び光結
合を介したループによる発振の場合のヒステリシ
ス電圧V3−V4を定める大きなフアクタとな
る。
The positive feedback resistor 44 improves the switching speed of the transistor 30 and reduces the rise and fall of the waveform in both cases of oscillation in the loop via the above-mentioned integrating circuit and oscillation in the loop via optical coupling. It functions to suppress power loss in the transistor 30. Furthermore, the ratio of the resistor 44 and the resistor 43 becomes a large factor that determines the hysteresis voltage V5-V6 in the case of oscillation by a loop via an integrating circuit and the hysteresis voltage V3-V4 in the case of oscillation by a loop via optical coupling. .

a点の電圧がV1からV2に上昇すると、c点の
電圧はより早くV3に達するようになるため、
LED63が点灯する位相が早くなり、PHT47
が早い位相でオンするので、トランジスタ30が
オンしている時間t3は更に短かくなる。
When the voltage at point a increases from V1 to V2, the voltage at point c will reach V3 sooner, so
The phase in which LED63 lights up becomes faster, and PHT47
Since the transistor 30 is turned on at an earlier phase, the time t3 during which the transistor 30 is turned on becomes even shorter.

負荷が短絡等して過大な出力電流が流れると、
抵抗41の両端に大きな電圧が生じe点の電圧が
上昇するため、光入力に関係なくPHT47がオ
ンしてトランジスタ30がオフする。従つて、例
えば負荷が短絡しc点の電圧が0VになつてLED
63が点灯しないような場合でも過大な電流が流
れるのを防止し、絶縁トランス20やトランジス
タ30が焼損してしまうことを防ぐことができ
る。このように過大な電流が流れたとき積分回路
を介した閉ループが働くため、このスイツチング
レギユレータの出力特性は第4図に示すようにな
り、定格最大出力電流を超えると過電流保護機能
が働く。
If the load is short-circuited and excessive output current flows,
Since a large voltage is generated across the resistor 41 and the voltage at point e increases, the PHT 47 is turned on and the transistor 30 is turned off regardless of the optical input. Therefore, for example, if the load is short-circuited and the voltage at point c becomes 0V, the LED
Even in the case where the switch 63 does not light up, it is possible to prevent excessive current from flowing and prevent the insulation transformer 20 and the transistor 30 from burning out. In this way, when an excessive current flows, a closed loop via the integrating circuit operates, so the output characteristics of this switching regulator are as shown in Figure 4, and when the rated maximum output current is exceeded, the overcurrent protection function is activated. works.

なお、電圧検出回路60として図示のものを使
用しているが、差動増巾器を用いてより正確な電
圧検出を行なうよう構成すれば、直流出力の定電
圧特性がより向上する。
Although the illustrated voltage detection circuit 60 is used, if a differential amplifier is used to perform more accurate voltage detection, the constant voltage characteristics of the DC output will be further improved.

以上、実施例について説明したように、本発明
によれば、極めて簡単な構成により絶縁トランス
を用いて入力と出力とを絶縁する自励式スイツチ
ングレギユレータが実現できる。しかも、負荷が
短絡等して過大な出力電流が流れても、電圧検出
用抵抗の両端に大きな電圧が生じフオトトランジ
スタのベース電圧が上昇するため、光入力に関係
なくフオトトランジスタがオンしてスイツチング
トランジスタがオフするので、この自励式スイツ
チングレギユレータは過電流保護機能を果たす。
従つて負荷が短絡して発光ダイオードが点灯しな
いような場合でも過大な電流が流れるのを防止
し、絶縁トランスやスイツチングトランジスタが
焼損してしまうことを防ぐことができるという効
果を有する。
As described above with respect to the embodiments, according to the present invention, a self-excited switching regulator that isolates the input and output using an isolation transformer can be realized with an extremely simple configuration. Moreover, even if the load is short-circuited and an excessive output current flows, a large voltage will be generated across the voltage detection resistor and the base voltage of the phototransistor will rise, so the phototransistor will turn on regardless of the optical input and will not switch. Since the switching transistor is turned off, this self-excited switching regulator performs an overcurrent protection function.
Therefore, even if the load is short-circuited and the light-emitting diode does not light up, it is possible to prevent an excessive current from flowing and to prevent the insulation transformer or the switching transistor from burning out.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のブロツク図、第2図は本発明
の一実施例のブロツク図、第3図は第2図の各部
の波形図、第4図は出力特性を示すグラフであ
る。 1,10,5,50……整流平滑回路、2,2
0……絶縁トランス、3,30……スイツチング
トランジスタ、4……周波数可変形発振器、6,
60……電圧検出回路、7……フオトカプラ、8
0……スパイク電圧保護回路。
FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a waveform diagram of each part of FIG. 2, and FIG. 4 is a graph showing output characteristics. 1, 10, 5, 50... Rectifier smoothing circuit, 2, 2
0...Isolation transformer, 3,30...Switching transistor, 4...Variable frequency oscillator, 6,
60... Voltage detection circuit, 7... Photocoupler, 8
0...Spike voltage protection circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁トランスと、この絶縁トランスの1次巻
線に直列に接続されて直流入力源に接続されるス
イツチングトランジスタと、このスイツチングト
ランジスタにベース電流を供給するベース電流供
給回路と、このベース電流を遮断するよう接続さ
れたフオトトランジスタと、前記絶縁トランスの
1次巻線及びスイツチングトランジスタの直列回
路に直列に接続される電流検出用抵抗と、この抵
抗の両端に生じた電圧を積分してこの積分電圧を
前記フオトトランジスタのベースに加える積分回
路と、前記絶縁トランスの1次巻線及び前記スイ
ツチングトランジスタの接続点と前記フオトトラ
ンジスタのベースとの間に接続された正帰還用抵
抗と、前記絶縁トランスの2次巻線に接続された
整流平滑回路と、この整流平滑出力の電圧を検出
し前記フオトトランジスタと光結合されている発
光ダイオードを点灯させる電圧検出回路とからな
る自励式スイツチングレギユレータ。
1. An isolation transformer, a switching transistor connected in series to the primary winding of this isolation transformer and connected to a DC input source, a base current supply circuit that supplies a base current to this switching transistor, and a base current supply circuit that supplies a base current to this switching transistor. A phototransistor connected to cut off the current, a current detection resistor connected in series to the primary winding of the isolation transformer and the series circuit of the switching transistor, and integrating the voltage generated across this resistor. an integrating circuit that applies this integrated voltage to the base of the phototransistor; a positive feedback resistor connected between the connection point of the primary winding of the isolation transformer and the switching transistor and the base of the phototransistor; A self-excited switching device comprising a rectifying and smoothing circuit connected to the secondary winding of the isolation transformer, and a voltage detection circuit that detects the voltage of the rectified and smoothed output and lights up a light emitting diode optically coupled to the phototransistor. Regulator.
JP13137480A 1980-09-19 1980-09-19 Self exciting type switching regulator Granted JPS5755430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13137480A JPS5755430A (en) 1980-09-19 1980-09-19 Self exciting type switching regulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13137480A JPS5755430A (en) 1980-09-19 1980-09-19 Self exciting type switching regulator

Publications (2)

Publication Number Publication Date
JPS5755430A JPS5755430A (en) 1982-04-02
JPS6336231B2 true JPS6336231B2 (en) 1988-07-19

Family

ID=15056439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13137480A Granted JPS5755430A (en) 1980-09-19 1980-09-19 Self exciting type switching regulator

Country Status (1)

Country Link
JP (1) JPS5755430A (en)

Also Published As

Publication number Publication date
JPS5755430A (en) 1982-04-02

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