JPS6336205B2 - - Google Patents

Info

Publication number
JPS6336205B2
JPS6336205B2 JP16366181A JP16366181A JPS6336205B2 JP S6336205 B2 JPS6336205 B2 JP S6336205B2 JP 16366181 A JP16366181 A JP 16366181A JP 16366181 A JP16366181 A JP 16366181A JP S6336205 B2 JPS6336205 B2 JP S6336205B2
Authority
JP
Japan
Prior art keywords
semiconductor
snubber circuit
wiring
capacitor
resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16366181A
Other languages
Japanese (ja)
Other versions
JPS5866575A (en
Inventor
Haruo Tetsuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56163661A priority Critical patent/JPS5866575A/en
Publication of JPS5866575A publication Critical patent/JPS5866575A/en
Publication of JPS6336205B2 publication Critical patent/JPS6336205B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08144Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in thyristor switches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Protection Of Static Devices (AREA)
  • Power Conversion In General (AREA)

Description

【発明の詳細な説明】 この発明はサイリスタ、トランジスタ、GTO
サイリスタ等の半導体で構成される半導体装置、
特に半導体と並列に接続されるスナバー回路を改
善した半導体装置に関するものである。
[Detailed Description of the Invention] This invention applies to thyristors, transistors, GTO
Semiconductor devices composed of semiconductors such as thyristors,
In particular, the present invention relates to a semiconductor device with an improved snubber circuit connected in parallel with a semiconductor.

回路電圧に対して半導体の最大定格電圧が同等
もしくは小さい場合は半導体を複数個直列に接続
して用いることは周知の如くである。半導体素子
を複数個直列に接続する場合は、電圧分担を許容
範囲内に平衡させるため半導体に並列にスナバー
回路を接続する。
It is well known that when the maximum rated voltage of a semiconductor is equal to or smaller than the circuit voltage, a plurality of semiconductors are connected in series. When a plurality of semiconductor elements are connected in series, a snubber circuit is connected in parallel to the semiconductors in order to balance voltage sharing within an allowable range.

また、半導体が高速スイツチング動作を行うも
のでは電流オフ時に半導体の両端に異常なサージ
電圧が発生し半導体の最大定格電圧を越えると半
導体が破壊するので、このサージ電圧を許容電圧
以下に制御するためにも半導体に並列にスナバー
回路が設けられる。
In addition, in semiconductors that perform high-speed switching operations, an abnormal surge voltage occurs across the semiconductor when the current is turned off, and if the maximum rated voltage of the semiconductor is exceeded, the semiconductor will be destroyed. A snubber circuit is also provided in parallel to the semiconductor.

第1図には従来の半導体装置が示されている。
図において、2個の半導体すなわちダイオード1
および2が直列に接続されており、抵抗器3,
4,5および6とコンデンサ7および8から成る
スナバー回路がダイオード1および2に並列接続
されて示されている。抵抗器3および4は定常時
の電圧分担を目的としてまた抵抗器5および6と
コンデンサ7および8とは過渡時の電圧分担とサ
ージ電圧抑制を目的として設けられる。
FIG. 1 shows a conventional semiconductor device.
In the figure, two semiconductors, namely diodes 1
and 2 are connected in series, and resistors 3,
A snubber circuit consisting of 4, 5 and 6 and capacitors 7 and 8 is shown connected in parallel with diodes 1 and 2. Resistors 3 and 4 are provided for the purpose of voltage sharing during steady state, and resistors 5 and 6 and capacitors 7 and 8 are provided for the purpose of voltage sharing during transient times and surge voltage suppression.

特にダイオード1(または2)のアノードおよ
びカソードの両電極に接続するコンデンサ7(ま
たは8)と抵抗器5(または6)の直列回路はサ
ージ電圧を抑制する目的からインダクタンスを極
力小さくすることが必要となり、通常抵抗器やコ
ンデンサの部品は無誘導構造のものを用いると共
に半導体の近傍に前記抵抗器やコンデンサの部品
を配設し配線を短かくすることによつてインダク
タンスを小さくするよう考慮している。
In particular, it is necessary to minimize the inductance of the series circuit of capacitor 7 (or 8) and resistor 5 (or 6) connected to both the anode and cathode electrodes of diode 1 (or 2) in order to suppress surge voltage. Therefore, consideration is given to reducing the inductance by using resistor and capacitor parts that have a non-inductive structure, and by arranging the resistor and capacitor parts near the semiconductor and shortening the wiring. There is.

さらに配線インダクタンスを小さくするため第
2図に示すように各部品の両端に配線する電線を
お互により合わせて配線インダクタンスを小さく
することも行なわれる。
Furthermore, in order to reduce the wiring inductance, as shown in FIG. 2, electric wires wired at both ends of each component are twisted together to reduce the wiring inductance.

しかしながら上述の抵抗器やコンデンサから成
るスナバー回路部品を半導体の近傍に設置するに
しても限度があり又第2図に示すように配線をお
互により合わすにしても全配線長さに対してより
合わせている部品の割合が小さく配線インダクタ
ンスを所定の値以下にできない場合が多々生じて
いた。
However, there is a limit to how snubber circuit components consisting of the resistors and capacitors described above can be installed near semiconductors, and even if the wires are twisted together as shown in Figure 2, it is difficult to install them in the vicinity of the semiconductor. There have been many cases in which the wiring inductance cannot be reduced to a predetermined value or less because the proportion of matched components is small.

第3図および第4図は以上の欠点をより具体的
に説明するためのもので、半導体とスナバー部品
とを1枚の絶縁板10の上に組立てて構成した半
導体ユニツトが示されている。絶縁板10の片面
には半導体1および2と、冷却フイン12を積重
ねて締付装置(図示せず)で組立てたスタツク1
1と、抵抗器5,6,3および4とが取付けられ
ており、また絶縁板10の他の面にはコンデンサ
7および8が取付けられて示されている。抵抗器
5および6の各々は並列接続された2本の抵抗器
で構成されている。
FIGS. 3 and 4 are for explaining the above drawbacks in more detail, and show a semiconductor unit in which a semiconductor and a snubber component are assembled on a single insulating plate 10. A stack 1 is formed by stacking semiconductors 1 and 2 and cooling fins 12 on one side of the insulating plate 10 and assembling them using a tightening device (not shown).
1 and resistors 5, 6, 3 and 4 are shown attached, and capacitors 7 and 8 are shown attached to the other side of the insulating plate 10. Each of resistors 5 and 6 is composed of two resistors connected in parallel.

スナバー回路の配線は、半導体1のアノード側
フインに設けた端子12aから絶縁板10を貫通
してコンデンサ7の一方の端子に配線される導線
13a、コンデンサ7の他方の端子から絶縁板1
0を貫通して抵抗器5の一方の端子に配線される
導線13b、2本の抵抗器5を並列接続するため
の導線13cおよび13d、抵抗器5の他方の端
子と半導体1のカソード側フインに設けた端子1
2bとを接続する導体13eによつて構成され
る。半導体2のスナバー回路も同様に接続されて
いる。抵抗器3および4の配線は図示を省略して
いる。
The wiring of the snubber circuit consists of a conductor 13a that is wired from a terminal 12a provided on the anode side fin of the semiconductor 1 through the insulating plate 10 to one terminal of the capacitor 7, and a conductive wire 13a that is wired from the other terminal of the capacitor 7 to the insulating plate 1.
0 and wires 13b and 13d to connect the two resistors 5 in parallel, the other terminal of the resistor 5 and the cathode side fin of the semiconductor 1. Terminal 1 provided in
The conductor 13e connects the conductor 2b. The snubber circuit of semiconductor 2 is also connected in the same way. Wiring for resistors 3 and 4 is not shown.

第3図および第4図から解るようにこのような
半導体ユニツトの構成では、半導体1または2
と、スナバー回路用の抵抗器5または6と、コン
デンサ7または8との配線を第2図に示すように
ツイストもしくはより合わすことが難しい。第3
図および第4図では配線13eと13aとをツイ
ストしているが全配線長に比べてツイストしてい
る範囲が少なく配線インダクタンスの低減効果は
極めて小さい。電気車のチヨツパ装置に用いるフ
リーホイリングダイオードのスナバー回路ではコ
ンデンサ7および8の容量を1μFとした時、抵抗
器5または6は定格電力300Wの抵抗器を2本並
列に用いている。この抵抗器1本の大きさは直径
40mm長さ450mmとなり抵抗器の両端子に接続する
導体をツイストしようとすればかえつて配線が長
くなり配線インダクタンスを増大せしめる結果と
なる。
As can be seen from FIGS. 3 and 4, in the configuration of such a semiconductor unit, semiconductor 1 or 2
It is difficult to twist or twist the wiring between the resistor 5 or 6 for the snubber circuit, and the capacitor 7 or 8 as shown in FIG. Third
Although the wirings 13e and 13a are twisted in the figures and FIG. 4, the twisted range is small compared to the total wiring length and the effect of reducing wiring inductance is extremely small. In the freewheeling diode snubber circuit used in the chopper device of electric cars, when the capacitance of capacitors 7 and 8 is 1 μF, two resistors with a rated power of 300 W are used in parallel as resistor 5 or 6. The size of this single resistor is the diameter
If the length is 40mm and the length is 450mm, and you try to twist the conductor connected to both terminals of the resistor, the wiring will become longer and the wiring inductance will increase.

第3図および第4図の半導体ユニツトでは半導
体とスナバー用抵抗器とコンデンサを極力近接し
て設置した場合を示しているが、半導体装置の構
成や冷却方式によつて種々の形態があり、特に半
導体を沸騰冷却方式で冷却する場合で、冷却タン
ク内に半導体を収納し抵抗器やコンデンサは冷却
タンクの外部に設置するものでは、半導体と抵抗
器やコンデンサを近接して配設することができな
いためスナバー回路が長くなり配線インダクタン
スが増大しサージ吸収効果が低減する。このため
にコンデンサの静電容量が増大しサージ吸収効果
を改善しているがコンデンサの静電容量を増大す
ると抵抗器の発熱量も静電容量に比例して大きく
なり半導体装置の効率低下と共に半導体装置が大
形化する傾向にあつた。
The semiconductor units in Figures 3 and 4 show the case where the semiconductor, snubber resistor, and capacitor are installed as close as possible, but there are various forms depending on the configuration of the semiconductor device and the cooling method. When semiconductors are cooled using the boiling cooling method, where the semiconductor is stored in a cooling tank and the resistors and capacitors are installed outside the cooling tank, the semiconductor and resistors and capacitors cannot be placed close to each other. Therefore, the snubber circuit becomes longer, the wiring inductance increases, and the surge absorption effect decreases. For this reason, the capacitance of the capacitor increases and improves the surge absorption effect, but when the capacitance of the capacitor increases, the amount of heat generated by the resistor also increases in proportion to the capacitance, and the efficiency of the semiconductor device decreases. There was a tendency for equipment to become larger.

この発明は上記従来装置の欠点を改善するため
になされたものでスナバー回路の配線インダクタ
ンスを効果的に抑制しサージ吸収効果を増大せし
めるようにした半導体装置を提供するものであ
る。
The present invention has been made in order to improve the drawbacks of the above-mentioned conventional devices, and provides a semiconductor device that effectively suppresses the wiring inductance of a snubber circuit and increases the surge absorption effect.

第5図はこの発明のスナバー回路の配線方法を
示す一実施例である。第5図において、抵抗器3
および4で構成される定常時用のスナバー回路は
従来と同じであるが、特に配線インダクタンスが
問題となるコンデンサ7(または8)と抵抗器5
(または6)とも直列接続した過渡時用のスナバ
ー回路に関して配線インダクタンスを低減するの
に効果的な新規な接続が示されている。
FIG. 5 shows an embodiment of the snubber circuit wiring method of the present invention. In Figure 5, resistor 3
The steady-state snubber circuit consisting of 4 and 4 is the same as the conventional one, but the capacitor 7 (or 8) and resistor 5 are particularly problematic due to wiring inductance.
(or 6) shows a novel connection that is effective for reducing wiring inductance regarding a series-connected snubber circuit for transient use.

半導体1のスナバー回路を構成するコンデンサ
7と半導体2のスナバー回路を構成するコンデン
サ8とが近接して並べて配設されており、同様に
抵抗器5と抵抗器6も並べて近接して配置されて
示されている。コンデンサ7およびコンデンサ8
の一方の同じ側の端子と、抵抗器5および抵抗器
6の一方の同じ側の端子とがそれぞれ導線14a
および14bで配線される。コンデンサ7および
8の他方の端子も、半導体1のアノード端子およ
び半導体2のカソード端子にそれぞれ導線14c
および14dで配線する。抵抗器5および6の他
端は半導体1と半導体2の接続点へそれぞれ導線
14eおよび14fで配線される。コンデンサ7
と8および抵抗器5と6とは各々近接して配設さ
れているから、上記導線14aと14b、14c
と14d、および14eと14fは各々近接して
配線することが可能で第5図に示すようにツイス
トすなわちより合わすことも容易にできる。従つ
て全配線長に対してツイスト範囲の割合を高くす
ることができる。
A capacitor 7 forming the snubber circuit of the semiconductor 1 and a capacitor 8 forming the snubber circuit of the semiconductor 2 are arranged adjacent to each other, and similarly the resistors 5 and 6 are arranged adjacent to each other. It is shown. Capacitor 7 and Capacitor 8
The terminal on the same side of one of the resistors 5 and the terminal on the same side of one of the resistors 6 are connected to the conductor 14a, respectively.
and 14b. The other terminals of capacitors 7 and 8 are also connected to conductive wires 14c to the anode terminal of semiconductor 1 and the cathode terminal of semiconductor 2, respectively.
and 14d for wiring. The other ends of resistors 5 and 6 are wired to the connection point between semiconductor 1 and semiconductor 2 by conducting wires 14e and 14f, respectively. capacitor 7
and 8 and resistors 5 and 6 are arranged close to each other, so that the conductive wires 14a, 14b, 14c
and 14d, and 14e and 14f can be wired close to each other, and can also be easily twisted or twisted as shown in FIG. Therefore, the ratio of the twist range to the total wiring length can be increased.

今、サージ電圧が発生した半導体2のカソード
側電位が半導体1のアノード側電位に比べて高く
なつた場合半導体1のスナバー回路の電流は半導
体1のカソード−抵抗器5−コンデンサ7−半導
体1のアノードの方向に流れる。一方半導体2の
スナバー回路の電流は半導体2のカソード−コン
デンサ8−抵抗器6−半導体2のアノードの方向
に流れる。このようにして配線14dと14c、
14aと14b、および14eと14fにお互に
逆方向の電流が流れるのでこれらの電線をツイス
トすることによつて通電電流による導線のまわり
に生ずる磁束を打ち消し、配線の自己インダクタ
ンスを減少させることができる。
Now, if the potential on the cathode side of the semiconductor 2 where the surge voltage has occurred is higher than the potential on the anode side of the semiconductor 1, the current in the snubber circuit of the semiconductor 1 will flow from the cathode of the semiconductor 1 to the resistor 5 to the capacitor 7 to the semiconductor 1. Flows towards the anode. On the other hand, the current in the snubber circuit of the semiconductor 2 flows in the direction of the cathode of the semiconductor 2, the capacitor 8, the resistor 6, and the anode of the semiconductor 2. In this way, the wirings 14d and 14c,
Since currents flow in opposite directions to 14a and 14b, and 14e and 14f, by twisting these wires, the magnetic flux generated around the conductor wires due to the current flow can be canceled out, and the self-inductance of the wiring can be reduced. can.

半導体1と半導体2の直列回路に異常電圧が発
生した場合半導体1と半導体2の特性によつて必
ずしも半導体1と半導体2とが異常電圧を等しく
分担するものではなく各スナバー回路に流れる電
流も同電流値でなくある程度のアンバランスを生
ずる。しかしこのスナバー回路の電流アンバラン
スは約10%程度であるから異つたスナバー回路の
配線をツイストするだけでインダクタンスの低減
効果が充分得られる。
When an abnormal voltage occurs in the series circuit of semiconductor 1 and semiconductor 2, the abnormal voltage is not necessarily shared equally between semiconductor 1 and semiconductor 2 due to the characteristics of semiconductor 1 and semiconductor 2, and the current flowing through each snubber circuit is also the same. This causes a certain amount of imbalance rather than the current value. However, the current imbalance in this snubber circuit is about 10%, so simply twisting the wiring of different snubber circuits can sufficiently reduce inductance.

第6図は抵抗器5および6と半導体1と半導体
2との接続線との配線を1本にした場合で第5図
と同様の効果が得られしかも配線が少なくなるこ
とから製作費の低減も図れる。
Figure 6 shows a case in which only one wire is used between resistors 5 and 6 and the connection line between semiconductor 1 and semiconductor 2. The same effect as in Figure 5 can be obtained, and the manufacturing cost is reduced because there are fewer wires. You can also plan.

第7図は第5図および第6図に示すこの発明の
配線方法を回路図で表わしたもので、第1図に示
す従来の回路と比べ抵抗器6とコンデンサ8が入
れ替わつているだけで性能的には全く同じ回路を
示している。
FIG. 7 is a circuit diagram showing the wiring method of the present invention shown in FIGS. 5 and 6. Compared to the conventional circuit shown in FIG. 1, only the resistor 6 and capacitor 8 are replaced. In terms of performance, they show exactly the same circuit.

第8図はこの発明による他の実施例を示す図で
半導体を2個並列に接続して用いる場合を示す。
この図に示すように半導体20と半導体21とは
電流分担をできるだけ等しくするためにリアクト
ル22および23を介して並列に接続されてい
る。半導体20用のスナバー回路はコンデンサ2
4と抵抗器26とから構成され、半導体21のス
ナバー回路はコンデンサ25と抵抗器27とから
構成されている。コンデンサ24と25および抵
抗器26と27は近接して配置し各々スナバー回
路の配線も近接もしくはツイストして配線してあ
る。第8図に示すように半導体20のスナバー回
路の配線と半導体21のスナバー回路の配線はお
互に電流方向が逆になるように半導体20および
21に接続されている。従つて半導体が並列に接
続される場合も第5図および第6図に示す直列接
続の場合と同様の効果を得ることができる。
FIG. 8 is a diagram showing another embodiment of the present invention, in which two semiconductors are connected in parallel.
As shown in this figure, semiconductor 20 and semiconductor 21 are connected in parallel via reactors 22 and 23 in order to make the current sharing as equal as possible. The snubber circuit for semiconductor 20 is capacitor 2
4 and a resistor 26, and the snubber circuit of the semiconductor 21 is composed of a capacitor 25 and a resistor 27. Capacitors 24 and 25 and resistors 26 and 27 are arranged close to each other, and the wiring of each snubber circuit is also arranged close to each other or twisted. As shown in FIG. 8, the wiring of the snubber circuit of the semiconductor 20 and the wiring of the snubber circuit of the semiconductor 21 are connected to the semiconductors 20 and 21 so that the current directions are opposite to each other. Therefore, even when semiconductors are connected in parallel, the same effects as in the case of series connection shown in FIGS. 5 and 6 can be obtained.

以上のようにこの発明によれば、半導体が並列
もしくは直列に接続され、その各々のスナバー回
路の配線をお互にツイストまたは近接させると共
に各々のスナバー回路の配線に流れる電流方向が
お互に逆方向になるようにすることにより、スナ
バー回路の配線インダクタンスを減少すると共に
半導体にかかるサージ電圧の抑制を効果的にして
いる。従つてサージ電圧が同程度の場合には、ス
ナバー回路の部品定格を低減することが可能とな
り小形かつ軽量で効率の高い半導体装置が得られ
る。
As described above, according to the present invention, semiconductors are connected in parallel or in series, the wiring of each snubber circuit is twisted or close to each other, and the directions of current flowing through the wiring of each snubber circuit are opposite to each other. By arranging the wires in the same direction, the wiring inductance of the snubber circuit is reduced and the surge voltage applied to the semiconductor is effectively suppressed. Therefore, when the surge voltages are about the same, it is possible to reduce the component ratings of the snubber circuit, and a compact, lightweight, and highly efficient semiconductor device can be obtained.

特に、この発明は簡単な構成でもつて多大の効
果を得極めて実用性の高いものである。
In particular, the present invention has a simple configuration but has great effects and is highly practical.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体とスナバー回路との構成
を示す接続図、第2図は従来のスナバー回路の配
線インダクタンスを抑制するための配線方法を示
す図、第3図は従来の半導体装置を示す図、第4
図は第3図の左側面図、第5図、第6図、および
第7図はこの発明の一実施例によるスナバー回路
配線を示す接続図、第8図はこの発明の他の実施
例によるスナバー回路配線を示す接続図である。 図において1および2はダイオード(半導体)、
5および6は抵抗器、7および8はコンデンサ、
14a〜14fは配線、20および21は半導
体、22および23はリアクトル、24および2
5はコンデンサ、26および27は抵抗器であ
る。
Figure 1 is a connection diagram showing the configuration of a conventional semiconductor and a snubber circuit, Figure 2 is a diagram showing a wiring method for suppressing the wiring inductance of a conventional snubber circuit, and Figure 3 is a diagram showing a conventional semiconductor device. Figure, 4th
The figure is a left side view of FIG. 3, FIGS. 5, 6, and 7 are connection diagrams showing snubber circuit wiring according to one embodiment of the present invention, and FIG. 8 is a diagram according to another embodiment of the present invention. FIG. 3 is a connection diagram showing snubber circuit wiring. In the figure, 1 and 2 are diodes (semiconductor),
5 and 6 are resistors, 7 and 8 are capacitors,
14a to 14f are wirings, 20 and 21 are semiconductors, 22 and 23 are reactors, 24 and 2
5 is a capacitor, and 26 and 27 are resistors.

Claims (1)

【特許請求の範囲】 1 並列又は直列に接続される複数個の半導体の
各々にスナバー回路を並列接続して構成される半
導体装置において、前記各スナバー回路を構成す
る部品を互いに近接配置し、前記各スナバー回路
の配線に流れる電流が互いに逆方向となるように
すると共に、前記各配線を互いに近接してツイス
トさせたことを特徴とする半導体装置。 2 各スナバー回路は、それぞれコンデンサ及び
抵抗器の直列接続体で構成される特許請求の範囲
第1項記載の半導体装置。
[Scope of Claims] 1. In a semiconductor device configured by connecting a snubber circuit in parallel to each of a plurality of semiconductors connected in parallel or in series, the components constituting each of the snubber circuits are arranged close to each other, and the 1. A semiconductor device characterized in that currents flowing through the wires of each snubber circuit are arranged in opposite directions, and the wires are twisted close to each other. 2. The semiconductor device according to claim 1, wherein each snubber circuit is formed of a series connection of a capacitor and a resistor.
JP56163661A 1981-10-13 1981-10-13 Semiconductor device Granted JPS5866575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56163661A JPS5866575A (en) 1981-10-13 1981-10-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56163661A JPS5866575A (en) 1981-10-13 1981-10-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5866575A JPS5866575A (en) 1983-04-20
JPS6336205B2 true JPS6336205B2 (en) 1988-07-19

Family

ID=15778175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56163661A Granted JPS5866575A (en) 1981-10-13 1981-10-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5866575A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020162648A1 (en) * 2019-02-08 2020-08-13 (주)제이월드텍 Food grinding and cooking device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0640470Y2 (en) * 1986-11-11 1994-10-19 富士電機株式会社 Static power converter GTO converter stack
JP3652934B2 (en) * 1999-09-06 2005-05-25 東芝三菱電機産業システム株式会社 Power converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020162648A1 (en) * 2019-02-08 2020-08-13 (주)제이월드텍 Food grinding and cooking device

Also Published As

Publication number Publication date
JPS5866575A (en) 1983-04-20

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