JPS6334961A - Base plate for mounting of semiconductor and its manufacture - Google Patents
Base plate for mounting of semiconductor and its manufactureInfo
- Publication number
- JPS6334961A JPS6334961A JP17812786A JP17812786A JPS6334961A JP S6334961 A JPS6334961 A JP S6334961A JP 17812786 A JP17812786 A JP 17812786A JP 17812786 A JP17812786 A JP 17812786A JP S6334961 A JPS6334961 A JP S6334961A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- mounting
- metal plate
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 83
- 238000007747 plating Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 239000004033 plastic Substances 0.000 claims description 9
- 229920003023 plastic Polymers 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000011888 foil Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000011347 resin Substances 0.000 description 15
- 229920005989 resin Polymers 0.000 description 15
- 239000000853 adhesive Substances 0.000 description 14
- 230000001070 adhesive effect Effects 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 229910000833 kovar Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 150000003918 triazines Chemical class 0.000 description 3
- 229910000906 Bronze Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- QHIWVLPBUQWDMQ-UHFFFAOYSA-N butyl prop-2-enoate;methyl 2-methylprop-2-enoate;prop-2-enoic acid Chemical compound OC(=O)C=C.COC(=O)C(C)=C.CCCCOC(=O)C=C QHIWVLPBUQWDMQ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、各種の半導体素子を搭載するために使用され
る半導体搭載用基板およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor mounting substrate used for mounting various semiconductor elements and a method for manufacturing the same.
特に本発明は、搭載された半導体素子から発生する熱放
散性に優れ、かつ外部から半導体素子へ湿気が侵入する
ことの少ない半導体搭載用基板とその製造方法を提供す
るものであり、カメラ、時計などの内装基板をはじめ、
チップキャリア、ピングリットアレイ、ハイブリッド基
板などに有利に使用される。In particular, the present invention provides a substrate for mounting a semiconductor, which has excellent heat dissipation properties generated from mounted semiconductor elements and prevents moisture from entering the semiconductor elements from the outside, and a method for manufacturing the same. Including interior substrates such as
Advantageously used in chip carriers, pin grid arrays, hybrid substrates, etc.
［従来の技術］
従来の半導体素子を直接搭載する半導体搭載用基板の材
質はプラスチックスまたはセラミックスであり、加工し
易く、コストか比較酌交いためプラスチックスが最も広
く使用されている。一般にガラスエポキシなどのプラス
チックスを使用した半導体搭載用基板は寸法精度に優れ
、機械強度もアルミナなどのセラミック基板より優れて
いるが、熱伝導率はアルミナの約ｌ／６０程度と極めて
小さい。このため従来のプラスチック基板は、集積度の
高いＩＣや消費電力の大きい半導体素子か搭載される基
板としては未だ十分に満足されていなかった。[Prior Art] Conventional materials for semiconductor mounting substrates on which semiconductor elements are directly mounted are plastics or ceramics, and plastics are most widely used because they are easy to process and cost-effective. In general, semiconductor mounting substrates made of plastics such as glass epoxy have excellent dimensional accuracy and mechanical strength that is superior to ceramic substrates such as alumina, but their thermal conductivity is extremely low at about 1/60 of that of alumina. For this reason, conventional plastic substrates have not yet been fully satisfied as substrates on which highly integrated ICs or semiconductor elements with high power consumption are mounted.
この欠点を除去改善するために熱伝導率の高い金属板を
プラスチック基板に装着し、半導体素子を前記金属板に
直接取り付けて熱放散性を向上させた構造からなる半導
体搭載用基板か従来から使用されている。In order to eliminate and improve this drawback, we have traditionally used a semiconductor mounting board with a structure in which a metal plate with high thermal conductivity is attached to a plastic substrate, and the semiconductor element is directly attached to the metal plate to improve heat dissipation. has been done.
第５図２よび第６図に従来技術による半導体搭載用基板
の縦断面図を示した。FIGS. 5-2 and 6 show vertical cross-sectional views of semiconductor mounting substrates according to the prior art.
［発明か解決しようとする問題点］
しかし、前述の半導体搭載用基板において、第５図に示
したような基板裏面側の開口部周辺に金属板を接着層を
介して接合された基板にあっては、半導体搭載用凹部を
形成する前記開口部の底面岡辺において基板と金属板と
を接合するのに用いられる接着材のはみ出しを完全にな
くすことは非常に困難であり、搭載する半導体素子の外
寸に比べ、半導体搭載部の内寸を予め大きく設計せねば
ならず装置が大型化する、またはさらに接着材のはみ出
し賃が大きくなると半導体素子を正規の位置に載置する
ことかできなくなることかあった。また第６図に示した
ような基板裏面に金属板が接合された後、前記基板表面
から前記金属板に到達するよう開口部を開削し接着材の
はみ出し部分を除去した基板にあっては、開削された金
属板の表面を完全に乎滑に加工することは困難であり、
安定した品質か得らずコストアップにつながる、もしく
は半導体素子の正規の位置、形状に搭載することができ
ない場合かあるといった欠点な有していた。[Problem to be solved by the invention] However, in the above-mentioned semiconductor mounting board, a metal plate is bonded to the board around the opening on the back side of the board via an adhesive layer as shown in FIG. Therefore, it is extremely difficult to completely eliminate the protrusion of the adhesive used to bond the substrate and the metal plate at the bottom surface of the opening that forms the semiconductor mounting recess, and the semiconductor element to be mounted The internal dimensions of the semiconductor mounting part must be designed to be larger than the external dimensions of the device, which increases the size of the device, or if the adhesive material protrudes too much, it becomes impossible to mount the semiconductor element in the correct position. Something happened. Further, in the case of a substrate in which a metal plate is bonded to the back surface of the substrate as shown in FIG. 6, an opening is cut so as to reach the metal plate from the surface of the substrate and the protruding portion of the adhesive is removed. It is difficult to process the surface of a cut-and-cut metal plate to make it completely smooth.
This method has drawbacks such as not providing stable quality, leading to increased costs, or being unable to mount the semiconductor device in the correct position and shape.
本発明はＥ記技術の有する欠点を改善した、熱放散性に
優れ信頼性が高く高密度配線の形成、装置の小型化が容
易であり、かつ基板裏面に一体形成されたメッキ被膜に
より耐湿性を向上させた半導体搭載用基板及びその製造
方法を提供することをｌＪ的とするものである。The present invention improves the drawbacks of technology described in E. It has excellent heat dissipation properties, is highly reliable, facilitates formation of high-density wiring, and miniaturization of devices, and is moisture resistant due to the plating film integrally formed on the back surface of the substrate. The purpose of the present invention is to provide a semiconductor mounting substrate with improved performance and a method for manufacturing the same.
［問題点を解決するための手段］ 以下、本発明を図面に従って詳細に説明する。[Means for solving problems] Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図〜第２図は本発明による半導体搭載用基板の縦断
面図である。第１図においてガラス−エポキシ樹脂、ガ
ラス−変性トリアジン樹脂、ガラス−ボッイミド樹脂な
どのプラスチック材料からなる上下表面に金属箔（２）
が貼付された基板（１）に表面から表面まで貫通する開
口部（３）か形成され、前記開口部（３）の基板裏面側
に前記開口部を閉塞するように金属板（４）が接着層（
５）を介して接合されることにより半導体搭載用凹部（
６）が形成されており、前記半導体搭載用凹部（６）の
底面周囲には連続した凹状の溝（７）か形成されている
。さらに前記基板（１）の裏面側の、前記金属板表面及
び前記金属板周辺領域の基板表面にはメッキ被膜（９）
か一体形成されている。1 and 2 are longitudinal sectional views of a semiconductor mounting substrate according to the present invention. In Figure 1, there are metal foils (2) on the upper and lower surfaces made of plastic materials such as glass-epoxy resin, glass-modified triazine resin, glass-boimide resin, etc.
An opening (3) penetrating from surface to surface is formed in the substrate (1) to which is pasted, and a metal plate (4) is adhered to the back side of the substrate to close the opening. layer(
5) to form a semiconductor mounting recess (
6) is formed, and a continuous concave groove (7) is formed around the bottom surface of the semiconductor mounting recess (6). Further, on the back side of the substrate (1), a plating coating (9) is formed on the surface of the metal plate and the substrate surface in the area around the metal plate.
or is formed in one piece.
ところで接着材のはみ出しを防ぐためには、接着材を前
記開口部（３）の＊壁面より内側に後退させるといった
方法かあるか、その方法ては基板（＋）と金属板（４）
との接合面積が減少するので、接着力が不足したり、搭
載された半導体素子を保護するために用いられる封＋１
：用樹脂の、接着材を後退させた部分への回り込みが悪
く、ボイドが発生しやすいといった欠点があるため、前
記問題点を解決する最良の手段とはならない。By the way, in order to prevent the adhesive from protruding, is there a way to retreat the adhesive inward from the *wall surface of the opening (3)?
Since the bonding area with
: The resin does not wrap around the area where the adhesive has been set back, and voids are likely to occur. Therefore, this is not the best means for solving the above problems.
よって、本発明では前記半導体搭載用凹部（６）の底面
周辺に連続した凹状の溝（７）を形成すると同時に前記
接着材のはみ出し部分（１１）を切削することにより前
記半導体搭載用凹部側壁を形成する基板（１）から金属
板（４）に至るまでの面を平滑にし・、接着材のはみ出
し部分をなくすることを可ス彪にした。ここで前記切削
加工において、加工精度の点で金属板（４）の一部を同
時に切削した方が安易である。Therefore, in the present invention, the side wall of the recess for semiconductor mounting is formed by forming a continuous concave groove (7) around the bottom surface of the recess for semiconductor mounting (6) and simultaneously cutting the protruding portion (11) of the adhesive. The surface from the substrate (1) to the metal plate (4) to be formed is made smooth, making it possible to eliminate any protruding parts of the adhesive. In the cutting process, it is easier to cut a part of the metal plate (4) at the same time in terms of processing accuracy.
第２図は本発明の半導体搭載用基板の他の実施態様の構
造の縦断面図を示しており、第１図と異って基板（１）
の裏面側に形成された段部（１０）に接着層（５）を介
して金属板（４）が接合されている。FIG. 2 shows a vertical cross-sectional view of the structure of another embodiment of the semiconductor mounting substrate of the present invention, and unlike FIG. 1, the substrate (1)
A metal plate (4) is bonded to a stepped portion (10) formed on the back side of the metal plate via an adhesive layer (5).
第２図における半導体搭載用基板にあっても、半導体搭
載用凹部側壁面は、：ＦＳ１図の未発ＩＴＪによる基板
と同様に前記基板（１）から金属板（４）に至るまでの
平滑なる面が形成されるとともに、半導体搭載用凹部底
面の切削加工を前記底面周囲に限定することが回部であ
るため半導体素子を直接固定する底面部分の金属板（４
）の表面は材料とする金属平板の表面形状をそのまま露
出させ、平滑な面を容易に形成することかできる。第２
１−１の半導体搭載用ノ＾板は第１ ［−Ｗに示すもの
に比較して基板全体を薄くすることが可ｆＰ、である。Even in the semiconductor mounting board shown in Fig. 2, the side wall surface of the recess for semiconductor mounting is smooth from the board (1) to the metal plate (4), similar to the board formed by the undeveloped ITJ shown in Fig. FS1. At the same time, the cutting of the bottom of the semiconductor mounting recess is limited to the circumference of the bottom, so the metal plate (4) of the bottom that directly fixes the semiconductor element is used.
) The surface shape of the flat metal plate used as the material is exposed as it is, and a smooth surface can be easily formed. Second
The semiconductor mounting plate 1-1 has fP, which allows the entire board to be thinner than the one shown in 1-W.
このように形成された半導体搭載用凹部の底面周囲の凹
状の溝は、半導体素子を該基板に装着するときに用いら
れる銀ペースト等の接着材の過剰部分の流れ込み用とし
ても利用することがてきる。また前記基板（１）のＸ面
側の、前記金属板表面および前記金属板周辺領域の基板
表面に一体形成されたメッキ被ＩＦ！Ｊ（９）により、
基板衷ｔｍからの湿気の侵入が防Ｉにされ、ひいては搭
載された半導体素子の湿気による故障や腐食を防ＩＪ−
，することに非゛潜に有効である。The concave groove around the bottom of the semiconductor mounting recess formed in this manner can also be used for flowing excess adhesive such as silver paste used when attaching a semiconductor element to the substrate. Ru. Further, an IF to be plated is integrally formed on the surface of the metal plate and the surface of the substrate in the peripheral area of the metal plate on the X-plane side of the substrate (1)! According to J(9),
The intrusion of moisture from the substrate tm is prevented, which in turn prevents the mounted semiconductor elements from malfunctioning or corroding due to moisture.
, it is non-submersible.
なお本発明の基板に用いられる接着材はエポキシ樹脂、
ポリイミド樹脂、アクリル樹脂、トリアジン樹脂あるい
はそれらの変性樹脂でありこれらの樹脂は接着性、耐熱
性、耐久性および電気絶縁性の面で優れているの゛Ｃ有
利に使用される。また金属板としては鋼、アルミニウム
５鉄あるいはそれらの合金など比較的熱伝導率の大きい
ものを有効に利用することかできる。前記メッキ被膜の
材質として銅、ニッケル、金、錫などを用いることかで
きる。Note that the adhesive used for the substrate of the present invention is epoxy resin,
Polyimide resins, acrylic resins, triazine resins, or modified resins thereof are advantageously used because these resins are excellent in terms of adhesiveness, heat resistance, durability, and electrical insulation. Further, as the metal plate, materials having relatively high thermal conductivity such as steel, aluminum 5 iron, or alloys thereof can be effectively used. Copper, nickel, gold, tin, etc. can be used as the material of the plating film.
次に、本発明の半導体搭載用基板の製造方法を図面に従
って説明する。Next, a method for manufacturing a semiconductor mounting substrate according to the present invention will be explained with reference to the drawings.
第３図（ａ）〜（ｄ）は本発明の半導体搭載用基板の縦
断面を工程順に示す図である。同図（ａ）に示すように
金属箔（２）が基板の上下表面に貼着された基板（１）
の裏面側に、半導体を搭載するための所定領域の周辺領
域のみに接着層（５）を介して金属板（４）を接合する
。次に同図（ｂ）に示すように前記金属板（４）を含む
基板（１）の外表面に一体にメッキ被膜（８） 、 （
９）を施す。次に同図（ｃ）に示すように前記基板（１
）に所望の導体回路（８）を形成する。次に同図（ｄ）
に示すように基板（１）の表面の半導体を搭載するため
の所定領域の周囲に相当する部分をエンドミルにより溝
掘り加−Ｌを前記金属板（４）の内部まで到達するよう
に施し、ト導体搭載１１１凹部（６）を形成するのと回
持に前記半導体搭載用凹部（６）の底面周囲に連続した
凹状の溝（７）を形成することにより本５１明か目的と
する基板を得ることかできる。FIGS. 3(a) to 3(d) are views showing longitudinal sections of the semiconductor mounting substrate of the present invention in order of steps. As shown in Figure (a), a substrate (1) with metal foil (2) attached to the top and bottom surfaces of the substrate.
A metal plate (4) is bonded to the back side of the metal plate (4) via an adhesive layer (5) only in the peripheral area of a predetermined area for mounting a semiconductor. Next, as shown in Figure (b), a plating film (8), (
9). Next, as shown in FIG.
) to form a desired conductor circuit (8). Next, the same figure (d)
As shown in Figure 2, grooves are cut using an end mill in a portion corresponding to the periphery of a predetermined area for mounting a semiconductor on the surface of the substrate (1) so as to reach the inside of the metal plate (4). By forming the concave portion (6) of the conductor mounting 111 and forming a continuous concave groove (7) around the bottom of the semiconductor mounting concave portion (6) for recirculation, the desired substrate can be obtained. I can do it.
なおこのように加「された後にあっては、半導体搭載用
四Ｆ？Ｒ（６）内に゛ト導体素子か銀ペーストなどを介
して実装される。After being added in this manner, it is mounted within the semiconductor mounting fourth frame resistor (6) via a conductor element or silver paste.
第４図（ａ）〜（ｅ）は本発明の半導体搭載用基板の他
の実施態様の縦断面を工程順に示す図である。同図（ａ
）に示すように金属箔（２）が基板の旧下表面に一貼着
された基板（１）の裏面側にエンドミルを用いて凹部（
ｌＯ）を形成する。次に同図（ｂ）に示すように前記凹
部（１０）の底面に金属板（４）を半導体を搭載するた
めの所定領域の周辺領域のみに接着層（５）を介して接
合する。次に同図（ｃ）に示すように前記金属板（４）
を含む基板（＋）の外表面に一体にメッキ被膜（８）
、 （９）を施す。次に同ＩＡ（ｄ）に示すように前記
基板（１）に所望の導体回路（８）を形成する。次に同
図（ｅ）に示すように基板（１）の表面の半導体を搭載
するための所定領域の周辺に相当する部分をエンドミル
により溝掘り加［を前記金属板（４）の内部まで到達す
るように施し、半導体搭載用凹部（５）を形成するのと
同時に前記半導体搭載用凹部（６）の底面周囲に連続し
た凹状の構（７）を形成することにより本発明が目的と
する基板を得ることかできる。FIGS. 4(a) to 4(e) are views showing longitudinal sections of another embodiment of the semiconductor mounting substrate of the present invention in the order of steps. The same figure (a
), use an end mill to cut a recess (
form lO). Next, as shown in FIG. 4B, a metal plate (4) is bonded to the bottom surface of the recess (10) via an adhesive layer (5) only in the peripheral area of a predetermined area for mounting a semiconductor. Next, as shown in the same figure (c), the metal plate (4)
A plating film (8) is integrally formed on the outer surface of the substrate (+) including
, Perform (9). Next, as shown in IA(d), a desired conductor circuit (8) is formed on the substrate (1). Next, as shown in FIG. 2(e), a groove is dug with an end mill in a portion corresponding to the periphery of a predetermined area on the surface of the substrate (1) for mounting a semiconductor [to reach the inside of the metal plate (4). By forming a continuous concave structure (7) around the bottom of the semiconductor mounting recess (6) at the same time as forming the semiconductor mounting recess (5), the substrate which is the object of the present invention can be obtained. Can you get it?
以下実施例に基づいてさらに説明する。Further explanation will be given below based on examples.
［実施例］
実施例１
第１１ｇにおいてガラス−エポキシ樹脂かうなる基板（
１）のＬ下表面には銅箔（２）が貼着されており、前記
ノ、（板（１）の表面側に矩形に中抜き加工を施したエ
ポキシ樹脂からなる接着シート （５）を介してコバー
ル板（４）を接合した。次に、 ＋ｉ’ｉｉ記基板（１
）およびコバール板（４）の外表面全体に銅メッキ（８
） 、 （９）を施し、感光性樹脂フィルムを貼着し露
光現像して回路パターンを形成したのち、エウチングを
行ない、さらに導体表面にニッケルメッキ、金メッキを
施すことによって導体回路（８）および基板寞面側のメ
ッキ被膜（９）を形成した。[Example] Example 1 In the 11th g, a glass-epoxy resin substrate (
Copper foil (2) is pasted on the lower surface of L of 1), and an adhesive sheet (5) made of epoxy resin with a rectangular hollow cut on the surface side of the plate (1) is attached. The Kovar plate (4) was joined through the +i'ii board (1).
) and the entire outer surface of the Kovar plate (4) is copper plated (8
), (9) are applied, a photosensitive resin film is attached, exposed and developed to form a circuit pattern, etching is performed, and the conductor surface is further plated with nickel and gold to form the conductor circuit (8) and the board. A plating film (9) was formed on the top side.
そののち基板（１）の表面からエンドミルによりコバー
ル板（４）に到達する深さまで矩形に溝掘り加工を施し
、基板（１）の一部分を除去することにより半導体搭載
用凹部（６）と前記凹部（６）の底面周囲に連続した凹
状の溝（７）とを同時に形成し１本発明による゛ト導体
ＮＳ佐用基板を製作した。Thereafter, a rectangular groove is cut from the surface of the substrate (1) using an end mill to a depth that reaches the Kovar plate (4), and a part of the substrate (1) is removed to form a semiconductor mounting recess (6) and the recess. At the same time, a continuous concave groove (7) was formed around the bottom surface of (6) to produce a substrate for use in a conductor NS according to the present invention.
実施例２
第２図においてガラス−変性トリアジン樹脂からなるノ
＾板（１）のに下表面には銅箔（２）か貼着されており
、前記ノ、（板（１）の裏面側にエンドミルを用いて切
消加工を施し凹部（１０）を形成した。次に前記凹部内
にガラス−変性トリアジン樹脂からなる接着シートを矩
形に中抜きして載置しリン青銅板（４）を合わせたのち
１５０°Ｃ３０分の加圧加熱を施して接合した。そのの
ち前記基板（１）およびリンｎ銅板（４）の外表面全体
に銅メッキを施し、基板表面に感光性樹脂フィルムを貼
付し、所望の回路パターン以外の部分に前記感光性樹脂
フィルムを残すように露光現像し、所望の回路パターン
」−のみに銅メッキ、はんだメッキを施し前記はんだメ
ッキをエツチングレジストとしてエツチングを行ない、
さらに導体表面にニッケルメッキ、金メッキを施すこと
により導体回路（８）および基板裏面側のメ・ツキ被膜
（９）を形成した。そののち基板（１）の表面からエン
ドミルによりリン青銅板（４）に到達する深さまで溝掘
り加工を施し、基板（１）の一部分を除去することによ
り半導体ＮＳａ用凹部（６）と、前記半導体搭載用凹部
（６）の底面周囲に連続した凹状の１１１（７）とを同
時に形成し、本発明による半導体搭載用基板を製作した
。Example 2 In Fig. 2, a copper foil (2) is pasted on the bottom surface of the plate (1) made of glass-modified triazine resin, and a copper foil (2) is pasted on the bottom surface of the plate (1). A recess (10) was formed by cutting using an end mill.Next, an adhesive sheet made of glass-modified triazine resin was cut into a rectangular shape and placed in the recess, and a phosphor bronze plate (4) was placed thereon. Afterwards, they were bonded by applying pressure and heating at 150°C for 30 minutes.Then, the entire outer surfaces of the substrate (1) and the phosphorus n copper plate (4) were plated with copper, and a photosensitive resin film was attached to the surface of the substrate. , exposing and developing the photosensitive resin film so as to leave it in areas other than the desired circuit pattern, applying copper plating and solder plating only to the desired circuit pattern, and performing etching using the solder plating as an etching resist;
Further, the surface of the conductor was plated with nickel and gold to form a conductor circuit (8) and a metal coating (9) on the back side of the substrate. Thereafter, trenching is performed from the surface of the substrate (1) to a depth reaching the phosphor bronze plate (4) using an end mill, and a part of the substrate (1) is removed to form a recess (6) for the semiconductor NSa and the semiconductor A continuous concave shape 111 (7) was simultaneously formed around the bottom of the mounting concave portion (6) to produce a semiconductor mounting substrate according to the present invention.
第７図は本発明の半導体搭載用基板を用いて製作された
ピングリットアレイの一実施例を示す基板の裏面から見
た斜視図であり、また第８図は第７１：４に示す基板を
Ａ−Ａに沿って切った縦断面図である。このビングリウ
ドアレイは本発明の半導体搭載用基板（１）の賽導体搭
載用凹部（６）に半導体素−ｆ−（＋８）か搭載された
のち、ワイヤーボンデインクされさらに周囲をエポキシ
樹脂（２０）で封止されている。また基板（１）の金属
板（４）との反対面側には封止樹脂用枠板（１３）が接
着層（Ｉ４）を介して接合されるとともに、外部接続用
の導体ビン（＋６）か前記封止樹脂用枠板（１３）を４
通した形で導体回路と電気的に接続したスルーホール（
１５）に固定されている。FIG. 7 is a perspective view showing an embodiment of the pin grid array manufactured using the semiconductor mounting substrate of the present invention, as seen from the back side of the substrate, and FIG. 8 is a perspective view of the substrate shown in No. 71:4. It is a longitudinal cross-sectional view taken along A-A. This Bingliou array is made by mounting a semiconductor element -f- (+8) in the recess (6) for mounting a semiconductor in the semiconductor mounting substrate (1) of the present invention, and then wire bonding and surrounding it with epoxy resin ( 20). In addition, a sealing resin frame plate (13) is bonded to the side opposite to the metal plate (4) of the substrate (1) via an adhesive layer (I4), and a conductor bottle (+6) for external connection is bonded to the side opposite to the metal plate (4). or the frame plate (13) for the sealing resin 4
A through hole (through which the conductor circuit is electrically connected)
15).
［発明の効果］
以１−のように本発明による半導体搭載用基板にあって
は、基板と金属板を接合する際に生ずる半導体ＮＳ佐部
への接着材のはみ出し部分か完全に除去されるので゛ト
導体搭載用凹部を有効に利用することかてき、半導体Ｗ
？佐用基板の小型化か容易である。また半導体搭載用凹
部の底面を平滑に仕上げることが容易てあり、かつ半導
体素子を前記基板に固定する際に用いられるペーストの
過剰部分をＴｉ′ｉｉ記凹部岡囲の溝に流し込むことか
できるため搭載される半導体素子の位置精度の向上、３
よび該基板か安定した品質て得られることによるコスト
ダウンを［Ａることか可ｆ七である。[Effects of the Invention] As described in 1- below, in the semiconductor mounting board according to the present invention, the protruding portion of the adhesive material to the semiconductor NS section that occurs when the board and the metal plate are bonded can be completely removed. Therefore, it is possible to effectively utilize the recess for mounting the conductor.
? It is easy to downsize the service board. In addition, it is easy to finish the bottom surface of the recess for semiconductor mounting smoothly, and the excess portion of the paste used for fixing the semiconductor element to the substrate can be poured into the groove surrounding the recess described in Ti'ii. Improving the positional accuracy of mounted semiconductor elements, 3
It is also possible to reduce costs by obtaining stable quality of the substrate.
さらに、この上導体ＭＳ佐用基板にあっては、その金属
板表面及びこの金属板の周辺領域の基板表面にメッキ被
膜を形成したから、これによって！−記全金属板保護さ
れるとともに当該半導体搭載用基板の耐湿性が向ヒして
いる。Furthermore, in the case of the above-mentioned conductor MS service board, a plating film was formed on the surface of the metal plate and the surface of the board in the peripheral area of this metal plate. - The entire metal plate is protected and the moisture resistance of the semiconductor mounting board is improved.
第１図は本発明による゛ｈ導体搭載用基板のＩｆ断面図
、第２１Ａは本発明の半導体搭載用基板の他の実施態様
の構造の縦断面図である。第３図は本発明による半導体
搭載用基板の縦断面を工程順に示すｌ：４であり、第４
図は本発明の半導体搭載用基板の他の実施態様の縦断面
を工程順に示した図である。第５図および第６図はそれ
ぞれ従来例の半導体搭載用基板の縦断面図である。第７
図は未発ＩＪＩＩの゛ｉ導体搭載用基板を用いて製作さ
れたピングリットアレイの一例を示す基板を裏面から見
た斜視図てあり、また第８図は第７図に示す基板なＡ−
Ａｈａに沿って切った縦断面図である。
符号の説ＩＩ
ｌ・・・基板、２・・・銅箔、３・・・開口部、４・・
・金属板。
５−・・接１１′層、６・・・半導体搭載用凹部、７・
・・凹状の溝、８・・・導体回路、９・・・メッキ被膜
、ＩＯ・・・凹部。
１１・・・接着材のはみたし部分、＋２−・・寥導体搭
載用凹部底面の凹凸、【３・・・封１１−樹脂用枠板、
Ｉ４・・・接着層、１５・・・スルーホール、 ＋６・
・・導体ビン、１７・・・導体ビンの鍔、１８・・・半
導体素子、１９・・・ボンディングワイヤー、２０・・
・封］１−樹脂。
第１図
第２図
ｉ３図 第４ズ
（ａ ） （ａ ）第５図
第６図
第７図
第８図FIG. 1 is a cross-sectional view of the If conductor mounting substrate according to the present invention, and FIG. 21A is a vertical cross-sectional view of the structure of another embodiment of the semiconductor mounting substrate of the present invention. FIG. 3 shows the vertical cross section of the semiconductor mounting substrate according to the present invention in the order of steps l:4;
The figures are longitudinal cross-sectional views showing another embodiment of the semiconductor mounting substrate of the present invention in the order of steps. 5 and 6 are longitudinal sectional views of conventional semiconductor mounting substrates, respectively. 7th
The figure is a perspective view from the back of a board showing an example of a pin grid array fabricated using the undeveloped IJII i-conductor mounting board, and Fig. 8 is a perspective view of the board shown in Fig. 7.
It is a longitudinal cross-sectional view taken along Aha. Code theory II l...Substrate, 2...Copper foil, 3...Opening, 4...
・Metal plate. 5--Contact 11' layer, 6--Semiconductor mounting recess, 7-
...Concave groove, 8...Conductor circuit, 9...Plating film, IO...Concave portion. 11...Adhesive filler part, +2-...Irregularities on the bottom of the recess for mounting the conductor, [3...Sealing 11-Resin frame board,
I4...Adhesive layer, 15...Through hole, +6.
... Conductor bottle, 17... Flange of conductor bottle, 18... Semiconductor element, 19... Bonding wire, 20...
・Sealing] 1-Resin. Figure 1 Figure 2 i3 Figure 4 (a) (a) Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
体搭載領域に、前記基板の表面から裏面まで貫通する開
口部が形成されており、前記開口部の基板裏面側に前記
開口部を閉塞するように金属板が接着層を介して接合さ
れることにより半導体搭載用凹部が形成された半導体搭
載用基板において、 前記半導体搭載用凹部の底面周囲に連続した凹状の溝が
形成されており、 かつ前記基板裏面側の、前記金属板表面および前記金属
板周辺領域の基板表面にはメッキ被膜が一体形成されて
なることを特徴とする半導体搭載用基板。 ２、前記半導体搭載用基板の前記開口部の基板裏面側の
周辺領域には段部が形成されており、前記段部に金属板
か接着層を介して接合されていることを特徴とする特許
請求の範囲第１項記載の半導体搭載用基板。 ３、下記（ａ）〜（ｄ）の工程からなる半導体搭載用基
板の製造方法。 （ａ）プラスチック材料からなるプリント配線用基板の
裏面側に、前記基板の半導体を搭載するための所定領域
の周辺のみに接着層を介して金属板を接合する工程； （ｂ）前記金属板を含む基板の外表面にメッキを施す工
程： （ｃ）前記基板に導体回路を形成する工程：（ｄ）前記
基板の半導体を搭載するための所定領域の周囲に相当す
る部分に前記金属板の内部まで到達する連続した溝掘り
加工を施すことにより、前記基板の一部分を除去し半導
体搭載用凹部を形成すると同時に、前記半導体搭載用凹
部の底面周囲に連続した凹状の溝を形成する工程。 ４、下記（ａ）〜（ｅ）の工程からなる半導体搭載用基
板の製造方法。 （ａ）プラスチック材料からなるプリント配線用基板の
半導体を搭載するための所定領域の裏面に凹部を形成す
る工程； （ｂ）前記凹部内の底面に半導体を搭載するための所定
領域の周辺のみに接着層を介して金属板を接合する工程
； （ｃ）前記金属板を含む基板の外表面にメッキを施す工
程； （ｄ）前記基板に導体回路を形成する工程；（ｅ）前記
基板の半導体を搭載するための所定領域の周囲に相当す
る部分に前記基板の内部まで到達する連続した溝掘り加
工を施すことにより、前記基板の一部分を除去し半導体
搭載用凹部を形成すると同時に、前記半導体搭載用凹部
の底面周囲に連続した凹状の溝を形成する工程。[Claims] 1. An opening penetrating from the front surface to the back surface of the substrate is formed in the semiconductor mounting area of a semiconductor mounting substrate made of a plastic material, and the opening portion is formed on the back surface side of the substrate of the opening portion. In a semiconductor mounting substrate in which a semiconductor mounting recess is formed by bonding a metal plate through an adhesive layer so as to close the semiconductor mounting recess, a continuous recessed groove is formed around the bottom surface of the semiconductor mounting recess. 1. A semiconductor mounting board, wherein a plating film is integrally formed on the surface of the metal plate and the surface of the substrate in the peripheral area of the metal plate on the back side of the substrate. 2. A patent characterized in that a stepped portion is formed in a peripheral area on the back side of the substrate of the opening of the semiconductor mounting substrate, and the stepped portion is bonded to the stepped portion via a metal plate or an adhesive layer. A semiconductor mounting board according to claim 1. 3. A method for manufacturing a semiconductor mounting substrate comprising the following steps (a) to (d). (a) A step of bonding a metal plate to the back side of a printed wiring board made of a plastic material via an adhesive layer only around a predetermined area for mounting a semiconductor on the board; (b) (c) forming a conductor circuit on the substrate; (d) plating the inside of the metal plate in a portion corresponding to the periphery of a predetermined area for mounting a semiconductor on the substrate; (c) forming a conductor circuit on the substrate; A step of removing a portion of the substrate to form a semiconductor mounting recess by performing a continuous groove digging process that reaches up to the depth of the semiconductor mounting recess, and at the same time forming a continuous recessed groove around the bottom surface of the semiconductor mounting recess. 4. A method for manufacturing a semiconductor mounting substrate comprising the following steps (a) to (e). (a) Forming a recess on the back surface of a predetermined region for mounting a semiconductor on a printed wiring board made of plastic material; (b) Forming a recess only around the predetermined region for mounting a semiconductor on the bottom surface of the recess. (c) plating the outer surface of the substrate including the metal plate; (d) forming a conductor circuit on the substrate; (e) semiconductor of the substrate By performing a continuous trenching process that reaches the inside of the substrate in a portion corresponding to the periphery of a predetermined area for mounting the semiconductor, a part of the substrate is removed and a recess for mounting the semiconductor is formed, and at the same time, the semiconductor mounting A process of forming a continuous concave groove around the bottom of the concave part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17812786A JPH0746708B2 (en) | 1986-07-29 | 1986-07-29 | Semiconductor mounting substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17812786A JPH0746708B2 (en) | 1986-07-29 | 1986-07-29 | Semiconductor mounting substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6334961A true JPS6334961A (en) | 1988-02-15 |
| JPH0746708B2 JPH0746708B2 (en) | 1995-05-17 |
Family
ID=16043126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17812786A Expired - Lifetime JPH0746708B2 (en) | 1986-07-29 | 1986-07-29 | Semiconductor mounting substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746708B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6178027B1 (en) | 1996-03-08 | 2001-01-23 | Nihon Shingo Kabushiki Kaisha | Optical barrier apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220012075A (en) | 2020-07-22 | 2022-02-03 | 삼성전기주식회사 | Printed circuit board |
-
1986
- 1986-07-29 JP JP17812786A patent/JPH0746708B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6178027B1 (en) | 1996-03-08 | 2001-01-23 | Nihon Shingo Kabushiki Kaisha | Optical barrier apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0746708B2 (en) | 1995-05-17 |
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