JPS6333601U - - Google Patents
Info
- Publication number
- JPS6333601U JPS6333601U JP1986126852U JP12685286U JPS6333601U JP S6333601 U JPS6333601 U JP S6333601U JP 1986126852 U JP1986126852 U JP 1986126852U JP 12685286 U JP12685286 U JP 12685286U JP S6333601 U JPS6333601 U JP S6333601U
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- resistor
- circuit board
- interposed
- interval
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
Landscapes
- Multi-Conductor Connections (AREA)
- Combinations Of Printed Boards (AREA)
- Details Of Resistors (AREA)
Description
第１図ａ，ｂ，ｃは本考案による一実施例の斜
視図、第２図は本考案による他の一実施例の斜視
図、第３図は本実施例を実装した斜視図、第４図
は従来技術による斜視図、第５図は従来リード端
子を実装した斜視図、である。
図において、１は抵抗体、１‐１は抵抗体付き
リード端子、１ａは絶縁体（磁器管）、１ｂは導
電性キヤツプ、１ｃは金属膜、１ｄは抵抗線、１
０はリード端子、１０ａ，１０ｂは接続部、１０
ｃは中間部、２０‐１は第１の回路基板、２１は
第２の回路基板、を示す。
Figures 1a, b, and c are perspective views of one embodiment of the present invention; Figure 2 is a perspective view of another embodiment of the invention; Figure 3 is a perspective view of the embodiment; The figure is a perspective view of a conventional technique, and FIG. 5 is a perspective view of a conventional lead terminal mounted thereon. In the figure, 1 is a resistor, 1-1 is a lead terminal with a resistor, 1a is an insulator (porcelain tube), 1b is a conductive cap, 1c is a metal film, 1d is a resistance wire, 1
0 is a lead terminal, 10a, 10b are connection parts, 10
20-1 is the first circuit board, and 21 is the second circuit board.
Claims (1)
両端の接続部１０ａ，１０ｂをそれぞれ接続し、
第１の回路基板を保持するリード端子１０におい
て、該リード端子１０の中間部１０ｃに所定の抵
抗を有する抵抗体１を介在させてなることを特徴
とする抵抗体付きリード端子。 Connecting the connecting parts 10a and 10b at both ends to the first and second circuit boards arranged side by side with an interval, respectively,
A lead terminal with a resistor, characterized in that, in a lead terminal 10 holding a first circuit board, a resistor 1 having a predetermined resistance is interposed in an intermediate portion 10c of the lead terminal 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986126852U JPS6333601U (en) | 1986-08-19 | 1986-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986126852U JPS6333601U (en) | 1986-08-19 | 1986-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6333601U true JPS6333601U (en) | 1988-03-04 |
Family
ID=31021050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986126852U Pending JPS6333601U (en) | 1986-08-19 | 1986-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6333601U (en) |
-
1986
- 1986-08-19 JP JP1986126852U patent/JPS6333601U/ja active Pending