JPS6333040A - Interface circuit - Google Patents
Interface circuitInfo
- Publication number
- JPS6333040A JPS6333040A JP61175511A JP17551186A JPS6333040A JP S6333040 A JPS6333040 A JP S6333040A JP 61175511 A JP61175511 A JP 61175511A JP 17551186 A JP17551186 A JP 17551186A JP S6333040 A JPS6333040 A JP S6333040A
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- high frequency
- circuit
- transmission
- jitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000005540 biological transmission Effects 0.000 claims description 44
- 239000000284 extract Substances 0.000 claims 2
- 230000001360 synchronised effect Effects 0.000 abstract description 6
- 239000000306 component Substances 0.000 abstract 8
- 238000010586 diagram Methods 0.000 description 9
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はインタフェース回路に係り、特に、デジタルオ
ーディオ機器やデジタルビデオ機器等、伝送デジタル信
号に微小な不要成分（高周波成分やジッタ成分）が重畳
されていても、伝送デジタル信号の論理符号に応じた常
に波形一定の受信デジタル信号を得ることを必要とする
回路に関する。[Detailed Description of the Invention] Industrial Field of Application The present invention relates to interface circuits, and in particular to interface circuits used in digital audio equipment, digital video equipment, etc., in which minute unnecessary components (high frequency components and jitter components) are superimposed on transmitted digital signals. The present invention also relates to a circuit that needs to obtain a received digital signal whose waveform is always constant according to the logical code of the transmitted digital signal.
従来の技術
第６図及び第７図は従来のインタフェース回路の各個の
回路図を示す。各図において、伝送側回路１の入力端子
２に入来した伝送デジタル信号は伝送線３を介して受信
側回路４に伝送され、出力端子５より取出される。この
場合、一般に、伝送デジタル信号の論理符号ＭＪ ｒ
ＯＪそのものは正しく受信デジタル信号として取出され
ても、受信デジタル信号の波形そのものに着目した場合
、伝送デジタル信号波形の高周波成分やジッタ成分の影
響を受ける。つまり、論理符号は同じであっても、伝送
デジタル信号波形及び伝送側回路１の状態によって受信
デジタル信号波形は種々異なることになる。PRIOR ART FIGS. 6 and 7 show respective circuit diagrams of conventional interface circuits. In each figure, a transmission digital signal that has entered an input terminal 2 of a transmission side circuit 1 is transmitted to a reception side circuit 4 via a transmission line 3, and is taken out from an output terminal 5. In this case, generally the logical code MJ r of the transmitted digital signal
Even if the OJ itself is correctly extracted as a received digital signal, when focusing on the waveform of the received digital signal itself, it is affected by high frequency components and jitter components of the transmitted digital signal waveform. In other words, even if the logic codes are the same, the received digital signal waveforms will vary depending on the transmitted digital signal waveform and the state of the transmission side circuit 1.
発明が解決しようとする問題点
従来装置は、伝送デジタル信号の論理符号を正しく伝送
することのみに注意が払われており、上記のように、受
信デジタル信号の波形そのものに着目した場合、伝送デ
ジタル信号波形の高周波成分やジッタ成分の影響が常に
現われる問題点があった。Problems to be Solved by the Invention Conventional devices pay attention only to correctly transmitting the logical code of the transmitted digital signal, and as mentioned above, when focusing on the waveform itself of the received digital signal, the transmitted digital There was a problem in that the influence of high frequency components and jitter components of the signal waveform always appeared.
本発明は、伝送側回路の伝送デジタル信号波形が高周波
成分及びジッタ成分等によって微小に変化してもその論
理符号ｒ１Ｊ ｒＯＪが変化しない限り常に波形一定
の受信デジタル信号を得ることができるインタフェース
回路を提供することを目的とする。The present invention provides an interface circuit that can always obtain a received digital signal with a constant waveform even if the transmitted digital signal waveform of the transmission side circuit slightly changes due to high frequency components, jitter components, etc., as long as its logical code r1J rOJ does not change. The purpose is to provide.
問題点を解決するための手段
第１図において、タイミング制御信号発生器１６、Ｄフ
リップフロップ１４は伝送デジタル信号に重畳されるジ
ッタ成分を除去して取出すジッタ成分除去手段、定電圧
回路１８、定電流制限用抵抗１９はジッタ成分除去手段
の出力信号に重畳される高周波成分を除去し伝送線を経
て受信側回路１１に取出す高周波成分除去手段の各−実
施例であり、第４図において、定電圧回路１８、定電流
制限用抵抗１９は伝送デジタル信号に重畳される高周波
成分を除去する手段、タイミング制御信号発生器１６、
Ｄフリップフロップ１４は伝送線を経て入来した伝送デ
ジタル信号に重畳されるジッタ成分を除去して取出す手
段の各−実施例である。Means for Solving the Problems In FIG. 1, the timing control signal generator 16 and the D flip-flop 14 are jitter component removing means for removing and extracting jitter components superimposed on the transmitted digital signal, a constant voltage circuit 18, and a constant voltage circuit 18. The current limiting resistor 19 is an embodiment of the high frequency component removing means that removes the high frequency component superimposed on the output signal of the jitter component removing means and takes it out to the receiving side circuit 11 via the transmission line. A voltage circuit 18, a constant current limiting resistor 19 is a means for removing high frequency components superimposed on the transmitted digital signal, a timing control signal generator 16,
The D flip-flop 14 is an embodiment of a means for removing and extracting jitter components superimposed on a transmitted digital signal input via a transmission line.
作用
Ｄフリップフロップにてジッタ成分を除去し、定電流制
御回路にて高周波成分を除去しているので、伝送デジタ
ル信号に微小変化があっても常に波形一定の受信デジタ
ル信号を取出し得る。Since the jitter component is removed by the D flip-flop and the high frequency component is removed by the constant current control circuit, a received digital signal with a constant waveform can always be obtained even if there is a slight change in the transmitted digital signal.
実施例
第１図は本発明回路の第１実施例のブロック系統図を示
す。同図において、伝送側回路１０及び受信側回路１１
は結合部１２における伝送線２８ａ。Embodiment FIG. 1 shows a block diagram of a first embodiment of the circuit of the present invention. In the figure, a transmission side circuit 10 and a reception side circuit 11
is the transmission line 28a in the coupling section 12.
２８ｂ及びトランジスタＱ１で接続されており、電源及
びＧＮＤは夫々別である。デジタル信号同期化制御回路
１３から取出された伝送デジタル信号ａ（第２図（Ａ）
）（高周波成分及びジッタ成分を含む）はＤフリップフ
ロップ１４に供給され、ここで、原信号発生器１５の出
力原信号からタイミング制御信号発生器１６によって作
られた同期クロックｂ（同図（Ｂ））に同期してジッタ
成分を除去された伝送デジタル信号Ｃ（同図（Ｃ））と
される。この場合、同期クロックｂは伝送デジタル信号
ａのジッタ成分のタイミング以外のタイミングで発生す
るように設定されている。28b and transistor Q1, and the power supply and GND are separate from each other. Transmission digital signal a taken out from the digital signal synchronization control circuit 13 (Fig. 2 (A)
) (including high frequency components and jitter components) is supplied to the D flip-flop 14, where the synchronized clock b (in the same figure (B )), the jitter component is removed in synchronization with the transmitted digital signal C ((C) in the same figure). In this case, the synchronous clock b is set to occur at a timing other than the timing of the jitter component of the transmitted digital signal a.
なお、伝送デジタル信号ａはタイミング制御信号発生器
１６から取出される同期信号に同期して取出される。Note that the transmission digital signal a is taken out in synchronization with a synchronization signal taken out from the timing control signal generator 16.
Ｄフリップフロップ１４から取出された伝送デジタル信
号Ｃは制御用ドライバ１７に供給され、制御用ドライバ
１７は伝送デジタル信号Ｃの論理符号が「１」の時オン
となり、これにより、結合部１２のトランジスタＱ１は
オフ状態となる。逆に、制御用ドライバ１７は伝送デジ
タル信号Ｃの論理符号が「０」の時オフとなり、これに
より定電圧回路１８から定電流制限用抵抗１９（Ｒａ）
、ダイオード２０を介して一定電流が流れ、トランジス
タＱ１はオンになる。この場合、定電圧回路１８、定電
流制限用抵抗１９により、伝送デジタル信号Ｃにいかな
る高周波成分が含まれていてもトランジスタＱ１には常
に一定電流が流れ、高周波成分を除去し得る。The transmission digital signal C taken out from the D flip-flop 14 is supplied to the control driver 17, and the control driver 17 is turned on when the logic code of the transmission digital signal C is "1". Q1 is turned off. Conversely, the control driver 17 is turned off when the logic code of the transmission digital signal C is "0", and as a result, the constant current limiting resistor 19 (Ra) is output from the constant voltage circuit 18.
, a constant current flows through diode 20, and transistor Q1 is turned on. In this case, the constant voltage circuit 18 and the constant current limiting resistor 19 cause a constant current to always flow through the transistor Q1 no matter what high frequency components are included in the transmitted digital signal C, and the high frequency components can be removed.
トランジスタＱ＋のオン、オフ動作によって受信側回路
１１には負荷抵抗２１ （Ｒｂ）伝送線２８ａ、２８ｂ
を介して一定電流が流れ、出力端子２２ａ、２２ｂより
受信デジタル信号ｄ（同図（Ｄ）〉として取出される。Load resistance 21 (Rb) and transmission lines 28a and 28b are added to the receiving circuit 11 by the on/off operation of transistor Q+.
A constant current flows through the output terminals 22a and 22b and is output as a received digital signal d ((D) in the same figure).
ここで、受信デジタル信号ｄの論理符号ｒ１ＪｒＯＪは
伝送デジタル信号ａの論理符号［１Ｊ ｒＯＪと同一
である。このように、伝送デジタル信号ａの波形の高周
波成分及びジッタ成分が微小に変化してもその論理符号
ｒｌＪ ｒＯＪが変化しない限り常に波形一定の受信
デジタル信号ｄを取出し得る。Here, the logical code r1JrOJ of the received digital signal d is the same as the logical code [1J rOJ of the transmitted digital signal a. In this way, even if the high frequency component and jitter component of the waveform of the transmitted digital signal a slightly change, the received digital signal d with a constant waveform can always be extracted as long as its logical code rlJ rOJ does not change.
なお、原信号発生器１５、タイミング制御信号発生土１
６等を用いる代りに、第３図に示す如く、同期信号生成
回路２３にて伝送デジタル信号ａから同期クロックｂを
生成するようにしてもよい。In addition, the original signal generator 15, the timing control signal generator 1
6 or the like, the synchronization clock b may be generated from the transmission digital signal a in the synchronization signal generation circuit 23, as shown in FIG.
この場合、同期信号生成回路２３にＰＬＬを設けて伝送
デジタル信号ａに同期させてその数倍の周波数を発生さ
せ、これを分周してジッタ成分に追従しない同期クロッ
クｂを得るようにする。In this case, a PLL is provided in the synchronization signal generation circuit 23 to synchronize with the transmission digital signal a to generate a frequency several times that frequency, and divide this to obtain a synchronization clock b that does not follow the jitter component.
又、原信号発生器１５は伝送側回路１０以外の部分に設
けるようにしてもよい。Further, the original signal generator 15 may be provided in a part other than the transmission side circuit 10.
第４図は本発明回路の第２実施例のブロック系統図を示
し、同図中、第１図と同一構成部分には同一番号を付し
てその説明を省略する。このものは、ジッタ成分を除去
する手段及び原信号発生器１５を受信側回路２５に設け
た実施例であり、受信側回路２５から結合部２６のトラ
ンジスタＱ２を介して同期信号を送って伝送側回路２４
と受信側回路２５とを同期状態に保持する。FIG. 4 shows a block system diagram of a second embodiment of the circuit of the present invention, in which the same components as those in FIG. 1 are given the same numbers and their explanations will be omitted. This is an embodiment in which a means for removing jitter components and an original signal generator 15 are provided in the receiving circuit 25, and a synchronizing signal is sent from the receiving circuit 25 via the transistor Q2 of the coupling section 26 to the transmitting side. circuit 24
and the receiving side circuit 25 are maintained in a synchronized state.
同図において、タイミング制御信号発生器１６によって
作られた同期信号は結合部２６のトランジスタＱ２を介
してデジタル信号同期化制御回路１３に供給され、これ
により、伝送デジタル信号ａは第５図（Ａ）に示すタイ
ミングを以て出力される。In the figure, the synchronization signal generated by the timing control signal generator 16 is supplied to the digital signal synchronization control circuit 13 via the transistor Q2 of the coupling section 26, whereby the transmission digital signal a is transmitted as shown in FIG. ) is output at the timing shown in FIG.
ここで、伝送デジタル信号ａ（第５図（Ａ））の論理符
号が「１」の場合の動作について説明する。伝送デジタ
ル信号ａは制御用ドライバ１７に供給され、これをオン
にする。これにより、結合部１２のトランジスタＱ１は
オフとされ、受信側回路２５のタイミング制御信号発生
ｉ！Ｓ１６から取出される同期クロックｂに同期したタ
イミングのドライバ制御信号によって制御用ドライバ２
７がオンとなっても電ＭＳから９荷抵抗２１に電流は流
れない。従って、Ｄフリップフロップ１４のＤ入力ｅ（
第５図（Ｂ））の論理符号は「１」となり、同期クロッ
クｂ（同図（Ｃ））によってＤフリップフロップ１４の
Ｑ出力ｄ（同図（Ｄ））は論理符号「１」となる。Here, the operation when the logical code of the transmission digital signal a (FIG. 5(A)) is "1" will be explained. The transmission digital signal a is supplied to the control driver 17 and turns it on. As a result, the transistor Q1 of the coupling section 12 is turned off, and the timing control signal i! of the receiving side circuit 25 is generated. The control driver 2 is controlled by a driver control signal synchronized with the synchronization clock b extracted from S16.
Even if 7 is turned on, no current flows from the electric MS to the 9-charge resistor 21. Therefore, the D input e(
The logic code in FIG. 5(B)) becomes "1", and the Q output d of the D flip-flop 14 (FIG. 5(D)) becomes the logic code "1" due to the synchronous clock b (FIG. 5(C)). .
この状態では、伝送側回路２４、受信側回路２５間に電
流は流れない。In this state, no current flows between the transmission side circuit 24 and the reception side circuit 25.
次に、伝送デジタル信号ａの論理符号がｒＯＪの場合の
動作について説明する。伝送デジタル信号ａは制御用ド
ライバ１７に供給され、これをオフにする。これにより
、トランジスタＱ１は定電圧回路１８、定電流制限用抵
抗１つを介して流れる電流によりオンとされる。このと
き、前述のように制御用ドライバ２７がオンとなると、
この・オン期間のみ電源Ｂから負荷抵抗２１に電流が流
れる。従って、Ｄフリップ７０ツブ１４のＤ入力ｅ（第
５図（Ｂ））の論理符号は「ｏ」となり、同期クロック
ｂ（同図（Ｃ））によってＤフリップフロップ１４のＱ
出力ｄ（同図（Ｄ））は論理符号ｒＯＪとなる。Next, the operation when the logical code of the transmission digital signal a is rOJ will be explained. The transmitted digital signal a is supplied to the control driver 17 and turns it off. As a result, the transistor Q1 is turned on by the current flowing through the constant voltage circuit 18 and one constant current limiting resistor. At this time, when the control driver 27 is turned on as described above,
Current flows from the power supply B to the load resistor 21 only during this ON period. Therefore, the logic code of the D input e (FIG. 5(B)) of the D flip-flop 70 tube 14 is "o", and the Q of the D flip-flop 14 is
The output d ((D) in the figure) becomes a logical code rOJ.
この状態では、受信側回路２５の電源Ｂから負荷抵抗２
１、トランジスタＱ１のコレクタ・エミッタ、制御用ド
ライバ２７を介して電流が流れるが、トランジスタＱ１
に流れる電流は、定電圧回路１８及び定電流制限用抵抗
１９によって一定であるため、受信側回路２５の電源Ｂ
から流れる電流は一定である。従って、伝送デジタル信
号ａの波形に高周波成分があってもその論理符号「１」
ｒＯＪが変化しない限り常に波形一定の受信デジタル信
Ｓ ｄを取出し得る。In this state, the load resistor 2 is connected to the power supply B of the receiving circuit 25.
1. Current flows through the collector/emitter of transistor Q1 and the control driver 27, but
Since the current flowing in the receiving side circuit 25 is constant due to the constant voltage circuit 18 and the constant current limiting resistor 19,
The current flowing from is constant. Therefore, even if there is a high frequency component in the waveform of the transmitted digital signal a, its logic code is "1".
As long as rOJ does not change, a received digital signal Sd with a constant waveform can always be extracted.
なお、伝送側回路２４と受信側回路２５との結合にはト
ランジスタの他、ＦＥＴ等これと同等の動作をするもの
なら何でもよい。It should be noted that the connection between the transmission side circuit 24 and the reception side circuit 25 may be made of anything other than a transistor, such as an FET, as long as it operates in the same manner as the transistor.
一発明の効果
本発明回路によれば、伝送デジタル信号に高周波成分や
ジッタ成分等の微小な不要成分がｆ畳されていても伝送
デジタル信号の論理符号に応じた常に波形一定の受信デ
ジタル信号を得ることができる等の特長を有する。Effects of the Invention According to the circuit of the present invention, even if minute unnecessary components such as high frequency components and jitter components are folded into the transmitted digital signal, the received digital signal always has a constant waveform according to the logical code of the transmitted digital signal. It has the following features:
第１図及び第２図は夫々本発明回路の第１実施例のブロ
ック系統図及び信号波形図、第３図は本発明回路の第１
実施例の実施例の要部のブロック系統図、第４図及び第
５図は夫々本発明回路の第２実施例のブロック系統図及
び信号波形図、第６図及び第７図は従来回路の各個のブ
ロック系統図である。
１０．２４・・・伝送側回路、１１．２５・・・受信側
回路、１２．２６・・・結合部、１３・・・デジタル信
号同期化制御回路、１４・・・Ｄフリップフロップ、１
５・・・原イｇ号発生器、１６・・・タイミング制御信
号発生器、１７．２７・・・制御用ドライバ、１８・・
・定゛電圧回路、１９・・・定電流制限用抵抗、２０・
・・ダイオード、２１ ・・・負荷抵抗、２２．２２ａ
、２２ｂ・・・出力端子、２３・・・同期信号生成回路
、２８ａ。
２８ｂ・・・伝送線。1 and 2 are block diagrams and signal waveform diagrams of the first embodiment of the circuit of the present invention, respectively, and FIG. 3 is a diagram of the first embodiment of the circuit of the present invention.
4 and 5 are block diagrams and signal waveform diagrams of the second embodiment of the circuit of the present invention, respectively. It is a block system diagram of each individual. 10.24... Transmission side circuit, 11.25... Receiving side circuit, 12.26... Coupling section, 13... Digital signal synchronization control circuit, 14... D flip-flop, 1
5... Original i-g generator, 16... Timing control signal generator, 17.27... Control driver, 18...
・Constant voltage circuit, 19...constant current limiting resistor, 20・
...Diode, 21 ...Load resistance, 22.22a
, 22b... Output terminal, 23... Synchronization signal generation circuit, 28a. 28b...Transmission line.
Claims (4)
して受信側回路に伝送して取出すインタフェース回路に
おいて、上記伝送側回路に、上記伝送デジタル信号に重
畳されるジッタ成分を除去して取出すジッタ成分除去手
段と、該ジッタ成分除去手段の出力信号に重畳される高
周波成分を除去し上記伝送線を経て上記受信側回路に取
出す高周波成分除去手段とを設け、上記伝送デジタル信
号に該高周波成分及びジッタ成分が重畳されていてもそ
の論理符号が変化しない限り上記受信側回路から取出さ
れる受信デジタル信号波形を常に一定レベルにするよう
に構成したことを特徴とするインタフェース回路。(1) In an interface circuit that transmits a transmission digital signal from a transmission side circuit to a reception side circuit via a transmission line and extracts it, the jitter component superimposed on the transmission digital signal is removed and extracted from the transmission side circuit. A jitter component removing means and a high frequency component removing means for removing a high frequency component superimposed on the output signal of the jitter component removing means and extracting the high frequency component to the receiving circuit via the transmission line are provided, and the high frequency component is removed from the transmitted digital signal. and an interface circuit configured to always maintain a received digital signal waveform taken out from the receiving side circuit at a constant level as long as its logical sign does not change even if a jitter component is superimposed.
データとし、該ジッタ成分のタイミング以外のタイミン
グで発生するクロックを用いて該ジッタ成分の除去され
た伝送デジタル信号を得るＤフリップフロップであり、
該高周波成分除去手段は、該Ｄフリップフロップの出力
信号により動作されて該伝送線に一定電流を流す定電流
制御回路であることを特徴とする特許請求の範囲第１項
記載のインタフェース回路。(2) The jitter component removing means is a D flip-flop that uses the transmitted digital signal as data and uses a clock generated at a timing other than the timing of the jitter component to obtain the transmitted digital signal from which the jitter component has been removed. ,
2. The interface circuit according to claim 1, wherein said high frequency component removing means is a constant current control circuit that is operated by the output signal of said D flip-flop and causes a constant current to flow through said transmission line.
して受信側回路に伝送して取出すインタフェース回路に
おいて、上記受信側回路に、上記伝送デジタル信号に重
畳される高周波成分を除去する手段を設け、上記受信側
回路に、上記伝送線を経て入来した上記伝送デジタル信
号に重畳されるジッタ成分を除去して取出す手段を設け
、上記伝送デジタル信号に該高周波成分及びジッタ成分
が重畳されていてもその論理符号が変化しない限り上記
受信側回路から取出される受信デジタル信号波形を常に
一定レベルにするように構成したことを特徴とするイン
タフェース回路。(3) In an interface circuit that transmits and extracts a transmission digital signal from a transmission side circuit to a reception side circuit via a transmission line, the reception side circuit is provided with means for removing high frequency components superimposed on the transmission digital signal. and a means for removing and extracting a jitter component superimposed on the transmission digital signal that has entered through the transmission line, in the receiving circuit, the high frequency component and the jitter component being superimposed on the transmission digital signal. An interface circuit characterized in that the received digital signal waveform taken out from the receiving side circuit is always kept at a constant level as long as its logical sign does not change.
信号により動作されて該伝送線に一定電流を流す定電流
制御回路であり、該ジッタ成分を除去する手段は、該伝
送線を経て入来した信号をデータとし、該ジッタ成分の
タイミング以外のタイミングをクロックとして該ジッタ
成分を除去された該受信デジタル信号を出力するＤフリ
ップフロップとよりなることを特徴とする特許請求の範
囲第３項記載のインタフェース回路。(4) The means for removing the high frequency component is a constant current control circuit that is operated by the transmission digital signal to flow a constant current through the transmission line, and the means for removing the jitter component is a constant current control circuit that is operated by the transmission digital signal and causes a constant current to flow through the transmission line. Claim 3, characterized in that the device comprises a D flip-flop that outputs the received digital signal from which the jitter component has been removed, using a received signal as data and a timing other than the timing of the jitter component as a clock. Interface circuit as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61175511A JPH0669184B2 (en) | 1986-07-28 | 1986-07-28 | Interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61175511A JPH0669184B2 (en) | 1986-07-28 | 1986-07-28 | Interface circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6333040A true JPS6333040A (en) | 1988-02-12 |
| JPH0669184B2 JPH0669184B2 (en) | 1994-08-31 |
Family
ID=15997327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61175511A Expired - Lifetime JPH0669184B2 (en) | 1986-07-28 | 1986-07-28 | Interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669184B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5307907A (en) * | 1991-06-11 | 1994-05-03 | Atsugi Unisia Corporation | Hydraulic damper |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5580943A (en) * | 1978-12-15 | 1980-06-18 | Matsushita Electric Works Ltd | Repeater for private line multiple transmission device |
-
1986
- 1986-07-28 JP JP61175511A patent/JPH0669184B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5580943A (en) * | 1978-12-15 | 1980-06-18 | Matsushita Electric Works Ltd | Repeater for private line multiple transmission device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5307907A (en) * | 1991-06-11 | 1994-05-03 | Atsugi Unisia Corporation | Hydraulic damper |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0669184B2 (en) | 1994-08-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |