JPS633280A - Testing and evaluating device for semiconductor integrated circuit - Google Patents

Testing and evaluating device for semiconductor integrated circuit

Info

Publication number
JPS633280A
JPS633280A JP61147523A JP14752386A JPS633280A JP S633280 A JPS633280 A JP S633280A JP 61147523 A JP61147523 A JP 61147523A JP 14752386 A JP14752386 A JP 14752386A JP S633280 A JPS633280 A JP S633280A
Authority
JP
Japan
Prior art keywords
relay
circuit
handler
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61147523A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Fukushima
福島 吉幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP61147523A priority Critical patent/JPS633280A/en
Publication of JPS633280A publication Critical patent/JPS633280A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To improve operation efficiency by providing a means which sends a stop signal of one automatic sorting machine to the operation control part of a testing and evaluating device and a means which varies the wait time of another automatic sorting machine based on the stop signal. CONSTITUTION:Signals from alarm towers 13 and 14 are inputted to an AND circuit 19, whose output is inputted to a signal inverting circuit 20 and a relay 17; and the output of the circuit 20 is further inputted to a relay 18. If a trouble occurs in an automatic handler 3, the towers 13 and 14 which illuminate in case of trouble are utilized to send their signals to a timer circuit, and consequently the relay 17 is turned on and the relay 18 is turned off to disconnect a wait time timer part 4 from a tester start circuit 7, thereby eliminating the waiting time. Consequently, the automatic handler 2 can starts measuring an IC 8 once the IC 8 is set. When the trouble is removed from the handler 3, the tower 14 turns off to turn off the relay 17 and also initialize the relay 18 to the on-state, so that the original set timer is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路(以下ICと呼ぶ)の電気的
特性を辿1定する試験評価装置(以下ICテスタと呼ぶ
)に係9、特に測定開始時期に対するICテスタの待ち
時間回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a test and evaluation device (hereinafter referred to as an IC tester) that traces and determines the electrical characteristics of a semiconductor integrated circuit (hereinafter referred to as an IC)9. In particular, it relates to an IC tester's waiting time circuit for measurement start timing.

〔従来の技術〕[Conventional technology]

近年、IC選別作業においては、ICテスタに2台以上
の自動選別装置(以下オート・)・ンドラと呼ぶ)を具
備し、しかも1台のオート・ハンドラで、多数個のIC
が袋層可能でちυ、且つ2台以上の前記のオート・ハン
ドラが、同時に動作することによシ、IC1個当個当側
定時間を短縮して、作業効率の向上を図っている。この
様な測定検収を多数個同時並列測定と称し、今後もなお
、この傾向は続くであろうと考えられる。
In recent years, in IC sorting work, IC testers are equipped with two or more automatic sorting devices (hereinafter referred to as auto-handlers), and one auto-handler can handle a large number of ICs.
Since the above-mentioned auto-handlers can be stacked, and two or more of the above-mentioned auto-handlers operate at the same time, the time required for each IC is shortened and work efficiency is improved. This type of measurement acceptance inspection is called multiple simultaneous parallel measurement, and it is thought that this trend will continue in the future.

第2図は、現在最も一般的な1台のICテスタに2台の
オート・ハンドラ2.3を具備して、同時並列1j11
.1定を行なっている状態を示すブロック図である。同
図の従来のICテスタ1とオート・ノ・ンドラ2.3と
の関係は、例えばオート・・・ンドラ2にオートハンド
ラ3よ)も早くICが測定部内にセットされた場合、オ
ート・ノ・ンドラ2のスタート回路10から測定準備完
了の信号がテスタ・スタート回路7に伝達されて、ノ・
ンドラの種類ごとに設定されているタイマー15がカウ
ントされる。タイマー15の時間内にオート・ハンドラ
3内のICが測定部にセットされて御]定スタート回路
12からテスタ・スタート回路7に測定準備完了の信号
が送られれば、その時にICの電気的特性試験を開始す
る。しかし、もし設定されているタイマー15の時間内
にオート・ハンドラ3から測定準備完了の信号がこない
場合には、タイマー15の時間経過後に、テスタ・スタ
ート回路7からIC測定回路5に信号が送ら炸て、オー
ト・ハンドラ2だけのICの電気的特性試験を開始する
。オート・ハンドラ内のICの測定が終シ、工Cテスタ
1のIC判定回路6からそれぞれのオート・ハンドラ2
及び3に同時にICの電気的特性試験の判定結果の情報
が伝達されて、ハンドラの収納動作回路9.11が動作
し、測定法ICは収納され、また新してICがオート・
ハンドラ2及び3の測定部にセットされる。この繰シ返
しに二って、同時並列測定が行なわれる。
Figure 2 shows a single IC tester, which is currently the most common, equipped with two auto handlers 2.
.. FIG. 2 is a block diagram showing a state in which constant constant is being performed. The relationship between the conventional IC tester 1 and the auto handler 2.3 in the figure is, for example, the auto handler 2 and the auto handler 3).・A measurement preparation completion signal is transmitted from the start circuit 10 of the tester 2 to the tester start circuit 7, and the
A timer 15 set for each type of driver is counted. If the IC in the auto handler 3 is set in the measurement section within the time set by the timer 15 and a measurement ready signal is sent from the constant start circuit 12 to the tester start circuit 7, then the electrical characteristics of the IC are determined. Start the exam. However, if the measurement preparation completion signal does not come from the auto handler 3 within the set time of the timer 15, a signal is sent from the tester start circuit 7 to the IC measurement circuit 5 after the time of the timer 15 has elapsed. Suddenly, an electrical characteristic test of the IC of auto handler 2 begins. After the measurement of the IC in the auto handler is completed, the IC judgment circuit 6 of the engineering C tester 1 sends a signal to each auto handler 2.
At the same time, information on the judgment result of the IC electrical characteristic test is transmitted to 3 and 3, and the storage operation circuit 9.11 of the handler operates, the measurement method IC is stored, and a new IC is automatically activated.
It is set in the measurement section of handlers 2 and 3. Simultaneous parallel measurements are performed twice in this repetition.

〔発明が解決しようとする問題点〕 しかし、多数個同時並列測定するには、オート・ハンド
ラの種類によシ、ICの供給収納する時間にばらつきが
ある為に、オート・ハンドラごとに待ち時間を設定して
おかなければならないが、同時に動作している2台以上
のオート・ハンドラのうち1台もしくはそれ以上のオー
ト・ハンドラがトラブル等により停止した場合には、現
在動作しているオート・ハンドラは、トラブル等で停止
しているオート・ハンドラのトラブルが解除されるまで
設定した待ち時間の分だけは、毎回測定を開始せずに待
っておかなければならず、効率低下をもたらす要因とな
る等多大な欠点を有している。
[Problems to be solved by the invention] However, in order to perform simultaneous parallel measurement of a large number of ICs, the waiting time for each auto-handler varies depending on the type of auto-handler. However, if one or more of the two or more auto handlers operating at the same time stops due to a problem, etc., the currently operating auto handler should be set. The handler must wait for the set waiting time without starting measurement each time until the trouble of the auto handler that has stopped due to trouble is resolved, which is a factor that reduces efficiency. It has many drawbacks such as:

本発明の目的は、前記欠点を解決し、オート・ハンドラ
の停止時にそのオート・ハンドラの待ち時間を変更し、
作業効率を向上させr、IC製造の工期短縮を可能にし
た半導体集積回路試験評価装置を提供することにある。
The object of the present invention is to solve the above-mentioned drawbacks and to change the waiting time of an auto-handler when the auto-handler is stopped;
An object of the present invention is to provide a semiconductor integrated circuit test and evaluation device that improves work efficiency and shortens the lead time for IC manufacturing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の構成は、半導体集積回路の電気的特性を評価す
る試験評価装置と、2台以上の自動選別装置とを具備し
、前記半導体集積回路の良品、不良品の選別を行う半導
体集積回路試験評価装置において、前記一台の自動選別
装置の停止信号を前記試験評価装置の動作制御部に送る
手段と、前記停止信号に基いて前記他の一台の自動選別
装置の待ち時間を変更する手段とを備えていることを特
徴とする。
The configuration of the present invention includes a test evaluation device for evaluating the electrical characteristics of a semiconductor integrated circuit, and two or more automatic sorting devices, and a semiconductor integrated circuit test for sorting out good products and defective products of the semiconductor integrated circuit. In the evaluation device, means for sending a stop signal of the one automatic sorting device to an operation control unit of the test and evaluation device, and means for changing the waiting time of the other one automatic sorting device based on the stop signal. It is characterized by having the following.

〔実施例〕〔Example〕

次に図面を参照しながら本発明の詳細な説明する。 Next, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の半導体集積回路試験評価装
置を示すブロック図である。同図において、本装置は、
アラーム・タワー13.14からの信号をアンド回路1
9に入力し、この出力を信号反転回路20.リレー17
に入力する。信号反転回路20の出力は、さらにリレー
18に入力される。その他の回路ブロックは、第1図と
同様である。
FIG. 1 is a block diagram showing a semiconductor integrated circuit test and evaluation apparatus according to an embodiment of the present invention. In the same figure, this device is
AND circuit 1 for the signal from alarm tower 13.14
9, and its output is input to the signal inverting circuit 20.9. relay 17
Enter. The output of the signal inversion circuit 20 is further input to the relay 18 . Other circuit blocks are the same as those in FIG.

今、オート・ハンドラ3がトラブルを発生した場合を考
えてみると、従来の第2図ではトラブルが解消するまで
毎回設定されたタイマー15の分だけはオート・ハンド
ラ2は測定を開始できずに待っていなければならないの
に対して、本実施例では、トラブル時に点燈するアラー
ム・タワー13.14を利用してその信号をタイマ回路
に送ることによ)、リレー17をオン、且つリレー18
をオフとして(トラブルが発生していない時はリレー1
7オフ、且つリレー18オン)、待チ時間タイマー部4
をテスタ・スタート回路5から切シ離し、待ち時間をO
にすることができる。これによシ、オート・ハンドラ2
は、ICがセットされ次第、測定を開始することが可能
となる。オート・ハンドラ3のトラブルが解除すれば、
アラーム・タワー14の清澄によシ、リレー17オフ、
且つリレー18オンの初期状態にもどり、もとの設定さ
れたタイマーになる。
Now, if we consider the case where the auto handler 3 has a problem, in the conventional figure 2, the auto handler 2 will not be able to start measurement for the timer 15 set each time until the trouble is resolved. In contrast, in this embodiment, by using the alarm tower 13.14 that lights up in the event of a trouble and sending that signal to the timer circuit), the relay 17 is turned on and the relay 18 is turned on.
(If no trouble occurs, turn relay 1 off.)
7 off and relay 18 on), waiting time timer section 4
is disconnected from the tester start circuit 5 to reduce the waiting time.
It can be done. For this, auto handler 2
The measurement can be started as soon as the IC is set. If the problem with auto handler 3 is resolved,
Clearing of alarm tower 14, relay 17 off,
Then, the relay 18 returns to the initial state of ON, and becomes the original set timer.

以上により、オート・ハンドラのトラブル発生時の待ち
時間を短く変更することによシ、作業効率を向上して生
産設備の効率の向上と共に、IC製造の工期短縮を図る
ことができる。
As described above, by shortening the waiting time when trouble occurs in the auto handler, it is possible to improve work efficiency, improve the efficiency of production equipment, and shorten the IC manufacturing period.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、ICテスタの待
ち時間の制御部にオート・ハンドラからの停止信号を受
けることのできる機能を加えて、その停止信号によ、9
)ラブルの発生したオート・ハンドラの待ち時間を短く
変更し、トラブルが解消してスタート信号が出た場合に
は、もとの待ち時間にもどる機能を有することでオート
・ハンドラのインデックスが大幅に短縮され、作業効率
の向上が期待できるという効果が得られる。
As explained above, according to the present invention, a function that can receive a stop signal from an auto handler is added to the waiting time control section of an IC tester, and the stop signal causes a
) By having a function that shortens the waiting time of an auto handler where a trouble has occurred, and then returning to the original waiting time when the trouble is resolved and a start signal is issued, the index of the auto handler can be significantly increased. This has the effect of shortening the time and improving work efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

笛1図は本発明の一実施例の半導体集積回路試験評価装
置を示すブロック図、第2図は従来の半導体集積回路試
験評価装置を示すブロック図である。 1・・・・・・ICテスタ、2.3・旧・・オート・ハ
ンドラ、4・・・・・・待ち時間タイマー部、5・・川
・IC測定回路、6・・・・・・IC判定回路、7・旧
・・テスタ・スタート回路、8・・・・・・IC,9,
11・・・・・・収納動作回路、10.12・・・・・
・測定スタート回路、13.14・・・・・・アラーム
・タワー、15・・・・・・タイマー、16・・・・・
・グラウンド、17.18・−・・・・リレー、19・
・・・・・アンド回路、20・・・・・・信号反転回路
。 \−−−ン゛ 第? 区
FIG. 1 is a block diagram showing a semiconductor integrated circuit test and evaluation apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit test and evaluation apparatus. 1...IC tester, 2.3...old auto handler, 4...wait time timer section, 5...river IC measurement circuit, 6...IC Judgment circuit, 7. Old... Tester start circuit, 8... IC, 9.
11... Storage operation circuit, 10.12...
・Measurement start circuit, 13.14... Alarm tower, 15... Timer, 16...
・Ground, 17.18...Relay, 19.
...AND circuit, 20...signal inversion circuit. \---N゛th? Ward

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路の電気的特性を評価する試験評価装置と
、2台以上の自動選別装置とを具備し、前記半導体集積
回路の良品、不良品の選別を行う半導体集積回路試験評
価装置において、前記一台の自動選別装置の停止信号を
前記試験評価装置の動作制御部に送る手段と、前記停止
信号に基づいて前記他の一台の自動選別装置の待ち時間
を変更する手段とをそなえていることを特徴とする半導
体集積回路試験評価装置。
A semiconductor integrated circuit test and evaluation device that is equipped with a test and evaluation device that evaluates the electrical characteristics of a semiconductor integrated circuit and two or more automatic sorting devices, and that selects good products and defective products of the semiconductor integrated circuit. means for sending a stop signal of one automatic sorting device to the operation control unit of the test and evaluation device; and means for changing the waiting time of the other automatic sorting device based on the stop signal. A semiconductor integrated circuit test and evaluation device characterized by:
JP61147523A 1986-06-23 1986-06-23 Testing and evaluating device for semiconductor integrated circuit Pending JPS633280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61147523A JPS633280A (en) 1986-06-23 1986-06-23 Testing and evaluating device for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61147523A JPS633280A (en) 1986-06-23 1986-06-23 Testing and evaluating device for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS633280A true JPS633280A (en) 1988-01-08

Family

ID=15432241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61147523A Pending JPS633280A (en) 1986-06-23 1986-06-23 Testing and evaluating device for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS633280A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198273B1 (en) 1996-11-12 2001-03-06 Advantest Corporation IC tester simultaneously testing plural ICS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198273B1 (en) 1996-11-12 2001-03-06 Advantest Corporation IC tester simultaneously testing plural ICS

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