JPS63317986A - Data recording method - Google Patents

Abstract

PURPOSE:To facilitate data interpolation by interleaving a data so as to maximize the minimum value of a burst error interpolation length on the recording position in the data recording direction on a track. CONSTITUTION:In recording digital data having a correlation between adjacent data as one track for a prescribed number of data, the prescribed number of data are shared one by one word to be divided into >=2 systems. An error correction code is generated and added in each system and the data is interleaved so as to maximize the minimum value of the burst error interpolation length when viewed from the recording position of data recording direction on the track. The burst error interpolation length is referred to as the length of the burst error; a distance between maximum adjacent two words for one word interpolation and a distance of maximum three words in case of the two-word interpolation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data recording method suitable for use, for example, when recording digital audio signals on a tape using a rotating head.

[Essentials of invention]

In recording digital data having a correlation between adjacent data as one trunk for each predetermined number of data, the present invention interleaves the adjacent data so that the recording positions in the data recording direction are as far apart as possible. This makes it possible to easily perform data interpolation even when scratches occur parallel to the direction intersecting the data recording direction.

[Conventional technology]

Rotating head type digital audio signal recording method (R
-DAT) is known, but this l? - In the DAT, in order to prevent errors that may occur in the tape and head systems, digital audio data is sent to the left and right channels, respectively, in odd-numbered and even-numbered data L (odd) and L (even), at predetermined intervals. and divided into R (odd) and R (even),
These data are recorded with two-track interleaving as shown in FIG. That is, the first half of the +azimuth trunk TA contains even-numbered data L (even) of the left channel, and the second half contains odd-numbered data R of the right channel.
(odd), and even number data R (even) of the right channel in the first half of the -azimuth trunk TB.

In the second half, odd-numbered data L (odd) of the left channel is recorded.

If such interleaving is applied, even if data in the first or second half of the track cannot be reproduced due to a scratch in the scanning direction (data recording direction) of the rotating head, the data can be reproduced from the odd or even data that could be reproduced. , through interpolation processing,
It becomes possible to restore the data that could not be reproduced. - [Problems to be Solved by the Invention] However, although the above interleaving method can adequately deal with scratches in the data recording direction, it does not provide sufficient countermeasures against scratches in the tape running direction. That is,
If there is a scratch as shown by a in the figure, burst errors will occur in both odd-numbered data and even-numbered data, and interpolation may not be possible.

This invention improves this point.

[Means for solving problems]

In this invention, when digital data having a correlation between adjacent data is recorded as one trunk for each predetermined number of data, the predetermined number of data is distributed one word at a time and divided into two or more systems. In the base,
An error correction code is generated and added, and the data is interleaved so that the minimum value of the burst error length becomes the maximum when viewed from the recording position in the data recording direction on the track. Here, the burst error interpolation length refers to the length of the burst error when interpolation is possible even if a burst error occurs, and in the case of 1-word interpolation, the maximum distance between two adjacent words, Up to 3 if interpolation
3, which is the distance between words. For example, if a predetermined number of words are divided into odd-numbered words and even-numbered words, and the interpolation process is one-word interpolation, the burst error length will be an odd number. Distance lDt between the th word and the recording position Di and D1+1 of the even-numbered word
+t Equal to Dil.

In this case, even if a scratch occurs on the recording medium in a direction that intersects the data recording direction, if the burst error caused in the reproduced data due to this scratch is at a distance of l DI + 1 - Di l, both adjacent data will not have an error. Therefore, one of the erroneous data can be restored by one-word interpolation such as average value interpolation.

[Embodiment] An embodiment of the present invention will be described below, taking as an example a case in which audio digital data is recorded on a tape by a rotary head.

FIG. 1 shows an example of a recording device that implements the method of this invention, and (IL) and (1 together) indicate the left channel (hereafter L
-ch) and right channel (hereinafter referred to as R-ch).

Audio signals through these input terminals (IL) and (IR) are supplied to an A/D converter (2), and each sampling value is converted into, for example, 12-bit digital data (word). In this case, the input audio signal is L
-ch and R-ch, and the A/D converter (2) outputs, for example, L-ch data and R-ch data alternately in a time-division manner.

In this example, as will be described later, 16 digital data words from the A/D converter (2) are included in one block of data, and one track (one field) formed by the rotary head is )
Each block shall be recorded to contain 80 blocks of digital data words.

The digital data from the A/D converter (2) is supplied to the multiplexer (3), and the L-ch and R-ch
Each odd numbered word OD and even numbered word E
It is divided into V.

The odd numbered word OD from this multiplexer (3) is then supplied to the odd numbered word encoder (4). Also, the even numbered word E from multiplexer (3)
V is supplied to the even-numbered word encoder (6) via a delay circuit (5) for five fields.

Encoders (4) and (6) perform intra-field interleaving to scatter data within one track and generate parities P and Q for error correction.

In this case, one block is made up of 16 words, 8 words each of odd-numbered words and even-numbered words, so interleaving is performed every 8 words of these odd-numbered and even-numbered words, and each of these 8 words is Parities P and Q are generated for the words.

The encoder (4) separates the odd-numbered words of L-ch and R-ch into every 8 words, and inputs the input word L1''.
l Rt' +L 3", R3"l L5",
R6”l Lv”+R? ', which is processed as follows.

That is, the word L 1'' + Ri'' is sent to the adder circuit (
34), the word L3°+R3'' is supplied to the adder circuit (34) via the two block delay circuits (13) and (14), and the words Ls' and Rs'' are supplied to the l block delay circuit (15). .

(16) to the adder circuit (34), and the word L v' + Rv' is supplied to the adder circuit (34) without delay.
supplied to The adder circuit (34) performs modulo-2 addition (modulo-2 addition) to generate a parity word Po♂.

Next, the word L1'' that has passed through the delay circuit (11) is supplied as is to the adder circuit (35), and
Word R1'' through 2) is passed through one block delay circuit (1
7) to the adder circuit (35).

Furthermore, delay circuits (13) (14) (15)
Words L3°, R3', L through (16)
5°, R5'' and the output parity word PoD' of the adder circuit (34), and the word L7'' which does not pass through the delay circuit.
Rv' is supplied to the adder circuit (35) through delay circuits (18) to (24) whose delay times are sequentially longer by l blocks than the delay circuit (17).

Also in this addition circuit (35), the addition circuit (
34), addition of (modulo-2) is performed,
A parity QoD' is generated.

Then, the word L1X passed through the delay circuit (11) becomes the output word L1 of this encoder (4), and the word R1'' passed through the delay circuits (12) and (17) is further output to the 8-block delay circuit (25). Output word R1 via
The word L3' passed through the delay circuits (13) and (18) is further made into the output word L3 via the 16 block delay circuit (26), and the word L3' is outputted through the delay circuits (14) and (19).
) through the plotter delay circuit (27) is further outputted as the output word R3 through the plotter delay circuit (27), and the parity word Pa♂ through the delay circuit (20) is further outputted through the 23 plotter delay circuit (27) as the output word R3.
It is output as an output parity word PoD via a block delay circuit (28).

Also, delay circuits (21) (22) (23)
Word L♂+ R6'l L through (24)? '
lR7'' are 37 block delay circuits (29
), 44 block delay circuit (30), 51 block delay circuit (31), 65 block delay circuit (
32) via the output word L5. R5゜L? l
It is considered to be R7.

Furthermore, the parity word IJo from the adder circuit (35)
D1 is outputted as an output parity word QOD via a 59 block delay circuit (33).

Note that the number of delay blocks of each of the block delay circuits (11) to (33) described above and block delay circuits (41) to (48) described later is modulo-80.

In the even-numbered word encoder (6), parities P and Q are generated in the same manner. That is, in the encoder (6), the same parts as in the encoder (4) are given the same reference numerals, but in the encoder (6), the L-ch
and words L2'', R2°+L4''+R4', which are the even-numbered words of R-ch divided into every 8 words.
+L C"+R♂) L8'HR8" is used as an input word, and from this, a parity word PEV and a parity word QEV are generated in the same manner as the encoder (4).

From the above, the generation sequence of parities P and Q generated within one track (one field) is the same for odd data words and even data words, and expressed in terms of the number of blocks is as follows.

Word number 0123456789P series 0
9 18263442505873QMri 0
8 16 23 30 37 44 51 65 59
O However, in this encoder (6), the delay circuit (11) ~
(16) and delay circuits (41) to (48) with equal delay lengths are inserted after the input end of the word L e'I Rs'', so the even numbered output word L2 + R2
+L4.

The output time of R4, LC, RG, LS + Re and the parity word PEVIQEV is the odd output word LX + Rt + L3 + from the encoder (4).
R3+L6. R5, Lt, Rt and parity word PoD+ (from the output point of loD, the block delay circuit (
41) to (48) are shifted by the number of delay blocks DL.

Here, in this example, the number of delay blocks DL of the block delay circuits (41) to (48) is set so that the length for l-word interpolation (for example, average value interpolation) can be maximized. is selected to be a value for shifting the rotation head in the scanning direction of the rotary head.

The number of delayed blocks is also affected by the block length of the field and the generation sequence of parities P and Q, and is not generally determined. However, it is relatively easy to select the optimal value by giving these values appropriately, for example, by calculating using a computer.

In this embodiment, DL=53 blocks.

The eight data words Ll, R11L3 . from encoder (4) thus obtained. R3, LS, R5゜Lt,
Rv, two parity words PoD, and OD are supplied to a block data generation and field data generation circuit (7). Also, eight data words L2 . R2, L4. R4, Ls.

RG, LS, Re and two parity words PEV.

QP:v is also supplied to this generation circuit (7).

In this generation circuit (7), both encoders (
4) A data block as shown in FIG. 2 is constructed from the data words from 16). That is, the odd-numbered words and the even-numbered lower words are arranged alternately for each bear of the L-ch and R-ch, and the parity POD.

floD+ PEV and QEV are given before that.

And before that, block address data Address
s is added, and sync data 5YNC is added before that.

Also, from the block address data Address,
A CRC code for error detection of 24 bits is generated and added to words up to word R8.

Furthermore, this generation circuit (7) adds control blocks and the like to the 80 data blocks to construct data for one field.

The data for l fields obtained in this way is converted into serial data by a parallel-serial conversion circuit (8),
In the recording modulation circuit (9), modulation for recording and reproduction is performed, and the rotary head (
10) and sequentially recorded on the tape as one diagonal trunk per field.

FIG. 3 shows the eight odd and even words and the parity words PoD, Qoa and Pt! for each. It shows the relative recording positional relationship of v and Qgv in the data recording direction (trunk longitudinal direction), and the numerical value in the vertical direction shows the number of blocks. In the figure, the position indicated by the Δ mark is the data word recording position (different from the actual position), the polygonal line (50) indicates the PI3 series for odd-numbered words, and the polygonal line (51) also indicates the Q series. , P and Q sequences for even-numbered words are omitted.

As is clear from the figure, in this case, the minimum value of the burst error length is 27 blocks, and if the burst error is shorter than 27 blocks, one-word interpolation, for example, average value interpolation can be performed.

In the illustrated example, the following effects are achieved by providing the delay circuits (11) to (16).

That is, without these delay circuits (11) to (16), when error correction of odd-numbered words becomes impossible due to parity PoD+Qoo, interpolation is performed using even-numbered words, but the interpolated data is Eight out of 16 consecutive samples resulted in quality deterioration. However, if delay circuits (11) to (16) are present, each sample of interpolated data becomes one sample out of 16 other samples, so quality deterioration can be minimized. .

Furthermore, in the illustrated example, the odd-numbered word and the even-numbered word are separated by 5 fields, that is, 5 tracks, so that they are resistant not only to scratches in the running direction of the tape but also to scratches in the longitudinal direction of the tracks. Note that the delay amount of the delay circuit (5) does not have to be 5 fields, but only needs to be equal to or larger than the ■ field.

Note that in the above example, the odd-numbered words and even-numbered words were recorded by shifting them in the longitudinal direction of the track so as to maximize the length that could be interpolated by one word, but one-word interpolation was not possible. , two-word interpolation (for example, word L1
and L4 to interpolate words L2 and L3), and if 2-word interpolation is not possible, perform 3-word interpolation (for example, interpolate words L21 L3 + L4 from words L1 and L5). The present invention can also be applied to cases where n-word interpolation is possible. In this case, for example, the highest weight is given to 1-word interpolation, and the weight becomes smaller for 2-word interpolation and below. Alternatively, the maximum value of the minimum value of the optimal burst error interpolation length may be selected.

In addition, the data was divided into two groups, odd numbered and even numbered, but
Parity generation and interleaving processing may be performed by dividing into three or more systems.

Further, the present invention can be applied to the case where an error correction code such as a Reed-Solomon code is generated instead of simple parity P and Q.

Note that the present invention is applicable not only to the recording of audio data but also to any recording of data in which there is a correlation between adjacent data.

〔Effect of the invention〕

According to this invention, since data is interleaved and recorded in the longitudinal direction of the trunk so that the minimum value of the burst error interpolation length is maximized, it is resistant to burst errors caused by scratches in the direction intersecting the longitudinal direction of the track. . In other words, the ability to interpolate erroneous data is enhanced in the longitudinal direction of the track.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a recording system for implementing the method of this invention, FIGS. 2 and 3 are diagrams for explaining the same,
FIG. 4 is a diagram for explaining an example of a conventional method. (4) and (6) are intra-field interleave and parity generation circuits.

Claims (1)

[Claims] A method for recording digital data having a correlation between adjacent data as one track for each predetermined number of data, wherein the predetermined number of data is distributed word by word and recorded into two or more tracks. In each system, a code for error correction is generated and added, and the data is interleaved so that the minimum value of the burst error interpolation length is maximized based on the recording position in the data recording direction on the track. data recording method.