JPS62271535A - Digital signal processing method - Google Patents

Abstract

PURPOSE:To apply error detection and error corection with high probability by using an error correction code so as to correct an error of a data signal and detecting the presence of an error by an error detection code. CONSTITUTION:A CRC encoder 4 and an ORC encoder 5 generate a CRC code being an error check code and an ORC code being an error correction code respectively. The CRC code and the ORC code are fed to a VTR 9 and recorded together with a data signal. Then a reproducing signal from the VTR 9 is fed to an ORC decoder 14 to correct the error of a data signal by the decoded ORC code. Then the presence of an error in the data signal is corrected by the decoded ORC code by the CRC decoder 9. Thus, the presence of the data corrected in error is checked and the error detection/error correction with high probability is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention transmits, for example, error-correctable block codes recorded on a plurality of tracks of a magnetic tape via a single track. The error correction ability is made sufficiently effective against burst errors caused by drop-out I. which cannot be avoided when using a medium.

Further, the present invention is suitable for use when an audio signal is converted into PCM and recorded and reproduced by a magnetic recording and reproducing apparatus using a rotating magnetic head.

There are various error correction codes, but in a multi-trunk fixed head system, ORC (Optimal
A block code called Rectangular Code has been proposed. This means that no matter how long a burst error occurs, it can be completely corrected if it only occurs on one trunk, and if the number of the track where the error occurred can be detected by another method, burst errors on up to two tracks can be corrected. It is something.

The present invention uses such block codes and error detection codes to perform error detection and error correction with high probability.

An embodiment in which the present invention is applied to an apparatus for converting audio signals into PCM and recording and reproducing them using a rotating two-hand VTR will be described below. In Fig. 1, (11 is an input terminal for an audio signal, and (2) is a sampling hold circuit.The sampling output of the sampling hold circuit (2) is outputted by an AD converter (3) as shown in Fig. 2. is converted into parallel 16-bit information bits α1 to α16. However, in FIG. 2, α is omitted and only the suffix number is shown. Information from this AD converter (3) The bits are ORC encoder (4), ORC encoder (5) and parallel to serial converter (
6).

The ORC encoder (4) forms an ORC code consisting of 4 bits αi'lsα18, α13 and α2°. CRC (Cyclic Redundancy)
y Check) is encoded by dividing a code expressed by a polynomial whose coefficients are information bits by a generator polynomial, and adding the remainder to the information bits as an ORC code. If the code is divided by the generator polynomial and the remainder is 0, it is determined that no error has occurred, and if a remainder is generated from something else, it can be detected that an error has occurred.

Note that in this specification, the calculation is based on the calculation of (aod2). That is, (addition) (multiplication) o+o=o o・0=0 1+0=1 1・0−O O+1=1 0・1−0 1+1=0 1・1−1 CRC encoder (4) is a shift register and +mod 2 This can be realized by an adder, but since this example is a parallel process, for example, when the generator polynomial (X) is (x4+x2+1), the ORC codes α17 to α20 can be obtained by performing the following calculations using an adder.

And the ORC code (5) has information bits α1 to α16
One block of ORC in a (6×5) matrix format as shown in FIG. 2 is formed from a total of 20 bits of ORC codes α17 to α20. ORC is generally recorded by a fixed head in parallel so that each row Zo"Zs becomes 6 tracks. It is expressed as here. However, a dash means transposition. Column vectors B1 to B4 are The column vector BO is formed from the information bit node, whereas the column vector BO is Bo = TBx +T' B2 +T3B3 +T'
Defined in B4. Here, T is the column vector Bo by calculating and T4 in advance.
Each bit of is obtained by parallel processing using the following operation.

Further, the 5 bits (a-e) in the sixth row z5 are even-numbered bits for the bits and nodes of the column vector Bo=B4. That is, the parallel-to-serial converter (6) receives the information bits (α, ~α16) from the AD converter (3) and the ORC encoder (4).
) from ORC code (α17 to α20) and 10 bits (A-E and a w e
) is supplied, Zo
.

30 bits serialized in the order of Zx, Z2...z6,
A note code (hereinafter referred to as 1 block) is obtained.

The output of the parallel-to-serial converter (6) is supplied to an interleave circuit (7). The interleave circuit (7) rearranges the serial code from the parallel-to-serial converter (6) and compresses the time axis of the serial code to form a data missing period. realizable. This data missing period is equal to the length of the horizontal and vertical blanking periods of the video signal. Then, the output of the interleave circuit (7) is supplied to the synchronization signal addition circuit (8), and the horizontal synchronization signal in the video signal,
A synchronization signal similar to a vertical synchronization signal and an equivalent pulse is added. In this way, the P signal has the same signal form as the video signal.
The CM signal is supplied to the recording signal input terminal (10i) of the rotating two-head VTR (91). T R ('Ill using PC as is)
This is to make it possible to record and reproduce M signals, and to make recording and reproduction of high-quality audio signals more familiar. In the VTR+91, the PCM signal is recorded via a recording system on a magnetic tape by a pair of rotating magnetic heads as slanted tracks having a length corresponding to the 1 field.

The above-mentioned interleave circuit (7) is for rearranging the array of serial codes, and this rearrangement is performed intermittently within the l-field period as much as possible. In this example, one rearrangement is completed in 35H (H is one horizontal period). 1 field is 262.511
The period during which data can be inserted, excluding the vertical blanking period, is approximately 245H. Therefore 1
Seven rearrangements will be made in the field.

Furthermore, the length of each part is selected as 1■, for example, 2 pro.
A synchronization signal corresponding to the horizontal synchronization signal is added every 7 seconds,
Data processing is performed using this synchronization signal as a time base. Figure 3A shows 35H from parallel-serial converter (6)
A serial code of length I rank (row) Z.

~z5 is shown as a unit, and in this 35H period, 210
1 in the block, K2 ”K21o, so 12
60) A code for rack (-6300 bits) exists.

In the interleave circuit (7), first, as shown by the solid line in FIG.
A first track Zo consisting of bits is selected and arranged in block order, and then a second trunk Z from each of 1 to K 210 in each block is selected and arranged in block order.
1 is selected and arranged in block order, and the third
The th to 6th tracks Z2 to Z5 are 1 in each block.
˜K 2x o and arranged in block order.

Therefore, the output of the interleaving circuit (7) is a collection of 210 trunks from each block and arranged in order, as shown in FIG. 3B.

During playback, the playback signal output terminal (1) of the VTR (9)
A PCM signal having the same format as the video signal as well as the recording signal waveform is obtained from 0o), and the synchronization signal separation circuit (11)
The signal is supplied to the dinterleave circuit (12) via the dinterleave circuit (12).

Based on the synchronization signal separated by the synchronization signal separation circuit (11), clock pulses for the dinterleave circuit (12) and other parts of the reproduction system are formed. In the recording system described above, clock pulses are formed based on the output of the reference oscillator.

De47ter')-P1rjll/& (12) HaP
Rearranging the CM (No. 8) array to the original order and extending the time axis to create a continuous PCM with no data missing period.
It is a signal, and can be realized by RAM like the interleave circuit (7). By using both a clock pulse formed from a synchronization signal having a time axis variation in VTR+91 separated from the reproduced signal and a clock pulse of a constant frequency from an oscillator as a clock pulse in such processing, V
The influence of time axis fluctuations such as jitter in TR+91 can be removed. This dinterleave circuit (1
If the output of 2) is shown for 3511, the third
It is the same as shown in Figure A. and a series-parallel converter (
13) into a parallel code, and then provided to an ORC decoder (14) shown surrounded by a broken line in FIG.

To explain the ORC decoding, from the above encoding, the row vector Zi (t is an integer from 0 to 4) has the following relationship with the column vector Bj (j is an integer from 0 to 4). Now, Zi = (Zlo, Zi1. Zi2. Z
i3. Zi4) Z ij=B ij , and both represent the bit located at (i, j) on the matrix.

Column vector Bj now satisfies equation (3) above.

So, we can define column vector 5(1) as 5(0) ==(1
, O, Q, O, O)', 5(1) -Ti 3 (0
1, the j-th column of matrix TI is s(i
+j-1). Here, formula (3) is: BO+TBl +T2B2 +T3B3 +T' B4
=0"+81, so select in the order of 10, 18, etc. and refer to formula (8). The above formula becomes Zo' +TZ: +T'Z2' 10Tj Z3'
+T'Z4'-0'' (11) holds, and the row vector Zi satisfies this (11) K.

Now, the error pattern is defined as follows.

84 B3 82 BI BO O, 1, 2, 3, 4, 5) as e i= (e+o, 61x, 612. e
i3+ 14) ++++ (12), and when this error is included, △Z i =Z i +e t ” (
13). Any symptoms that appear when a sequence containing this error is received are called syndromes.
(S 10% S 11 S1ha S 13% S 14
)'...(14) = (320,, 521, 522, 823, 824)'
” (15) The above equation (7) and (11
) If an error occurs from the equation, both S and S2 will be 0. Therefore, if an error occurs, =Σei' river・(1(Di
=0, the syndrome S1 can be found by simple addition of all the reproduced rows. That is, syndrome S2 is B at the time of encoding.

can be obtained as follows in the same way as .

Syndrome S2 is a column vector corresponding to the reproduced information focus, B4, B3, B2, 'B1, B.

It can also be formed by giving the feedback shift register, but in order to perform parallel processing, the above-mentioned method is required.

After obtaining the syndromes S1 and B2, the method of correcting the error is divided into the following two cases.

First, when correcting a burst error occurring only in the l trunk, assuming that there is a burst error only in the i-th trunk, the following relationship holds from equations (16) and (17).

S1=ei'" (
20) In this l-trunk-only error correction, 52
=0 means that the parity bit in the sixth row Z5 is incorrect, so the reproduced sequence is used as output data.

On the other hand, when 52=Tel', B
2 by T-1 i times.

That is, as S3=TS2...(22), find i (representing the number of M redo rank) of 51=33, and △Zi'-ZI'+S+...(2
3) By performing the following calculation, the burst error ei is corrected.

Corresponding to the above explanation, the ORC decoder (14) has S1
Forming circuit (15) and 32 and S3 forming circuit (16) and (
A coincidence detection circuit (17) for detecting S1=33) and an error correction circuit (18) are provided.

The error correction circuit (18) receives Bo (A to E) and Z6 (a to
20 information bits except e) (α1 to α20)
is given. For the formation of B3, T-1, T-2, T
By calculating -3, T-4, and T-5, 'l... (27) is supplied to the CRC decoder (19), which is processed in parallel by performing the following addition. CRC decoder (19) inputs information bits α1 to α16 and CRC code α
A polynomial whose coefficients are i7 to α2o is divided by a generator polynomial, and if the 4-bit remainder is ('Pi to P4), each bit can be obtained by the following calculation in the same way as encoding.

If ~P4 are all "0", it is determined that no error has occurred, and if even one bit is "1", it is detected that an error has occurred. This 4-bit output P1~
P4 is supplied to the OR gate (20). Also, in (20), Ss from the match detection circuit (17)
=33, that is, when correction is impossible by ORC, a mismatch detection output that becomes "1" is also supplied. Then, the output of the OR gate (20) is used by the interpolation circuit (
21) is controlled by control 9. This interpolation circuit (21) is supplied with 16 information bits α1 to αlε in parallel, and its output is D.
It is supplied to an A converter (22), and the DA conversion output is guided to an output terminal (24) via a low-pass filter (23).

FIG. 4 shows two examples of the interpolation circuit (21),
In the figure, (31) is the input terminal of clock pulse GK, (3
2) is the supply terminal for the output of (20).

In addition, (33) and (34) are launch circuits, and the parallel 16-bit output U1 of the launch circuit (33) is the latch circuit (
34).

The D input terminal of the 1-bit D flip-flop (33a) of the launch circuit (33) is connected to the terminal (32),
The output terminal of the D flip-flop (32a) is <34a
) is connected to the D input terminal of the The respective outputs QxEt and Q of these 6o flip-flops (33a) and (34a)
2 appears slightly later than the timing of the clock pulse CK. Further, (35) is a data selector consisting of an input selection gate and a latch circuit. The data selector (35) uses the parallel 16-bit output U2 of the latch circuit (34) and a digital average value forming circuit (
36) is selected according to the output N1 of the Nandt gate (37).
When (N 1 = "1"), U2 is output, (N1 =
When it is "0"), U4 is output.

The average value forming circuit (36) is supplied with the parallel 16-bit output U1 of the latch circuit (33) and the output U3 of the data selector (35), so that an average value output U4 of both can be obtained. In addition, the output Q1 of the D flip-flop (33a) is connected to the Nant gate (37) as a knot circuit (38).
) and a D flip-flop (3
The output Q2 of 4a) is supplied. Furthermore, the output N2 of the Nandt gate (39) to which these outputs Q1 and Q2 are given is supplied to the J input terminal of the flip-flop (40) and is also supplied to the input terminal of the flip-flop (40) via the NOT circuit (41). be done. The output Q3 of the flip-flop (40) is supplied to this J- to a Nant gate (42), and a data selector (35) is operated by clock pulses of the output N3 of the Nant gate (42).

The operation of the interpolation circuit (21) having the above configuration is shown in FIGS. 5 and 6.
To explain with reference to the figure, it is assumed that 16-bit information bits, which are PCM signals supplied from the correction circuit (1B), are expressed as m, and are supplied in the order ml m21n3 . First, it is assumed that each of m1 to m4 does not contain an error, and m3 is input to the latch circuit (33) at a timing before the discontinuous clock pulse CKI shown in FIG.
is latched, m2 is latched in the latch circuit (34), ml is latched in the data selector (35), and ml appears as the output U3. Then, m4 is latched by the latch circuit (33) and m3 is latched by the latch circuit (34) by the clock pulse CKI. Since the output of the OR gate (20) supplied to the terminal (32) along with m4 is 0, the output Qz of the D flip-flop (33a) (B in Figure 6) is O, and m3 is also incorrect. Since it is not included,
Output Q2 of D flip-flop (34a) (Fig. 6C)
is also “0”. Therefore, the output N of the Nantes gate (37)
l (Fig. 6D) and the output N2 of the Nant gate (39) become "l", and the output Q3 (Fig. 6E) of the flip-flop (40) at J- becomes "1'", and the data selector (3
5), a clock pulse N3 (FIG. 6F) corresponding to the clock pulse CKI is applied, whereby m2 is latched and appears as an output U3.

If the next information bit m5 contains an error, m5 is latched by the latch circuit (33) and m4 is latched by the latch circuit (34) by the clock pulse CK2. Q is slightly delayed with respect to this clock pulse CK2.
l becomes "1". Also, since Q2 is "0", N1 and N2 are both 1", and Q3 is l", and the clock pulse (N3) corresponding to the clock pulse CK2 is given to the data selector (35), and m3 is This is latched by the data selector (35) and becomes the output U3.

If the next information bit mg is correct, me is latched by the latch circuit (33) and m5 is latched by the latch circuit (34) by the clock pulse CK3. At the timing of this clock pulse CK3, (Q
l−“1”) (Q2="0"), so N1 and N2
are both 1'', therefore Q3 becomes l'', and m4 is latched in the data selector (35) by the clock pulse (N3) corresponding to the clock pulse CK3, which becomes the output U3.

Assume that the next information bit m7 is incorrect.

By clock pulse CK4, m7 is activated as a latch circuit (33
), and me is latched by the latch circuit (34), but at the timing of this clock pulse CK4, which is set to be sent to the average value forming circuit (36) at this time (Ql = "0") ( Q2-"1")
Therefore, N1 becomes 0'', and m5 is latched into the data selector (35) instead.

Furthermore, assuming that the next information bit m8 is also incorrect, me and m7 are latched by the latch circuits (33) and (34), respectively, by the clock pulse CK5, and (
Since Qz="l") (Q2="θ"), m
e is latched by the data selector (35) and output as output U3.

Then, when the next information bit mg (assumed to be correct) is given, me is latched by the latch circuit (33) by the clock pulse CK6, and me is latched by the latch circuit (34). At this time, since Ql and Q2 are both "1', N2 becomes 10", the output Q3 of the flip-flop (40) becomes "0" at J-, and the clock pulse CK6 is sent to the data selector (35). No corresponding clock pulse is given. Therefore, the output U3 remains at me, and a previous value hold operation is performed.

Furthermore, the next information bit m1o (assumed to be correct) is given, and by clock pulse CK7, m1o is latched into the latch circuit (33), and me is latched into the latch circuit (34). At this time (Q 1-“0”) (Q 2-“
1"), N1 becomes "0" and the average value is formed by the data selector (35). If the information given below m 11 m 12... is correct, the clock pulses CK8, CK9 m sequentially by...
s % mto, mtx1m12°°9 is taken as the output U3.

In this way, the interpolation circuit (21) outputs correct information bits as they are, and outputs the average value of the correct information bits before and after the erroneous information bits instead. When certain information bits are consecutive, it operates to hold the previous correct information bit. Of course, in reality, even with ORC, the probability that the error cannot be corrected is extremely low.

According to the present invention described above, error correction codes configured to correct burst errors in the row direction when arranged in a matrix can be serialized and recorded on a single track. In this case, the error correction code is written as ZOZI Z for each block as shown in FIG. 3A.
2...In addition to being serialized with z5, the interleaving circuit (7) allows Zo to be serialized as shown in FIG.
Since the tracks (rows) corresponding to multiple blocks are rearranged so that they are continuous, such as ...zOlzl ...zl, ..., the effects of dropouts are inevitable when using magnetic media. can be significantly reduced. In other words, burst errors due to dropouts that do not exceed the length of the 21O track (□H) are
When configured as C, it becomes a burst error that fits within one track in each block, and can be corrected. If interleaving is not performed while serialization is performed as shown in FIG. 3A, an error in two bits spanning Zo and zl, for example, will result in an error in two tracks. However, with ORC, errors in two tracks can be corrected if the track number where the error occurs can be detected by another method, but considering the complexity of the configuration, it is possible to correct burst errors within one track. This is desirable. Even if the structure is capable of correcting errors in two tracks, only burst errors in two tracks can be corrected. However, as in the above example, the rearrangement is done by 1
If the signal is completed within the field, it is convenient for editing the recorded signal.

In addition, in the present invention, the error detection code (CRC code) is ORed.
Since it is used in combination with C, it has the advantage of greatly increasing the probability of error detection. The present invention converts an audio signal into PCM as in the above-mentioned embodiment, and is suitable for use in a wideband magnetic recording/reproducing device that uses a car-truck as a transmission medium, such as a VTR.

Q In the above embodiment, the audio signal is converted to 16 bits.
Although it has been described that the signal is converted into CM, in the case of a stereo signal, each of the left and right signals is converted into 16-bit PCM.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of an embodiment of the present invention, Figs. 2 and 3 are diagrams used for explaining the same, Fig. 4 is a block diagram of an example of an interpolation circuit, and Figs. 5 and 6 are interpolation circuit diagrams. 4 is a truth table and a time chart used to explain an example of a circuit. (3) is an AD converter, (a is a CRCX7 coder, (5)
is an ORC encoder, (7) is an interleave circuit, (
9) is VTR1 (12) is a dinterleave circuit, (1
4) is an ORC decoder, (19) is a CRC decoder, (
21) is an interpolation circuit, and (22) is a DA converter.

Claims (1)

[Claims] After receiving a transmission signal including a data signal, an error correction code and an error detection code generated from the data signal, and correcting errors in the data signal using the error correction code, the presence or absence of an error is detected using the error detection code. A digital signal processing method characterized by detecting.