JPS63316440A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a trench whose bottom and side walls are not roughened and where a subtrench is not produced by a method wherein a gas of chlorine plus oxygen is used as an etching gas and an etching operation is executed while a deposit mainly composed of silicon dioxide is being deposited on the side walls of the trench. CONSTITUTION:During a process to form a trench 16 in a silicon substrate 11 by a reactive ion etching operation, a gas of chlorine plus oxygen is used as an etching gas; the etching operation is executed while a deposit mainly composed of silicon dioxide is being deposited on side walls of the trench 16. That is to say, the reactive ion etching operation (R.I.E.) is executed in a state that the deposit 17 mainly composed of SiO2 and capable of being resistant to a dry etching operation has been formed on the side walls, mainly at the upper part of the side walls, of the trench 16. By this setup, it is prevented that the bottom and the side walls of the trench are roughened and that a subtrench is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] During silicon trench etching, a vertical or forward tapered sidewall profile is obtained by creating an etch-resistant deposit.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a trench in a silicon substrate.

[Conventional technology]

In the formation of semiconductor devices, trenches are formed by etching to serve as element isolation and capacitive elements on a silicon substrate, and the trenches are processed. More specifically, trenches are formed on a substrate by etching in order to isolate active elements of a semiconductor device on the substrate and to form capacitive elements on the substrate. and,
Carbon tetrachloride (Cα4
), CCRu+02 and reactive ion etching (R,1,E,).

[Problem that the invention seeks to solve]

In trench processing using conventional CfJq or (2)-+02, there are two problems: (1) bottom roughness and sidewall roughness, and (2) sub-trench formation. .

To explain bottom roughness with reference to FIG. 3, bottom roughness refers to the occurrence of needle-like protrusions on the bottom of a trench 22 formed in a silicon substrate 21, as shown in FIG. .

The reason why such needle-like protrusions occur is that carbon (C) 23 contained in the gas used for etching is deposited on the bottom during etching, as shown in FIG. . As etching progresses,
This carbon 23 serves as a mask, and only the empty portions between the carbon 23 where no carbon is deposited are etched as shown by solid lines in the figure. However, as the etching progresses further, the carbon 13 becomes thinner and etched as shown by the dotted line in the same figure, and after the required time elapses, needle-like protrusions are formed, and trenches with such needle-like protrusions cannot be used. I can't.

Regarding sidewall roughness, in etching using CCRu, carbon is also deposited on the sidewalls of the trench, as shown in FIG. 3(C).

If there is a part on the side wall where carbon 23 is not deposited ((dl) in the same figure), radicals and ions generated at R, 1, and E enter the substrate from that part, and the substrate becomes damaged as shown by the dotted line in the figure. After etching R, 1, and E, the shape of the trench becomes as shown in FIG. 3(e).A trench with such rough sidewalls cannot be used.

cci! Hata: 200 (sccm), 02:
20 (sccm), high frequency (RF) electric crab 40
0W, pressure crab 0.05 Torr R, 1, E.

In the experiment, it was confirmed that the bottom and sidewalls of the trench were rough.

The sub-trench will be explained with reference to FIG. 4. In the initial stage of trench formation, ions move straight at R,1,E, so the trench 22 is formed as shown in FIG. 4(a).
It is etched straight as shown by the solid line. R,1
, E, increases, the ion density increases in the area marked with a circle in the figure, and as a result, some of the ions do not go straight but travel in a curved manner, which only creates a taper in the trench 22 as shown in the figure. The shape of the bottom of the trench is shown in the same figure (b
), it becomes an acute angle. This acute-angled portion at the bottom of the trench 22 is called a sub-trench 25, but when such a sub-trench 25 is formed, an electric field is concentrated there, and this electric field concentration has an adverse effect when the trench is used as a capacitive element of a MOS transistor. give.

In a bipolar IC, as shown in FIG. 5, an n1 layer (buried layer) 24 is formed in a silicon substrate.
1st layer 24 has Sb”, As”, P+ 1×IQ
It is formed by ion implantation at a high dose of 15 167C...2, which has poor compatibility with carbon and is difficult for carbon to accumulate there, so as shown in Figure 5, n+
Side etching may occur in the layer 24 as if it were hollowed out. The side etching in this n1 layer is
This is understood to be due to the Fermi level of the n + 9 layer being lowered and the etchant reactivity of the substrate becoming higher.

CCi! 4: 200 (5ccn+), 02
: 10 (sccm), RF: 400W, R, 1, E of pressure crab 0.07 Torr.In the experiment, the occurrence of such sub-trench and side etching was confirmed.

In addition to the above, at R,1,E, a bias of -200V to -700V is applied to the susceptor on which the silicon substrate is placed, and this bias causes carbon to be injected into the substrate by 50V.
This carbon diffuses to a depth of about 0.0 mm and contaminates the silicon substrate, and this carbon causes leakage and electrostatic damage in capacitive elements. Post-treatment annealing cures the substrate contamination caused by carbon to some extent, but the substrate does not completely return to its original state, so the problem of carbon diffusion cannot be ignored.

Furthermore, it has been reported that the etching gas CCeu and its reaction products have an adverse effect on the human body.

The present invention was created in view of these points, and it is an object of the present invention to provide an etching method that achieves an appropriate ratio of trench shapes.

[Means for solving problems]

FIG. 1 is a sectional view of the first embodiment of the present invention, in which 11 is a silicon substrate, 15 is a 5i02 film 12, a Si3Ng film 13,
An etching mask material composed of a PSG film 14, 16 a trench, and 17 a deposit. The mask material is not limited to PSG, and may be metal.

In the first embodiment of the present invention, in the process of forming trenches 16 in silicon substrate 11 by reactive ion etching, [chlorine +
In the second embodiment of the present invention, etching is performed using oxygen] gas while depositing a deposit mainly composed of silicon dioxide on the side wall of the trench 16.
→ If a layer is formed, use [chlorine (α2) boron trichloride (BCe3) decaoxygen (02)] gas,
trench 16 by reactive ion etching
form.

[Effect]

In the first embodiment described above, the dry etching-resistant deposit 17 mainly composed of SiO2 is deposited in the trench 1.
Since R, 1, and E are performed on the sidewalls of No. 6, mainly formed on the upper part of the sidewalls, an appropriate ratio of trench shape is achieved, i.e., a trench with no bottom roughness, sidewall roughness, or sub-trenches. 16 is formed, and in the second embodiment, the deposit is 5i02 plus 8203, which also has dry etching resistance and has the same effect as the first embodiment.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, no n layer is formed on a silicon substrate 11 in anticipation of manufacturing a MOS IC.

For trench formation, we used ci:2+02 gas, which has never been tried before, and used ri2:02#
The flow rate (actual flow rate) and flow rate ratio are 90.0 : 20.0 (sccm), and the pressure is 2.67 Pa (2,Q
X 1O-2Torr), high frequency output is 2.36W
/Ba2 when R,1,E was performed, mainly in the upper part of the side wall of the trench to be etched.
A deposit 17 containing SiO+ as a main component was formed, and by forming this deposit 17, it was possible to obtain a shape in which the trench sidewalls were vertical and no sidewall roughness, bottom roughness, or sub-trenches were generated. The deposits 17 are completely removed by the treatment using hydrochloric acid and water and are not left behind.

When an n+b layer as shown in FIG. 5 is formed on the silicon substrate 11, the SiO2 film 12, the Si3Ng film 13
, PSG 1m! A window 18 is opened in the etching mask material 15 constituted by the etching mask material 14 by ordinary gluing lithography technique, and then a window 18 is opened using (J!2+Bα3+02 gas).
, 1. E.

I do. α2:Bα3: 02-85.7=4.
1: Flow rate (actual flow I) of 19.8 (scca+) and flow rate ratio, pressure is 2.67 Pa (2,OX 10-
Torr) and high frequency output 2.36W/cm', the trench sidewalls are vertical and the sidewalls are rough.
We were able to obtain a shape without bottom roughness or sub-trenches. The reason for using Bα3 gas is that Bα3 gas has low reactivity even when the Fermi level decreases and has high etching resistance.
This is because side etching in the n+i layer can be prevented by adding Bα3 gas that forms the deposit 17 containing 2O2. Note that 5i02 and B103, which are the main components of the deposit 17 in this case, are substances that do not diffuse into the silicon substrate and have no adverse effect on the silicon substrate, and are completely removed by treatment using hydrochloric acid and water after trench formation. It will be removed and will not be left behind.

Ci! mentioned above! 2 + BCi! 3 + 02 Woyo Iru R, 1, 8, 4;! It is used in the manufacture of bipolar ICs in which an n + b layer is formed, and Ba3 is used to prevent the side etching described with reference to FIG. 5.

Next, Ce2 + BCf! I using 3 + 02
? , 1. f! An experiment conducted by the present inventor regarding , will be explained.

FIG. 2(a) is a diagram showing the relationship between etching rate and pressure, and the gas flow rate is BCe 3 : 10 (5CCII
+), CI! 2: 100 (sccm), 02
: 20 (sccm), RF output 60 cm, etching time: 600 sec, the vertical axis shows the etching rate (in/+in), and the horizontal axis shows the pressure (Torr). In the figure, the area to the right of line A is a region where side etching is likely to occur, and the area to the right of line B is a deposition area. Here, the deposition region refers to a region where deposition occurs that does not serve as an etching stop, and where 5i02/1 is deposited on the substrate surface.
It shows an area in which deposits mainly composed of 3203 have been deposited. From the same figure, if the pressure Q is less than QIT Torr, the etching rate will be less than 5000 people/min, which is not practical, and if it exceeds 0.06 Torr, side etching will occur, so 0.02 to 0.06 Torr is the practicable range. It is understood that

Next, Fig. 2 shows the results when changing the displayed flow rates of 02 vs. Bα3.02 vs. Bα2, 2 vs. 8 vs. 3.02 vs. BCl23.02 vs. α2, and 2 vs. Bα3 (bl~(J) Here, the deposition area is as described above, and the flow rates are all directly read from the mass flow meter display, and the actual flow rate conversion is α2! 0.858 407 x display value 02: given by 0.991 x display value.

Since the substrate used had an n + b layer, B
Data for Zheng 3 flow rate = 0 was not collected. Figure 2(b)~
In U), the area surrounded by sandy soil is the effective area, and the criteria for determining effectiveness are: ■Etching speed: 4,000 people/min≦E, R,≦9,000 people/mi
■ No SiO2/Bz03 deposits on the substrate surface, ■ No etching residue due to deposits inside the pattern, ■ No side etching in the n→ layer, ■ No side etching at the bottom of the trench. Therefore, the effective area is the area that can actually be implemented.

〔Effect of the invention〕

As described above, according to the present invention, trench bottom roughness and sidewall roughness can be suppressed, generation of sub-trenches can be suppressed, silicon substrate contamination by reaction products mainly composed of carbon can be avoided, etc. effective.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 (al-0) is a line diagram showing an embodiment of the present invention, and FIGS. 3 to 5 are sectional views of a conventional example. In FIG. 1, 11 is a silicon substrate, 12 is a 5iOz film, 13 is a Si7Ng film, 14 is a PSG film, 15 is an etching mask material, 16 is a trench, 17 is a deposit, and 18 is a window. Agent Patent Attorney Akifuku Agent Patent Attorney Yoshio Suga Nofuyukurou'#1 Bunden Example Son Shigeka Figure 1, 1-Hiro A f + 1 cut t 3rd leap / tren'r 22 Next sting ill included Ika Kopko 1st cow figure 15 μm 1 rainbow puller 5th figure

Claims (2)

[Claims] (1) In the step of forming a trench (16) in a silicon substrate (11) by reactive ion etching, the etching gas is [chlorine (Cl_2) + oxygen (O_
2)] A method for manufacturing a semiconductor device, characterized in that etching is performed using a gas while depositing a deposit (17) mainly composed of silicon dioxide (SiO) on the side wall of a trench (16). (2) The silicon substrate has an n^+ type buried layer formed thereon, and the etching gas further contains boron trichloride (BCl_3). the method of.